GB2113485A - An a.c. supply converter - Google Patents

Description

1

G&2 113 485A 1

SPECIFICATION

An A.C. supply converter

5 This incention relates to a direct a.c. supply converter, that is a converter in which an alternating current power supply input is converted into an alternating current power supply output having different characteristics from the input supply with-10 out passing through an intermediate direct current stage.

A direct a.c. power converter is described and claimed in co-pending British Patent Application No. 80.06636, which converter uses a matrix of bi-15 directional switches having contiguous width-modulated conduction periods to connect the phases of a poly-phase a.c. input supply to output conductors to synthesise the output supply. The switches are operated in a cycle of much higher frequency than 20 the supply frequencies in such a way that each output conductor is connected to only one of the input conductors at a time. A difficulty which arises in the operation of this converter is that the generation of the control signals for the switches involves 25 calculations dependent on the phases of the supplies which means that the characteristics of the output supply cannot be altered easily.

An object of the present invention is to provide an improved a.c. supply converter in which the above 30 difficulty is largely overcome.

According to the present invention there is provided an a.c. supply converter having input conductors for a balanced polyphase a.c. input supply system, output conductors for an a.c. output supply 35 system, a plurality of bidirectional switches which individually connect each input conductor to each output conductor, and a control system connected to operate the switches by a repeating sequence of abutting width modulated pulses, there being the 40 same number of pulses in the sequence as there are phases in the input supply, in such a way that each phase of the input supply is connected in turn to each phase of the output supply and that at any instant one and only one of the switches connected 45 to each of the output conductors is closed, wherein the control system includes a computer programmed to produce a sequence of values representing the widths of the modulated pulses, pulse generators responsive to the values to produce the width 50 modulated pulses and apply them to the switches, and means connected to the input conductors to derive therefrom signals indicative of the phase of the a.c. input supply, which signals are applied to the computer to influence the sequence of values gener-55 ated.

The signals indicative of the phase of the a.c. input supply may be derived in response to the voltage of the supply crossing a particular level, such as zero, and may be applied to an interrupt input of the

60 computerto initiate a program for synchronising the operation of the computer with the time of the crossing. The synchronising program may be a software phase locked loop.

The pulse generators may include means for 65 monitoring the conductive states of the bidirectional switches and a circuitfor interlocking the operation of the switches so that the turning on of a switch coincide with the turning off of the preceding switch. In the case of an overload on the output circuit the 70 bidirectional switches may be unable to be fully turned on and the pulse generators may have an overload detection circuit which compares the period of time taken for each switch to turn on fully with a preset value and if that time is exceeded turns 75 off all the switches.

A default logic circuit may be provided forfeeding equal values to the pulse width modulators should the computer suffer a hardware or software failure preventing the correct operation of the pulse width 80 modulators. When this happens the output voltage is zero.

Although a converter according to the invention is generally useful for providing an output a.c. supply of selected voltage, frequency, relative phase or 85 number of phases from an at least 3-phase input supply, it is particularly applicable to the speed control of an induction motor.

The control system described uses a computer working on-line to provide values representing the 90 pulse widths which are utilised as they are generated to control the pulse width modulators. In an alternative arrangement the computer may be arranged to calculate the values in advance for a whole cycle, which values are then stored and used 95 as required, the computer updating the values whenever a change is required.

In order that the invention may be fully understood and readily carried into effect an embodiment will now be described with reference to the accom-100 panying drawings, of which

FIGURE 1 is a block diagram of the embodiment of the invention;

FIGURE 2 is a circuit of the microcomputer circuit of Figure 1;

105 FIGURES 3 and 4 together show a circuit diagram of each pulse width modulator of Figure 2;

FIGURES 5 and 6 are flow diagrams of the microcomputer program;

FIGURE 7 shows the memory map of the micro-110 computer;

FIGURE 8 shows details of the input data file; and

FIGURE 9 shows examples of the waveforms applied to the switches.

Reference will also be made to Table 1 which 115 shows the program of the microcomputer in detail. The program is written in the assembly code of the microprocessor type TMS 9995 which is the microprocessor used in the embodiment of the invention to

The drawings originally filed were informal and the print here reproduced is taken from a later filed formal copy.

This specification as filed includes a computer programme which is not here reproduced.

2

GB 2 113 485 A

2

be described. The reader is referred to the data manual for this device to enable him to follow the operations performed by the program and to determined the operation codes for the program. 5 The embodiment of the invention as shown in Figure 1 is for converting a 3-phase input supply into a 3-phase output supply, the converter controlling the phase amplitude and frequency of the output supply. The input supply is applied via conductors 1 10 to nine switches S1 to S9 in groups of three as shown and the output supply appears on conductors 2. The operation of the switches is performed in accordance with the principles described in copending British Patent Application No. 80.06636 by a 15 microcomputer circuit 3. Input values indicative of the phase, amplitude and frequency required of the output supply are applied via an input unit 4 to the microcomputer circuit 3. In order that the microcomputer circuit 3 can perform its calculation on the 20 basis of the phase and frequency of the input supply, one predetermined phase of this supply is applied to the circuit 3 via a conductor 5. The microcomputer circuit 3 will be described later with reference to Figures 2,3 and 4 and its program with reference to 25 Figures 5,6,7 and 8. The switches S1 to S9 may take any of the forms described in the above-mentioned co-pending British patent application and, for example, illustrated in Figure 12,16,17,18 or 19 of that application.

30 The microcomputer circuit includes a microprocessor of type TMS 9995 manufactured by Texas Instruments, and the reader is directed to the data manual for this device to improve his understanding of the operation of the circuit to be described. The 35 microprocessor carries the reference 10 and has its eight parallel data terminals connected to the 8-bit data bus 11. The device 10 has sixteen address connections of which ten are connected to an address bus 12. The remaining address terminals are 40 not used in this application. The device 10 has a built in oscillator to which a 12 MHz crystal 13 is connected, which oscillator provides the pulses for the operation of the device 10. A programmable read only memory (PROM) 14 is connected to the data 45 bus 11 and the address bus 12 and provides not only the program for the operation of the device 10 but also a look-up table of cosines, the values of which are used in the calculations performed by the device 10. The input data is applied to the circuit via a buffer 50 store 15, which is connected to both data and address buses 11 and 12. A memory map logic circuit 16 is connected to the address bus and to the PROM 14 and the buffer store 15 to provide chip select signals for those components in accordance 55 with the allocation of memories used in the circuit. Three pulse width modulators 17,18 and 19 are connected to the data bus 11 to receive values representing the widths of pulses to be applied to the switches S1 to S9 to produce the required output 60 supply in accordance with the principles described in the above-mentioned co-pending British patent application. The modulator 17 has outputs connected to switches S1, S2 and S3, the modulator 18 has outputs connected to switches S4, S5 and S6, the 65 modulator 19 has outputs connected to switches S7,

S8 and S9.The addressing of the modulators 17,18 and 19 is effected by a decoder circuit 20 connected to the address bus 12, which decoder has outputs respectively for the modulators 17,18 and 19 which 70 are applied to those modulators via a default logic circuit 21 which operates as described belowto override the control of the modulators 17,18 and 19 by the device 10 in the event of a breakdown which could lead to damage of the switches S1 to S9 or of 75 the devices driven by the output of the converter. The default logic unit 21 is connected to the data bus 11 and receives timing pulses from a time bus 22, which also supplied the timing pulses for the pulse width modulators 17,18 and 19. The time bus 22 is 80 driven by a crystal oscillator 23 controlled by 2 MHz crystal 24. A ready logic circuit 25 is connected to the device 10, the memory logic 16 and the time bus 22 to derive an indication of when the circuit timing is synchronised and provide an indication of this state 85 to the device 10.

Since the calculations to be performed by the device 10 depend on the phase and frequency of the input supply, a sample of the input supply derived from one of the conductors 1 (Figure 1) via a 90 conductor 5 is applied to an integrator 26, the output of which is connected to a comparator 27 and thence to a monostable multivibrator 28. The integrator 26 not only provides a 90° phase shift so that zero crossings detected by the comparator 27 coincide 95 with input voltage peaks which is desirable because of the use of cosines in the calculations, but also confers a measure of noise immunity to the circuit. The multivibrator 28 applies interrupt pulses to the device 10 via a conductor 29 to operate a software 100 phase locked loop included in the program of the device 10.

Before describing the calculations performed by the program, the functions of the various parts of the microcomputer circuit shown in Figure 2 will be 105 discussed. The device 10 reads input data from the buffer store 15, which data represents the voltage, frequency and phase required of the output supply. For a given output supply the phase of the switching signals will clearly depend on the phase of the input 110 supply and it is for this reason that the operation of the device 10 is synchronised with a phase of the incoming supply. Similarly, the output voltage of the converter will depend on the input voltage and the representations of the output voltage takes the form 115 of the relationship of the output voltage to the input voltage. The frequency control data represents the actual output frequency, but, as will be evident from a consideration of the calculations to be described, the device 10 requires an indication of the input 120 supply frequency in order to calculate the pulse widths. This input supply information is derived from the input supply by means of the software phase locked loop.

The PROM 14 operates in a conventional manner 125 to provide the program information for the device 10 and the program makes use of the internal registers provided. If another type of microprocessor is employed, then it may be necessary to provide some random access memory to enable the program to be 130 performed. The program of the device 10 causes it to

3

GB 2 113 485 A

3

address the buffer store 15 when input data is required and to address the pulse width modulators 17,18 and 19 via the decoder 20 when output values have been calculated.

5 The pulse width modulators 17,18 and 19 are of the same construction and each consists of the circuitry shown in detail in Figures 3 and 4. The data bus 11 is connected to two 8-bit latches 50 and 51 which are selected alternately by decoding of the 10 address data on the bus 12 (Figure 2). The values stored in the latches 50 and 51 are transferred to a counter 52 formed of two chips, and pulses of a constant frequency are applied via a conductor 53 to the counter 52 to cause it to count down to zero, an 15 operation which takes a period of time depending on the value transferred into the counter from one of the latches. The end of this period is indicated by a pulse on conductor 54 which is applied to latches 55 and 56, the outputs of which are combined logically 20 to effect the application of the width modulated pulse output of the latches in turn to the three switches to which the particular modulator is connected. The modulator in addition to including the circuitry for producing the width modulated pulses 25 also includes a programmable timing counter 57, the purpose of which is to detect an overload of the switches. This circuit receives state signals from the three switches via conductors 58,59 and 60, which are directed via gates 61 and 62 to the counter 57. 30 When a switch is driven a pulse is transmitted via a gate 63 and the gate 62 which starts the counter 57 and if the state indication from the switch does not indicate that the switch has changed state within a predetermined time set by a number applied to the 35 counter 57 via conductors 64, then this is assumed to be due to the overloading of the switches, for example, due to a short-circuit, and the circuit • produces a trip output to block further conduction of the switches.

40 The state inputs from the switches are also used to ensure that there is no overlap in the conduction apparatus of the switches by holding off the application of a turning on signal to one switch until the preceding switch is turned off. This function is 45 achieved by the gates 75 to 80.

In the pulse width modulators only two data latches 50 and 51 are required because the on time of the three switches connected to each modulator always adds up to a constant interval with the result 50 that only two on times need be specified in each cycle of control of the switches. The period of this cycle of control is determined by signals applied to the modulator from the time base 22 and is typically between 50 and 200 /xs. The operation of the 55 modulator is such that the first switch on-time is stored in the latch 50, the second switch on-time in the latch 51 and the third switch on-time occupies the remainder of the period before the next pulse from the time base 22 via a conductor 81. During the 60 respective switch off times the latches 50 and 51 receive the next input values for the next cycle. The maximum duration of the on-time of any switch is two-thirds of the total cycle period, and this means that at least one-third of the cycle period is available 65 for updating each latch. If the values are not loaded into the latches 50 and 51 during this time, the default logic 21 is arranged to override the control of the modulators by the microprocessor 10 and automatically loads the latches 50 and 51 with values 70 representing one-third of the cycle period which has the effect of making the output voltage of the converter equal to zero. This default logic serves to protect the load whilst the converter is coming into synchronism and, in the event of failure of the 75 microprocessor or a crash of its program. The synchronisation of the program of the processor to the loading times for the loads is achieved by the use of the READY signal provided by the ready logic 25. If the microprocessor 10 completes the calculation 80 routine before this time occurs and is ready to perform a memory write to the pulse width modulator, the ready logic 25 applies a signal to the device 10 which causes it to enter an extended wait state until the ready logic 25 output indicates that the time 85 for loading the value has come. The use of the ready logic in this way has the effect that after a few cycles the timing becomes stabilised, so that the processor enters a wait state on each cycle halting program execution until the calculated values can be loaded 90 into the latches. Immediately after the loading has been effected, the processor 10 resumes the calculations for the next switch interval. The transfer of data requires much less time than is provided by the one-third of the cycle period, so that, if necessary, 95 the transfer can be delayed allowing for interruption of the calculation, for example, to perform the phase locking with the input supply.

As shown in Figure 2, the default logic 21 transmits the address signals for the pulse width modula-100 tors 17,18 and 19 from the decoder 20. The logic 21 includes six latches respectively connected to the six address lines and are set when the corresponding sets of latches in the pulse width modulators are addressed. A gate is provided in the default logic to 105 produce an output if at the end of a cycle all of the latches have not been set. Any failure to address one of the sets of latches in the pulse width modulators will be detected by this arrangement and is used to initiate the fail-safe override to avoid damage to the 110 switches or the load device.

Turning now to the program to be performed by the microprocessor, consideration will first be given to the calculations to be performed in generating the values representing the required pulse widths. From 115 the above-mentioned co-pending British patent application, the theory for the operation of a 3-phase to 3-phase converter can be described in the following terms.

Given a set of input sinusoidal voltages at input 120 frequency:

= vjcos^t)

2

v<2 = v-ioos(<,)it+ j11)

v<3 = v4c°s^a£t* 3»)»

and a set of output sinusoidal currents at output frequency:

4

GB 2 113 485 A

4

zoi ~ C0oos^0t+ V 1oz - c0oos(uot+ §"+ V

Z03 = c0°os(u0t+ |u+ *0),

determine a control law for the switches S11f Sn2,.. S33 so that the low frequency parts of the synthetized output voltages V01, V02, V03, and input currents In, Ii2» Ii3 are sinusoidal with the prescribed output 5 frequency, input frequency, phase and amplitude respectively.

Let now the desired input currents and output voltages be:

f = c^oos

Ii2 = cia°s(u^t+ -^71+

= c^cos(e$t+ -J7T+

'V01 = Vos(V)

= v.cos(u tt In)

with:

V03 * V0S

(Bgt* jir).

According to the existence theorem, the output 10 voltage and input current high frequency synthesis are possible, in this case, only if:

2 0

a2 & 0

0 < q i

In the particular embodiment, the input data is as follows:

20 Output frequency: 12-bit word, say 0 to 1000 Hz = f0 Output amplitude: 8-bit word, range 0 to 0.5 = q Input-Output phase transfer: 5-bit word (4 bits + sian), range -1 to +1 = 0,

Output Phase Set (optional,: 8 bit-word,

25 not in this implementation) range 0 to 2ir/3 = 0O

The input voltage frequency and phase must be obtained from the supply. This is achieved by taking zero crossings in the comparator 27 which causes pulses to be produced by the multivibrator 28

30 applied as interrupts via conductor 29 to the microprocessor 10.

Input voltage = Vj; Output voltage = VQ; so that

= Vo q = ^

Input frequency = fj and Ouput frequency = fQ and v£

vD * -j- and

= 2*^ ;

u = 27lf o o

Furthermore, it is required that:

v0 C' COS 4.

within these limitations, a solution of the system of equations is the following generalized transformer 15 low frequency modulation matrix"m(t):

'1+ 2q CS(0) 1+ 2q CS(-|iO 1+ 2q CS(-|ir)"J 1+ 2q CS(-|jt) 1+ 2q CS(0) 1+ 2q CS(-|ir)|

-r

1+ 2a CS(-|ir) 1+ 2q CS(-|tt) 1+ 2q CS(0)

!1+ 2q CA(0) 1+ 2q CA(-|ir) 1+ 2q CA(-|ir) ' 1+ 2q CA(-|ir) 1+ 2q CA(-|ir) 1+ 2q CA(0) 1+ 2q CA(-yO 1+ 2q CA(0) 1+ 2q CA(-|it)v where:

CS(x) = eosCuwfc+ x] CA(x) = cos[-(<dm+ 2uj^)t+ x]

= a0~ "-t al = C4>0)3

a2 =1 " al

„ - vo

35 The input data file is shown in Figure 8 and indicated in Figure 7. Each memory location indicated is of 1 byte, that is to say 8 bits. The values stored represent 0O, the output phase set value, q and a frequency control value occupying 2 bytes. 40 The value stored in these bytes has 14 significant bits and is a twos complement value in the range 2001 to 1FFF(-8191 to +8191). This value defines the output value frequency as fs fo = -

where fs is the switch rate.

45 Apart from the input data file, the memory map shown in Figure 7 indicates that 256 bytes are provided for storing the program, another 256 bytes store the cosine look-up table and a further 256 bytes are provided by the internal RAM of the microp-50 rocessor, which locations are used in the performance of the calculations. In addition, the memory map includes six bytes forming an output data file and two bytes forming an event counter.

Flow diagrams of the calculations performed by 55 the microprocessor are shown in Figures 5 and 6. The flow diagram A of Figure 5 indicates the main loop of the program which periodically cause the calculation subroutine which is shown in the flow diagram of Figure 6. The flow diagram B of Figure 5 60 illustrates the program used to ascertain whether the microprocessor operation is synchronised and the values being calculated can be used to control the pulse width modulators.

The details of the program itself in the assembly 65 language of the TMS 9995 microprocessor are given in Table 1 which is annotated to indicate the

5

GB 2 113485 A

5

particular functions being performed by the operations.

Figure 9 shows an example of typical width modulated pulses which would be produced by the 5 microcomputer circuit for operating the switches S1 to S9 of the converter. The cycle time Tc is 192 /as, resulting from the use of 2 MHz as the time base frequency, 8 bits to specify each switch pulse duration and the fact that the maximum duration for 10 a switch pulse is 2/3 ofthe cycle time. The maximum duration for a switch pulse is 28 = 256 times 0.5 /u.s 128 /as from which the cycle time Tc = 192 (jls follows.

TABLE 1

************************************************************

PROGRAM CONSTANTS

************************************************************* • *

* ABSOLUTE: ADDRESSES *

* *

PHI

EQU

>1000

*

FCQNT

EQU

>1002

*

OUT1

EQU

>1800

*

0UT2

EQU

>1802

*

OUT3

EQU

>1804

*

*

*

*

WORKSPACE POINTERS *

*

*

UP.

EQU

>F0C0

*

WP2

EQU

WP+26

*

*

*

*

WORKING REGISTER ADDRESSES #

*

*

MO

EQU

WP

ROLSB

EQU

WP+1

R4LSB

EQU

WP+9

R7LSB

EQU

WP+15

R8LSB

EQU

WP+17

R9LSB

EQU

WP+19

R10LSB

EQU

WP+21

*

NUMERIC CONSTANTS

* cosine t*6l& *******************************************************>.

6

GB 2 113 485 A 6

TABLE 1 COST.

»WP NAME #

PRODI PR0D2

EQU EQU

REGISTER UTILISATION WP1 NAME

RO PHI,Q INPUT REGISTER R1 41+PHI) COEFFICIENT R2 tl+PHI)«Q PRODUCT R3 <1-PHI> COEFFICIENT R4 <1-PHI)*Q PRODUCT R5 BL VECTOR STORAGE

R6 MPYS DEST OP AND MSW RESULT REGISTER R7 MPYS LSW RESULT REGISTER

r

COEFF1

EQU

2

RS

<1+PHI)*Q STORAGE REGISTER

C0EFF2

EQU

3

R9

(PHI-1)»Q STORAGE REGISTER

ANGLE

■EQU

4

RIO

ANGLE STORAGE REGISTER

•

EQU

5

Rll

BL RETURN ADDRESS REGISTER

»

EQU

6

R12

CRUBASE

TEMP

EQU

7

TEMPORARY STORAGE REGISTER

ACCUM1

EQU

8

OUTPUT ACCUMULATOR REGISTER 1

ACCUM2

EQU

9

OUTPUT ACCUMULATOR REGISTER 2

ACCUM3

EQU

10

OUTPUT ACCUMULATOR .REGISTER 3

R'ETN

EQU

11

INDEXING REGISTER

UPDATE

EQU

12

INDIRECT ADDRESS STORAGE

* *

WP2 NAMES

LOKFLG

EQU

13

RO

LOCK STATUS FLAG '

DIFF

EQU

14

R1

(WO-WI)T STORAGE

SUM

EQU

15

R2

(-WO-WI)T STORAGE

*R3

R3

(WI*T) STORAGE

*R4

R4

<WI*T> INCREMENT STORAGE

*R5

R5

(WO*T) STORAGE

*R6

R6

<UO*T> INCREMENT STORAGE

*R7

R7

INTERRUPT WORKING REGISTER

AORG

0

DATA

WP,START

RESET VECTOR

DATA

WP2,

ZERO

INTERRUPT VECTOR

START

LIMI

1

SET INT. MASK TO ONE

CLR

R2

INIT. R2

CLR

R3

INIT. R3

IDLE

WAIT FOR INTERRUPT

CLR

R13

CLEAR LOCK FLAG

LWPI

WP2

SELECT WORKSPACE 2

CLR

R7

CLEAR ROLLING ERROR REG,

LI R4»>2AF LOAD 55HZ CENTRE FREQUENCY

LMPI MP-12 SELECT UPDATE WORKSPACE

7

GB 2 113 485 A

7

TABLE 1 CONT.

************************************************************ * *

* UPDATE ROUTINE *

************************************************************

BEGIN

CLR

LI

TB

JEQ

MOV

LI

MOV

AB

BL

SB

MOVB

MPY

BL

R12

R5» CALC 0

END1

ePHI*RO

R1»>7F00

R1»R3

RO»Rl

*R5

ROi R3 R12.R0 R0»R1 *R5

ZERO CRUBASE 4

LOAD BL VECTOR 5

TEST UPDATE INPUT 9

SKIP IF HIGH 4

READ (PHI)»(Q) 5

LOAD WORK CONSTANT (1) 5

COPY TO R3 4

MAKE (PHI+1) IN MSB R1 4

BRANCH TO CALCULATE PROG. 7 TOT= 47

MAKE <1-PHI> IN MSB R3 4

MASK PHI * 4

PRODUCE <Q)*<PHI+1> IN R1 24

BRANCH TO CALCULATE PROG. 7 TOT- 39

END1

END2

MOV MPY MOV BL

TB

JEQ

MOV

BL

JMP

R1.R3 R0.R3 R3»R9 *R5

0

END2

®FC0NT,eWP+26+i:

*R5

BEGIN

COPY <Q)*(PHI+1) TO R2(WP) 4 PRODUCE <Q>*(1-PHI) IN R3 24 COPY <Q>*<1-PHI) TO R3(WP) 4 BRANCH TO CALCULATE PROG. 7

TOT= 39

TEST UPDATE INPUT 9

SKIP IF HIGH 4

READ FREQUENCY CONTROL REG 5 BRANCH TO CALCULATE PROG. 7

START UPDATE AGAIN 4

TOT= 29

************************************************************

TABLE 1 CONT.

* START OF CALCULATION ROUTINE *

* *

tt*********************************************************** * *

* THE CODE THEN HAS TO UPDATE THE INPUT AND OUTPUT PHASE *

* INFORMATION FOR THE NEXT INTEGRATION PERIOD. *

* *

************************************************************ *

CALC

LWPI

WP+26

SELECT UPPER WORKSPACE

5

A

R4»R3

INCREMENT <WI*T>

5

A

R6,R5

INCREMENT CWO*T>

5

MOV

R5» R1

COPY < WO*T) TO R1 .

4

MOV

R5»R2

COPY <WO*T> TO R2

4

NEG

R2

PUT —(WO*T) IN R2

4

•s

R3,R1

MAKE (WO-WI)*J IN R1

5

S

R3» R2

MAKE (—WO-WI)*T IN R2

5

LWPI

WP

SELECT LOWER WORKSPACE

5

LI

R4» >S00

LOAD TABLE START ADDRESS

5

LI

R12»R4LSB

LOAD INDIRECT ADDRESS

5

MOVB

R14,*R12

CONCATENATE-(WI-WO)T & TABLE6

TOT= 53

************************************************************

8

GB 2 113485 A

8

TABLE 1 CONT.

«****■»****##*********##*#*##********#*##****#******##*##****

* *

* THE FINAL PULSE WIDTH VALUES ARE CALCULATED FROM * ♦PARTIAL RESULTS DESIGNATED 1 > 2,3,4,58<6. THESE RESULTS ARE *

♦EVALUATED FROM THE FOLLOWING EQUATIONS. *

* *

* 1=((PHI+1>*Q)*COS(WO-WI>T *

* 2=< (PHI+1) ♦Q)*COS(WO-WI >T-2/3PI *

* 3~((PHI+1>*Q)*COS(WO-WI)T-4/3PI *

* 4=((1—PHI)*Q)*COS(—WO-WI)T ♦

* 5=<<1-PHI)*Q)ttC0S(-W0-UI)T-2/3PI *

* 6=((1-PHI)^Q)*COS<-WO-WI)T-4/3PI *

* *

********♦*♦♦*♦********♦************#**********♦♦************

LI R'S» >7F7F

MOV R3» R9

LI R7,>5500

LI RI1»R3*2+WP

LOAD OFFSET INTO ACCUMULATORS LOAD OFFSET INTO ACCUMULAT0R4 STORE 2/3PI IN R7 5

LOAD OUTPUT ACCUM. ADDRESS 5

CLR RO MOVB *R4» RO DATA >1C2 AB GROLSBi*R11+

TOT— 19

INITIALISE REGISTER 4

LOOKUP COS(WO-W1)T 5

MPYS 2 PRODUCE (1) 26

ADD RESULT TO ACCUMULATOR 7

SB R7,^R12 CLR RO MOVB *R4,R0 DATA >1C2 AB &ROLSB ■> *R11+

MAKE <WO-WI)T—2/3PI IN R4 6

INITIALISE RGISTER 4

LOOKUP COS < WO-WI)T-2/3PI 5

MPYS 2 PRODUCE <2> 26

ADD RESULT TO ACCUMULATOR ?

SB R7,*R12 CLR RO MOVB *R4,R0 DATA >1C2 AB SROLSBi*R11+

MOVB R15,*R12

MAKE (WO-WT)T—4/3PI IN R4 6

INITIALISE REGISTER 4

LOOKUP COS(WO-WI)T—4/3PI 5

MPYS 2 PRODUCE (3) 26

ADD RESULT TO ACCUMULATOR 9 TOT=141

CONCAT. (-WI-WO)T %c TABLE 6

CLR RO MOVB *R4»R0 DATA MC3 MOVB SROLSB»*Rll+

INITIALISE REGISTER 4

LOOKUP COS(-WO-WI)T 5

MPYS 3 PRODUCE (4) 26

COPY RESULT TO ACCUMULATOR 9

SD

R7»*R12

MAKE (-WO-WI>T-2/3PI IN R4 6

CLR RO MOVB *R4»R0 DATA >1C3 MOVB 3R0LSB* *R11 +

INITIALISE REGISTER 4

LOOKUP COS <-WO-WI)T-2/3PI 5 MPYS 3 PRODUCE (5) 26

COPY RESULT TO ACCUMULATOR " 9

SB R7,*R12

MAKE (-WO-WI)T-4/3PI IN R4 6

CLR RO MOVB *R4,R0 DATA >1C3 MOVB fiROLSB* *R11+

INITIALISE REGISTER 4

LOOKUP COS<—WO-WI)T—4/3PI 5 MPYS 3 PRODUCE (6) 26

COPY RESULT TO ACCUMULATOR 9

************************************** a-**************.********

9

GB 2 113 485 A

9

TABLE 1 CONT.

* *

* RESULT COMPLETION ROUTINE *

* *

♦THIS ROUTINE COMPUTES THE PULSE WIDTH VALUES S1.S2.S4.S5 *

* S7 h S3 FROM THE PARTIAL RESULTS 1.2.3.4.5.&6. THE DATA *

* IS FORMATTED AS SHOWN BELOW. *

*

MSB

/

LSB

♦

RS

1

/

2

*

R9

3

/

4

INITIAL FORMAT

*

RIO

5

/

6

*

♦

R7

1

/

2

SAVED RESULTS

*

R3

Sl=l+4

/

S2=2+5

R9 RIO

S7=2+6 S4=3+5

S3=3+4 S5=6+l

COMPLETED VALUES

* * * * ♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦*****************************

MOV

RS.R7

COPY

TO WORKING REGISTER 4

LI

R11»R8*2+WP

LOAD

OUTPUT ACCUM.

START ADD5

AB

SR9LSB.*R11+

MAKE

SI (4+1)

10

AB

RIO.*R11+

MAKE

S2 (5+2)

S

AB

*R11+.*R11+

MAKE

S3 (3+4)

11

AB

R9,*RU+

MAKE

S4 (3+5)

8

MOVB

SR10LSB.R9

COPY

(6) TO R9 MSB

5

AB

R7»♦Rl1

MAKE

S5 (1+6)

6

AB

0R7LSB.R9

MAKE

S7 (6+2)

7

TOT= 64

♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦*********************************

1Q

GB 2 113 485 A 10

TABLE 1 CONT.

************************************************************

* *

* DATA OUTPUT ROUTINE *

* *

************************************************************

LI RiltOUTl LOAD OUTPUT CHIP ADDRESS 5

MOV R8 ? *R11+1 OUTPUT S 1*^32 3

MOV R13.R13 LOCK FLAG SET? 4

JEQ NOLOAD SKIP IF NOT 4

MOV R10,*R11+ OUTPUT S4.S5 8

MOV R9.»R11+ OUTPUT S7.S3 8

NOLOAD LWPI WP—12 SELECT UPDATE WORKSPACE 5

RT 5

* TOT= 47 ************************************************************

* *

* INTERRUPT ROUTINE *

* *

» THIS ROUTINE PERFORMS THE PHASE LOCK FUNCTION »

» REQUIRED FOR PRODUCTION OF THE SUPPLY VOLTAGE PHASE »

» INFORMATION. *

» THIS IS ACHIEVED BY EXAMINING THE VALUE CONTAINED IN »

» THE (WI*T) STORAGE REGISTER WITH A ZERO CROSSING *

* INTERRUPT. WHEN IN LOCK THIS VALUE SHOULD BE CLOSE # » TO ZERO. THE ERROR IS ADDED TO THE PREVIOUS ERROR AND * *. DIVIDED BY TWO TO PRODUCE A ROLLING AVERAGE ERROR *

* WHICH IS THEN USED TO MODIFY THE ANGLE INCREMENT. * » ENSURING THAT THE ERROR IS SMALLER AT THE TIME OF THE *

* NEXT INTERRUPT. THE ERROR SHOULD THUS TEND TOWARDS ZERO »

» AFTER A NUMBER OF INTERRUPTS. WHEN THE ERROR IS LESS *

» THAN +/- 2 THE SYSTEM IS DECLARED IN LOCK AND THE FLAG *

» SET. CONVERSELY IF THE ERROR IS GREATER THAN +/- 2 »

» THE FLAG IS RESET. *

» THE ANGLE COUNT IS RESET TO ZERO AFTER THE ABOVE *

* PROCESSING. *

* *

»»**#»**********»»*»#*»*»»**»***»**»********»*»»»»»*»,»*****

» 14

ZERO SRA R3,8 DIVIDE ERROR BY 256 14

A R3.R7 ADD TO PREVIOUS ERROR 5

SRA R7,l DIVIDE BY TWO FOR MEAN ERROR 7

S R7.R4 MODIFY INCREMENT 5

ABS R3 MAKE ERROR POSITIVE 4

CLR RO CLEAR LOCK FLAG 4

CI R3.4 IN LOCK? 6

JGT NOLOK EXIT WITH FLAG CLEARED 4

SETO RO SET LOCK FLAG 4

NOLOK CLR R3 CLEAR ANGLE COUNT 4

RTWP 7 6W»

Although the invention has been described with reference to a specific embodiment it will be appreciated that many other embodiments are possible. For example, the input supply may have more than three 5 phases and the output supply may be d.c. or a.c. of any number of phases. Moreover, the various clock and switching frequencies may be modified to suit other embodiments and applications.

Claims (14)

10 1. An A.C. supply converter having input conductors for a balanced polyphase A.C. input supply system,

output conductors for an A.C. output supply system,

15 a plurality of bidirectional switches which individually connect each input conductor to each output conductor, and a control system connected to operate the switches by a repeating sequence of abutting width 20 modulated pulses, there being the same number of pulses in the sequence as there are phases in the input supply, in such a way that each phase ofthe input supply is connected in turn to each phase of the output supply and that at any instant one and 25 only one ofthe switches connected to each ofthe output conductors is closed,

wherein the control system includes a computer programmed to produce a sequence of values representing the widths ofthe modulated 30 pulses.

pulse generators responsive to the values to produce the width modulated pulses and apply them to the switches,

and means connected to the input conductors to 35 derive therefrom signals indicative ofthe phase of the A.C. input supply, which signals are applied to the computer to influence the sequence of values generated.

2. A converter according to claim 1, wherein the 40 sequence of width modulated pulses is repeated at a constant frequency much higher than the input and output supply frequencies.

3. A converter according to claim 2, wherein the computer calculates the values for all but one pulse

45 in the sequence and the pulse generators are arranged to produce the remaining pulse in a sequence to fill the period ofthe constant frequency.

4. A converter according to claims 1,2 or 3 wherein the means connected to the input conduc-

50 tors to derive signals indicative ofthe phase ofthe input supply includes circuit means responsive to the waveform of the voltage on a single input conductor to produce an output pulse when the voltage waveform crosses a particular voltage level. 55

5. A converter according to claim 4 wherein the particular voltage level is zero.

6. A converter according to claim 4 or 5 wherein the output pulses from the circuit means are applied to an interrupt input ofthe computerto initiate a 60 program for synchronising the operation ofthe

computer with the instants ofthe voltage waveform crossing the particular voltage level.

7. A converter according to claim 6, wherein the synchronising program is a digital phase locked

5 loop.

8. A converter according to claim 7, wherein the phase locked loop includes the steps of examining a stored digital value representing the input supply phase at the time ofthe interrupt, forming the to average ofthe value and the corresponding value at the previous interrupt and modifying the stored digital value so as to tend to bring it into agreement with the input supply phase.

9. A converter according to any preceding claim, 15 wherein the pulse generators include means for monitoring the conductive states ofthe bidirectional switches and an interlocking circuit responsive to the monitoring means for controlling the operation ofthe 20 switches so thatthe turning on of a switch coincides with the turning off ofthe previously conducting switch.

10. A converter according to any preceding claim, wherein the pulse generator include an over-

25 load detection circuit having means for comparing the period of time taken for each switch to turn on fully with a preset value and means for turning off all ofthe switches if the period of time for any switch exceeds the preset value.

30

11. A converter according to any preceding claim, wherein the control system includes a default logic circuit responsive to a hardware or software failure likely to prevent the correct operation of the pulse width modulators to feed equal values to all 35 the pulse width modulators so that the width modulated pulses are alt of equal duration.

12. A converter according to any preceding Glaim wherein the computer is programmed to calculate the values of the pulse widths as they are required. 40

13. A converter according to any of claims 1 to 11 wherein the computer is programmed to calculate the values ofthe pulse widths in advance for a whole cycle.

14. An A.C. supply converter substantially as 45 described herein with reference to the accompanying drawings or modified as herein described.

Printed for Her Majesty's Stationery Office by The Tweeddale Press Ltd., Berwick-upon-Tweed, 1983.

Published atthe Patent Office, 25 Southampton Buildings, London, WC2A1 AY, from which copies may be obtained.