GB2096431A - Telephone line supervision arrangement - Google Patents

Abstract

A telephone line supervision system which detects the OFF-HOOK handset condition by monitoring the current drawn from the telephone installation power supply and signalling the OFF-HOOK condition when a sustained increase in the current taken from the power supply is detected within a set period. The monitoring operation is performed by generating short-term and long-term quantities corresponding to the short-term and long-term load currents, respectively, and detecting a sustained minimum increase in the short-term quantity above the long-term quantity. The long-term quantity is held as a binary quantity and converted to an analogue value for the comparison.

Description

SPECIFICATION Telephone line supervision system This invention relates to a telephone line supervision system.

It is necessary to detect the lifting of the telephone handset of a telephone installation.

Conventional supervision systems apply a -50 volt bias to the subscribers line and monitor the line current. When the handset is down the phone bell is seen across the line. The bell is a series L CR circuit and hence no d.c. current can flow. When the handset is lifted the 300 Q microphone resistance is seen across the line and a direct current flows dependent on line resistance. This direct current is detected by a relay.

During ringing of the handset the same direct current monitoring is performed, an 85 volt rms, 25 Hz sinusoid being applied to the A wire and the -50v bias to the B wire.

This system has disadvantages, including the fol lowing:- 1. A bulky relay is required to detect the off-hook condition, 2. the speed of the off-hook detection is low, 3. a bulky ring relay is needed to apply the ring signal to the line, and 4. it requires a ring generating machine.

It is an object of the present invention to overcome at least some of these disadvantages.

Atelephone line supervision system in accordance with the invention may be implemented as an integrated circuit.

According to the invention, in a telephone line supervisory system, a method of detecting an OFF HOOK condition of a telephone handset, includes the operations of monitoring the load current drawn from a power supply providing electrical energy to the telephone installation and detecting a sustained increase in the load current within a set period as an OFF-HOOK condition.

The operation of monitoring the load current may include the step of generating a reference signal which tracks slow variations in the peak load current.

The operation of monitoring the load current may include the step of storing the reference signal as a binary quantity.

The operation of monitoring the load current may include the step of detecting a minimum short-term increase above the binary quantity.

The operation of monitoring the load current may include the step of detecting, for a period following the detection of the first short-term increase above the minimum, when the short-term increase exceeds the minimum increase for a set minimum proportion of the said period.

The method of monitoring the load current may include the step of counting the number of occasions on which the short-term increase exceeds the minimum and detecting when the count reaches a minimum set number.

The operation of monitoring the load current may include the step of altering the line energisation from an alternating drive to a direct drive at or near the peak of the alternating drive.

Apparatus for performing a method of detecting an OFF-HOOK condition of a telephone handset includes means arranged to receive a signal dependent on the load current drawn from a power supply providing electrical energy to the telephone installation, means arranged to generate short-term and long-term quantities dependent on the load current signal, means arranged to compare the short-term and long-term quantities, means arranged to detect a sustained increase in the short-term quantity above the long-term quantity within a period, and means arranged to signal the presence of the said sustained increase as an OFF-HOOK condition.

The means arranged to generate short-term and long-term quantities dependent on the load current signal may be arranged to track slow variations in the peaks of the load current signal.

The means arranged to generate the said shortterm and long-term quantities may include a binary store for holding the long-term quantity as a binary quantity.

The means arranged to detect a sustained increase in the said short-term quantity may include means arranged to count the number of occasions on which the short-term quantity exceeds the long-term quantity by a set minimum and means arranged to signal that a set minimum count has been reached.

To permit the use of an integrated circuit RING generator the voltage the integrated circuit must withstand is minimised by the use of a supervision technique that does not require a bias voltage during ringing.

The ring sinusoid is applied to the line by a bridge amplifier to minimise the voltage requirements. The ring signal is balanced about the supply rails to minimise cross talk effects.

When the RING generator is inoperative, the exchange battery may be routed through to the line or supplied with a constant current feed. In these cases the line current is monitored and OFF-HOOK signalled when a preset threshold is crossed. Dial pulses are signalled by this method too.

During ringing the situation is more complex. The supervision is effected most readily when the power supply is a resonant circuit converter power supply unit by the use of the power supply waveforms as timing signals in addition to the RING generator sinusoid.

The resonant circuit converter can operate at approximately 100kHz. The conduction angletd of the converter is directly proportional to the current supplied to the interface circuit and the subscribers line.

During the first period of the ring sinusoid (40ms) an adaptive threshold level is setatthe peak of the RING current waveform. This threshold is continuously updated during ringing by small changes, up or down, of the current peaks.

Should the current peak increase in any ring period by more than a preset amount the threshold is clamped and the conduction angle is monitored by a statistical decision circuit for up to one half of a ring period (20ms). Should the clamped threshold be crossed for greater than a preset percentage of the decision interval (2ms) then an OFF-HOOK condition is signalled, the RING signal removed and the interface circuit set up for speech conditions. The worst case detection time between lifting the handset and signalling OFF-HOOK is one and one half of a RING period. If the decision criterion is not satisfied then the increase in conduction angle is deemed to be due to causes other than the handset being lifted and the threshold is unclamped and monitoring continues.

The same off-hook detection scheme is always used, and when a change is made from the alternating (RING) line drive to a direct (NO RING) line drive the back emf produced by the inductance of the handset bell is minimised by holding the RING oscillator voltage at the point where the rate of change of current is zero. The voltage applied to the line is then driven exponentially to the peak RING voltage. The adaptive threshold circuitry is prevented from falling during the direct (NO RING) line drive period. Since peak ringing volts are applied to the line during the direct (NO RING) line drive period, should the subscriber handset be lifted, then the conduction angle increases to a value detectable as the OFF-HOOK condition.

Any common mode currents induced in the line appear in a resonant circuit converter and modulate the conduction angle. This modulation is removed by arranging for the lines to be balanced about the supply voltage. When balance is achieved, the balanc ing signal can be added to the threshold voltage in the correct proportion so that the threshold tracks the common mode induced component of the conduction angle.

A method and apparatus for supervising a telephone installation, in accordance with the present invention, will now be described by way of example only and with reference to the accompanying drawings in which: Fig. 1 shows diagrammatic representations of voltages and currents used to control a telephone line supervision system according to the invention and voltages and currents existing in the system, Fig. 2 shows circuit diagram representation of a part of a telephone line supervision system according to the invention, and, Fig. 3 shows a circuit diagram representation of the remainder of the telephone line supervision system of Fig. 2.

Reference is made to Fig. 1 which shows signals VC V, VCI, and RT used as clock signals in a telephone supervisory system according to the invention. The signalsVCl and VCV are in phase quadrature relationship with a period of the order of 40 ,aS, that is, a frequency of 25 KHz. The signal RT is of the same frequency as VCI and VCV, is in phase with VCI but has a shorter duration positive excursion than that of VCI. The signals VCI and VCV may be of higher frequency, of 100 KHz, for example.

A pulse signal T is also used in the telephone supervisory system. The signal T has the same frequency and phase as the signal VCI but the respective pulse widths vary according to the energy being drawn from the telephone power supply at each rising edge of the signal VCI.

The signal VCV may be generated by means of an astable multivibrator and the waveform VCI obtained by applying the signal VCV to a Type CD 4046 phase locked loop. The signal RT may then be generated in known manner from the signal VCI, by means of a monostable multivibratorsay. The signal Twould be obtained by sampling the current drawn from the power supply at the appropriate times and converting the samples, in known manner, to a width-modulated pulse train.

The signals VCV, VCI and Tare readily obtainable when the telephone employs a power supply which has a resonant circuit which is maintained in an oscillatory state by periodically replacing its energy loss. The signal VCI is a clipped and square up form of the resonant circuit current waveform and the signal VCV is a clipped and squared up form of the voltage waveform existing across one of the resonant components. The signal T is a voltage signal which controls a transistor switch arranged to replace the energy losses of the resonant circuit. The energy loss is, of course, very nearly equal to the energy supplied to the load.

Fig. 1 shows also several cycles of a sinusoidal RING signal v, a RING ENABLE signal RE which controls a RING generator to produce the RING signal v, a CADENCE signal CA which controls the supervision operation, a STOP RING signal SR which, when at the logical o level for the system, stops the RING generator independently of the signal RE, a LINE CURRENT signal IL obtained by monitoring the line current, a LINE ENERGY signal EL obtained by monitoring the line energy, and an ENERGY TRANS FER MINIMA signal ETM obtained by generating voltage step at each line energy zero crossing.

The period of the RING signal is about 40 mS, that is, the RING signal v has a frequency of 25 Hz. The signals RE, CA, SR, IL, EL and ETM are all represented on the same time scale.

The various signals shown in Fig. 1 are employed as follows in telephone handset supervision: The pulse signal T is converted to a voltage level V2 for comparison with a threshold voltage V1 which represents the long-term average value of V2 itself.

On the comparison of V1 and V2, a HIGH or LOW result (logical 1 orO) is obtained, and the result is stored in a single-bit memory cell in the presence of the signal RT. The single-bit memory cell is loaded (with a logical 1 orO, as appropriate,) during each power supply cycle and is cleared at the end of each power supply cycle.

During ringing the long-term average value V2 is held as a binary value in a binary counter/store by the use of the signals RE, CA, SR, IL, EL, and ETM.

Ringing is initiated by the signal RE going to its HIGH level. The binary counter/store is cleared at the time RE goes HIGH but not activated until the signal CA goes to its HIGH level. The delay from RE going HIGH to CA going HIGH is about 41 of a RING cycle and is considered long enough for the disappearance of transient conditions caused by the change in RE. A STOP RINGING signal SR goes to its HIGH value at the same time as CA. Ringing is prevented when SR is at its LOW value.

During the part of the first RING cycle which remains after CA has gone HIGH, the digital counter/store will be incremented until the count reaches a valve corresponding to the peak energy drawn from the power supply, as represented by the waveform EL in Fig. 1. The signal ETM assists in holding the stored count at the long-term peak energy value by decrementing the stored count periodically, in practice, at each positive ETM transition, or, at or near an energy-transfer minimum. The count is incremented whenever it falls below the current peak-energy level. An added count of three in any half-ring cycle is treated as a possible OFF HOOK condition and leads to the execution of additional checks.

Reference is now made to Fig. 2 which is a diagrammatic representation of a part of a telephone supervision system using the waveforms of Fig. 1 to detect an OFF HOOK condition.

As shown in Fig. 2, the variable width pulse signal T, which is a measure of the power taken from a power supply in each ring cycle, is applied to a voltage-to-current converter circuit lying within a dotted enclosure 1. The voltage-to-current converter 1 provides a current proportional to the width of the input pulse signal T by means of a current mirror arrangement. The current is used to charge a capacitor 2. The capacitor 2 is held discharged during the periods when the signal VCI is at its LOW value by means of a transistor switch 3 connected across the capacitor 2 and controlled by the signal VCI. The transistor switch 3 is switched off while the input pulse signal T is present and the capacitor 2 is charged during the period that the transistor switch 3 is off.

The voltage at the capacitor 2 is applied to the non-inverting input port of a comparator 4, and a voltage V1 is applied to the inverting input port of the comparator 4. The voltage V1 is the output voltage from a digital-to-analogue converter 5. A digital counter/store 6 provides the digital input to the digital-to-analogue converter 5.

The output signal from the comparator 4 is applied to a D-type flip-flop 7 which is clocked by the signal RT and reset by the signal VCI inverted. The output port of the D-type flip-flop 7 is applied to an input port of an AND gate 8. The AND gate 8 is controlled by one of a group of three flip-flops 12 and the output port of the AND gate 8 is connected to the CLOCK input port of the digital counter/store 6. The one of the group of three flip-flops 12 controlling the AND gate 8 has its RESET input port connected to a flipflop 13. The flip-flop 13 has its CLOCK input port connected to receive a RING TRIP ENABLE signal RTe.The signal RTE is arranged to so control the group of flip-flops 12 and the flip-flop 13 that the AND gate 8 is open for the first ring cycle, permitting the output signals from the flip-flop 7 to reach the CLOCK input port of the digital counter/store 6. The digital counter/store 6 is incremented by 1 each time the output level of the flip-flop 7 is a logical 1, the effect being that the stored count at the end of the first ring cycle corresponds to the peak energy drawn from the power supply in the first ring cycle.

The contents of the digital counter/store 6 are applied to the digital-to-analogue converter 5. The output level of the digital-to-analogue converter 5 is the input voltage V1 of the comparator 4.

At the end of the first ring cycle, RTE changes from a LOW to a HIGH level and releases the group of flip-flops 12. The gate 8 is then controlled by one of the group of flip-flops 12.

The signal RE is transmitted to the digital counter/store 6 by way of an inverter 10 and a flipflop 9. The flip-flop 9 provides an output which is applied to the PRESET ENABLE input ports of the counter/store 6 causing it to be loaded with zero count at the beginning of a RING operation.

Two flip-flops 14 and 15 are connected together and to the source of the signal ETM. The flip-flops 14 and 15 provide a pulse for each rising edge of the ETM waveform. The pulses are applied to the digital counter/store 6 in such a way that the stored count is decremented by 1 each time a pulse arrives. The decrementing of the stored count overrides incoming pulses from the flip-flop 7. The binary counter/store 6 decrements only so long as the stored count exceeds zero.

A CLOCK input port of the group of flip-flops 12 is connected to the output port of the flip-flop 7 and an output port of the group of fiip-flops 12 is connected to an ENABLE input port of a second binary counter/store 16. The group of flip-flops 12 count pulses from the flip-flop 7 and are set by the pulses from the flip-flop 15 each time it decrements the binary counter/store 6, at each half cycle of the ring sinusoid. The group offlip-flops 12 are arranged to activate the second binary counter/store 16 if and when they the group of flip-flops 12, reach a count of three.

The group of flip-flops 12 shut the AND gate 8 when they reach a count of three and open an AND gate in the second binary counter/store 16 through which the signal VCI can pass to drive the CLOCK input port of the second digital counter/store 16. The second binary counter/store 16 can count either up or down as controlled by the flip-flop 7 which provides a logical 1 output, permitting an UP count, when the output of the comparator 4 is at the HIGH level.

The group of flip-flops 12 also release a flip-flop pair 17, 18 which have their CLOCK input ports connected to the source of the signal ETM. The flip-flop pair 17, 18, initially, provide a logical 0 signal to the RESET input port of the group of flip-flops 12, but the signal to the RESET input port of the group of flipflops 12 changes to a logical 1 aftertwo positivegoing edges of the ETM signal have been received by the flip-flop pair 17, 18. The logical 1 signal at the RESET input port of the group of flip-flops 12 disconnects the second binary counter/store 16.

During the time the second binary counter/store 16 is connected, it counts the number of occasions on which the output signal from the flip-flop 7 is at its HIGH value and provides a binary count output. The two most significant digit outputs from the second binary counter/store 16 are connected to an AND gate 19. The output port othe AND gate 19 is connected to the CLOCK input port of a D-type flip-flop 20. The D-type flip-flop 20 is driven to its HIGH output state when the two most significant digit outputs of the second digital counter/store 16 are logical 1.

The second binary counter/store 16 reaches the state necessary to drive the flip-flop 20 to its output state when the output of the flip-flop 7 remains at its HIGH state for at least 75% of some 256 power supply cycles which occur between adjacent positive-going edges of the ETM signal. The second binary counter/store 16 is cleared when it is disconnected subsequently.

If the flip-flop 20 has been driven to its HIGH output state a POSSIBLE OFF HOOK condition is maintained. This leads to a check which distinguishes conditions consistent with an additional phone being connected to the line from conditions consistent with a handset being taken off the hook.

The check for distinguishing between an additional phone being connected and a handset being lifted begins with the signal CA being taken to its LOW level. The change in CAto its LOW level releases a flip-flop 21, previously held SET by CA.

The CLOCK input port of the flip-flop 21 is connected to a peak detector circuit 22 which is driven by a signal VIL proportional to the line current. The peak detector circuit 22 provides a signal suitablefortrig- gering the flipflop 21 when the rate of change of line current is zero. The flip-flop 21 receives a trigger signal on the first occasion after CA goes to its LOW value that the rate of change of line current is zero.

The output signal from the flip-flop 21 appears as an output signal SR.

The detection of the said zero rate of change of current in the RING sinusoid is followed by the cessation of the RING drive at the zero rate of current change point. The cessation of the RING drive at zero rate of current change effects the minimum-transient condition. An exponentially rising d.c. bias is then applied in place of the RING sinusoid. The circuits which effect the change from the RING sinusoid to the final d.c. bias are not shown.

Reference is now madeto Fig. 3. The signal SR generated bythe flip-flop 21 (Fig. 2) is used to trigger a monostable multivibrator 23. The output port of the monostable multivibrator 23 is connected to the CLOCK input port of a D-type flip-flop 24. The DATA input port of the flip-flop 24 is held at the logical 0 level for the system, so the D-type flip-flop 24 provides a logical 0 output signal when the monostable multivibrator23 returns to a logical 1 output. The logical 1 output signal from the D-type flip-flop 24 holds four binary counters 25,26,27 and 28 in the "cleared and inoperative" state.

The integrated value V2 of the load current pulse T (Fig. 1) is now compared with a reference voltage VT (Fig. 1) by means of a comparator 29. The values VT corresponds to the small line currentthat would flow should the handset be ON HOOK.

A flip-flop 30, its CLOCK input port connected to the source of the signal VCV (Fig. 1), has its output port connected to the UP/DOWN control input ports of the binary counters/stores 25, 26, with the result that the binary counters/stores 25,26, count UP when the flip-flop 30 provides a logical 1 output and counts DOWN when the flip-flop 30 has a logical 0 output. The flip-flop 30 has a D-input port driven by the comparator 29.

The CLOCK input ports of the binary counter/stores 25,26, 27 and 28 are connected to the source of the signal VCI (Fig. 1). The two mostsignif- icant digit outputs of the binary counters/stores 25 and 26 are connected to input ports of an AND gate 31 and the AND gate 31 has its output port connected to the D-input port of a flip-flop 32. The four most significant digit outputs of the binary counters/stores 27 and 28 are connected to input ports of an AND gate 33 and the AND gate 33 has its output port connected to the CLOCK input port of the flipflop 32. The flip-flop 32 is clocked by the AND gate 33 when the outputs of the binary counter/stores 28 are all logical 1, and, when the flip-flop 32 is clocked, it is a logical 1 is the two most significant digits of the counter 26 are logical 1.The output port of the flipflop 32 is connected to an input port of an AND gate 34.

The AND gate 34 has a second input port connected to the source of a signal CA CONTROL. The AND gate 34 therefore provides a logical 1 output when both the signal CA CONTROL and the output of the flip-flop 32 are logical 1. This is signalled as the OFF HOOK condition.

The complemented output of the flip-flop 32 is connected to an input port of an AND gate 35 which has another input port connected to the source of the signal CA CONTROL, and the output port of the AND gate 35 is connected to an input port of an AND gate 36 which has another input port connected to the output port of the AND gate 33. The AND gate 36 is held open when the output of the AND gate 33 is logical 1, and should the output of the AND gate 31 be a logical 0, a logical 1 will be provided by the AND gate 36 to the SET input ports of the flip-flop 24, clearing the system. The output of the flip-flop 32 will then be a logical 0 also, and the AND gate 34 will provide a logical 0 or NEGATIVE OFF HOOK CONDI TION.

The output signal B from the AND gate 36 is returned to the RESET input port of the flip-flop 20 (Fig. 2) which is RESET in the NEGATIVE OFF HOOK condition.

The signal CA CONTROL is connected also to an input port of an AND gate 37 by way of an inverter 38 so that the gate 37 is held open when the signal CA CONTROL is at the logical 0 level. The output port of the AND gate 31 is connected to an input port of the AND gate 37. The AND gate 37 therefore provides a logical 1 output at any time that the two most significant digit outputs of the binary counter/store 26 are logical 1 and the CA CONTROL signal is at the logical 0 level. The CA CONTROL signal is at the logical 0 level at times when the signal RE is at a LOW level.

An AND gate 38 and an inverter 39 generate the signal CA from the signal CA CONTROL and the output signal A from the flip-flop 20. The source of the signal CA CONTROL is connected to an input port of the AND gate 38 and the output port of the flip-flop 20 is connected to the input port of the inverter 39, the output port of the inverter 39 being connected to the other input port of the AND gate 38. The result of the arrangement of the AND gate 38 and the inverter 39 is that CA is at the low level so long as CA CON TROL is, CA is at the HIGH level while CA CONTROL is at the HIGH level and the signal A is at the LOW level, and CA is at the LOW level while CA CONTROL is at the LOW level and the signal A is at the HIGH level.

When the signal RE is at a LOW level i.e. phone not ringing, fixed reference voltage VT (Fig. 1) is provided at the inverting input port of the comparator 4 (Fig. 2) as the means of detecting an OFF HOOK condition.

Claims (13)

1. In a telephone line supervisory system, a method of dtecting an OFF-HOOK condition of a telephone handset, including the operations of monitoring the load current drawn from a power supply providing electrical energy to the telephone installation and detecting a sustained increase in the load current within a set period as an OFF-HOOK condition.

2. A method of detecting an OFF-HOOK condition of a telephone handset as claimed in claim 1, wherein the operation of monitoring the load current includes the step of generating a reference signal which tracks slow variations in the peak load current.

3. A method of detecting an OFF-HOOK condition of a telephone handset as claimed in claim 2, wherein the operation of monitoring the load current includes the step of storing the reference signal as a binary quantity.

4. A method of detecting an OFF-HOOK condition of a telephone handset as claimed in claim 3, wherein the operation of monitoring the load current includes the step of detecting a minimum short-term increase above the binary quantity.

5. A method of detecting an OFF-HOOK condition of a telephone handset as claimed in claim 4, wherein the operation of monitoring the load current includes the step of detecting, for a period following the detection of the first short-term increase above the minimu, when the short-term increase exceeds the minimum increase for a set minimum proportion of the said period.

6. A method of detecting an OFF-HOOK condition of a telephone handset as claimed in claim 5, wherein the method of monitoring the load current includes the step of counting the number of occasions on which the short-term increase exceeds the minimum and detecting when the count reaches a minimum set number.

7. A method of detecting an OFF-HOOK condition of a telephone handset as claimed in any one of claims 1 to 6, wherein the operation of monitoring the load current includes the step of altering the line energisation from an alternating drive to a direct drive at or near the peak of the alternating drive.

8. Amethod of detecting an OFF-HOOK condition of a telephone handset substantially as herein described with reference to the accompanying drawings.

9. Apparatus for performing a method of detecting an OFF-HOOK condition of a telephone handset, as claimed in any one of the preceding claims, including means arranged to receive a signal dependent on the load current drawn from a power supply providing electrical energy to the telephone installation, means arranged to generate short-term and long-term quantities dependent on the load current signal, means arranged to compare the short-term and long-term quantities, means arranged to detect a sustained increase in the short-term quantity above the long-term quantity within a set period, and means arranged to signal the presence of the said sustained increase as an OFF-HOOK condition.

10. Apparatus for performing a method of detecting an OFF-HOOK condition of a telephone handset, as claimed in claim 9, wherein the means arranged to generate short-term and long-term quantities dependent on the load current signal is arranged to track slow variations in the peaks of the load current signal.

11. Apparatus for performing a method of detecting an OFF-HOOK condition of a telephone handset, as claimed in claim 10, wherein the means arranged to generate the said short-term and long-term quantities includes a binary store for holding the longterm quantity as a binary quantity.

12. Apparatus for performing a method of detecting an OFF-HOOK condition of a telephone handset, as claimed in claim 11, wherein the means arranged to detect a sustained increase in the said short-term quantity includes means arranged to count the number of occasions on which the short-term quantity exceeds the long-term quantity by a set minimum and means arranged to signal that a set minimum count has been reached.

13. Apparatus for performing a method of detecting an OFF-HOOK condition of a telephone handset substantially as herein described with reference to and as illustrated by the accompanying drawings.