GB2089599A - Data Clock Pulse Generator - Google Patents

Abstract

As shown in Figure 3, a data clock pulse generator comprises a data clock pulse source 20 for generating local clock pulses CK, a phase sensitive detector 21 for producing a control signal CS whose value depends on the difference in phase between the clock pulses CK and received data pulses DP, a voltage-to-current converter circuit 31 which converts the control signal into a control current, and a capacitor 22 which is charged by the control current to produce a control voltage which controls a phase shifter 29 of the source 20. The converter 31 is controlled by a timing circuit 32 to operate at a high rate during the first part of a data pulse burst when only clock run-in pulses CL (Figure 2c) are being received, and at a second low rate for the remainder of the data pulse burst. The initial high control rate allows rapid correction of a large phase drift between the pulses DP and CK which can occur between successive data pulse bursts. <IMAGE>

Description

SPECIFICATION Data Pulse Receiver Arrangement This invention relates to a data pulse receiver arrangement of a type suitable for the acquisition of data pulses which occur in a serial bit stream in a received bi-amplitude signal in which one level of the signal (say high) represents a binary value '1' and another level of the signal (say low) represents a binary value '0', said arrangement including a data clock pulse generator for clocking the data pulses into the data pulse receiver arrangement.

A data pulse receiver arrangement of the above type (which is known for instance from Mullard Technical Information Article 34, dated September 1976, and Mullard Technical Information Article 54, dated August 1977) has application in data transmission systems in which data transmission and reception is not synchronised. Such a data transmission system is, for example a television transmission system of a character in which coded data pulses representing alphanumeric text or other message information are transmitted in a video signal in at least one television line in field-blanking intervals where no picture signals representing normal picture information are present. United Kingdom Patent Specification No. 1,370,535 discloses a television transmission system of this character.

A requirement with such an application of the data pulse receiver arrangement is to synchronise clock pulses locally generated therein with the received coded data pulses. One technique for achieving this synchronisation is to generate a local data pulse clock from the received data pulses. A data clock pulse generator which is suitable for this purpose is a ringing circuit which comprises a tuned circuit arranged for oscillation at predetermined clock pulse frequency, together with means to produce current pulses in response to the received data pulses for exciting the tuned circuit to maintain its oscillation in synchronism with the received data pulse. Another technique for achieving said synchronisation is to generate a local data pulse clock independently of the received data pulses and then shift its phase into synchronism with them.A data clock pulse generator which is suitable for this latter purpose may comprise an oscillator arranged for oscillation at a predetermined clock pulse frequency to produce locally generated clock pulses, together with a phase sensitive detector which is operable to produce a control signal in accordance with the relative phases of the received data pulses and the clock pulses, which control signal is then used to correct the phase of the oscillator output to bring the data pulses and clock pulses into synchronism. The control exercised by the control signal may act directly on the oscillator (e.g. in the case of a voltagecontrolled oscillator), so that the phase of the oscillator output, as actually produced, is corrected.Alternatively, the control exercised by the control signal may cause a phase shifter arrangement to alter the phase of the oscillator output after it has been produced. This latter form of control permits a highly stable oscillator, such as a crystal-controlled oscillator, to be used to generate the clock pulses.

Where a serial bit stream of data pulses is deemed to be "continuous" by virtue of the face that a succession of its data pulses occur for a significant duration without interruption, the phase sensitive detector and oscillator can readily establish the required phase of the locally generated clock pulses with respect to the incoming data pulses and, since the latter are "continuous", any tendency for this phase relationship to alter can be corrected continually.

Thus, once the required phase relationship has been established it is unlikely that there will be any appreciable drift from this required phase relationship.

However, where data pulses of a serial bit stream occur in short bursts with a relatively long interruption between successive bursts, difficultly has been encountered in achieving the required phase relationship sufficiently quickly in each successive data pulse burst because the relatively long interruption allows drift from the required phase relationship to occur without any opportunity for correction. In particular, such a difficulty arises in a data pulse receiver arrangement for a television transmission system of the character referred to in which an entire field of picture information may be transmitted between successive bursts of coded data pulses.

It is an object of the present invention to seek to provide a solution to this difficulty in respect of data pulse transmission formats in which the data pulses of each burst comprise a sequence of clock run-in pulses followed by a sequence of code pulses.

According to the invention there is provided a data clock pulse generator for clocking data pulses into a data pulse receiver arrangement, the data pulses occurring in a serial bit stream in a received bi-amplitude signal and being arranged in successive bursts of which each comprises a sequence of clock run-in pulses followed by a sequence of code pulses, which data clock pulse generator compiises an oscillator arranged for oscillation at a predetermined clock pulse frequency to produce locally generated clock pulses, together with a phase sensitive detector which is operable to produce a control signal in accordance with the relative phases of the received data pulses and the clock pulses, the control signal being used to correct the phase of the oscillator output to bring the data pulses and clock pulses into phase synchronism, and which data clock pulse generator is characterised by including level-adjusting means which are operable such that during the sequence of clock run-in pulses of a data pulse burst the response of the phase sensitive detector in the production of said control signal is at one rate, whereas during the following sequence of code pulses of the data pulse burst, said response is at another, lower, rate.

The effect of causing the level-adjusting means to vary the rate of response of the phase sensitive detector in the production of said control signal, so that initially the rate can be relatively high, is to enable the data clock pulse generator to bring the data pulses and clock pulses into approximate phase synchronism during the period that the clock run-in pulses occur, which period would normally be relatively short compared with the ensuing period during which the following sequence of code pulses occurs. The rate would need to be lower for the code pulses in order to provide a more stable control signal.

In carrying out the invention there may be provided re-setting means which are operable before the beginning of each data pulse burst to set said control signal to a value corresponding to the centre of its control range. This re-setting will facilitate the adjustment of the clock pulses into approximate phase synchronism with the data pulses during the period that the sequence of clock run-in pulses Qccurs.

Where the invention is employed in a television transmission system of the character referred to, the re-setting means may be operable by the flyback pulse that occurs at the beginning of each television line that contains data pulses.

The control signal can be constituted by the voltage developed across a capacitor the charge on which is determined by a current source circuit which is controlled by the phase sensitive detector to drive current into and extract current from the capacitor. In this arrangement, the current source circuit can comprise two current sources connected in parallel, together with an electronic switch which is connected in series with one of these two current sources between it and the capacitor and is closed to connect that current source to the capacitor only during the period that the sequence of clock run-in pulses occurs.

The invention also extends to a data clock pulse generator as set forth above, embodied in a data pulse receiver arrangement of the type referred to for use in a television receiver apparatus for a television transmission system of the character referred to. Such television receiver apparatus can be adapted to display alphanumeric text or other message information concurrently with, or as a selectable alternative, to, normal picture information.

In order that the invention may be more fully understood reference will now be made by way of example to the accompanying drawings, of which: Figure 1 is a block diagram of a television transmission system of the character referred to; Figures 2(a), 2(b) and 2(c) show explanatory diagrams relating to the data pulse coding and tgansmission of alpha-numeric text or other message information by the system of Figure 1; Figure 3 is a block diagram of a data clock pulse generator; and Figure 4 shows a circuit element for the data clock pulse generator of Figure 3.

Referring to Figure 1 of the drawings, which shows diagrammatically a television transmission system of the character referred to having television receiver apparatus which embodies the invention and which is for displaying selectively either a television picture which is produced from picture information in a normal broadcast or cable television video signal, or alpha-numeric text or other message information which is produced from coded data pulses which are transmitted in the video signal in vertical or field-blanking intervals thereof. The possibility can also exist for displaying such message information concurrently with a television picture, for instance as sub-titles or captions which are superimposed on the television picture.

Examples of a television transmission system of the character referred to are the CEEFAX and ORACLE systems used by the BBC and IBA, respectively, for transmitting Teletext data within the broadcast standards of the 625-line domestic television system as employed in the United Kingdom.

An incoming television video signal VS appears at an input lead 1 of the television receiver apparatus via its front end 2 which comprises the usual amplifying, tuning, i.f. and detector circuits.

The front end 2 is assumed to be adapted to receive the video signal VS from a television transmitter 3 via a conventional over-air broadcast or cable transmission link 4. The transmitter 3 includes in known manner means for producing television picture information, means for producing alpha-numeric text or other message information, and further means for generating the appropriate composite television video signal containing picture signal representative of the picture information, and coded data pulses representative of the message information, together with the usual synchronising, equalizing and blanking signals which are necessary for the operation of the television receiver apparatus.

For normal picture display in the television receiver apparatus, the received video signal is applied to a selector circuit 5 which includes a selector switch 5. When the switch 6 is closed, the video signal VS is applied to a colour decoder 7 which produces the R, G and B component signals for the picture display, these component signals being applied via a video interface circuit 8 to the red, green and blue guns of a colour television picture tube 9. Scanning circuits 10 for the tube 9 receive the usual line and field synchronising pulses LS and FS from a synchronising separator circuit 11 which extracts these synchronising pulses from the incoming video signal VS.

Coded data pulses representing message information in the video signal VS do not affect the picture display because they occur in one or more lines inthe field-blanking interval when there is no picture display. Of the lines occurring in the field-blanking interval, most could be used to transmit coded data pulses representing message information. However, in the BBC/IBA Teletext System at present only lines 1 7/1 8 of even fields and line 330/331 of odd fields of the 625-line broadcast television system are used in the United Kingdom. (See "Broadcast Teletext Specification", September 1976, published jointly by the British Broadcasting Corporation, Independent Broadcasting Authority and British Radio Equipment Manufacturers' Association).

The video signal VS on the input lead 1 is also applied to a data acquisition circuit 1 2 which includes a data clock pulse generator (to be described) for clocking the coded data pulses representing the message information into the data pulse receiver arrangement of the television receiver apparatus. This data pulse receiver arrangement comprises those elements within the dotted line rectangle 19.

It is assumed that the message information represented by the coded data pulses contained in the video signal VS is divided into different pages of information, and that each page is for display as a whole on the screen of the picture tube 9, with the coded data pulses representing each page of information being repeated periodically in a recurrent cycle with or without updating of the information. It is further assumed that each page of message information is identified by means of a unique page address code which is included in the coded data pulses and defines the page number.The television receiver apparatus includes a code selector circuit 1 3 which controls the particular coded data pulses that are acquired by the data acquisition circuit 12 at any time. (This control is indicated by a broad-arrow connection n representing the presence of a group of n parallel channels which form an n-bit channel link for carrying n bits of information required for data selection-other groups of parallel channels forming multi-bit channel links in the television receiver apparatus are represented similarly as m, p, q and r numbers of channels and bits).

The acquired coded data pulses are clocked serially into the data acquisition circuit 12 by the clock pulses produced in the latter. From the data acquisition circuit 12, the acquired coded data pulses are fed in parallel groups of m bits to a data store 14. It is assumed than an m-bit character byte is required for each character (or other item of information) contained in the message information. If, for example, m=8, a character byte would comprise a character code consisting of 7 bits plus a single parity bit. The data store 14 can store a complete page of message information. In a typical television transmission each page of message information would contain up to 24 rows of characters, with each row containing up to 40 characters.Thus in order to identify the different characters of a page, it is furthermore assumed that the coded data pulses also include an address code for each character, this address code employing r bits and being fed to the data store 14 over an r-bit channel link to control the storage therein of the character codes.

In view of the restricted transmission time which is available for transmitting the coded data pulses representing message information, for instance, sufficient time to transmit the coded data pulses for only one character row during a television line in the field-blanking interval, character data for a page of message information has to be stored row-by-row in the data store 14 over a relatively large number of television fields.

This storing of character data row-by-row in the data store 14 is under the control of the address codes received from the data acquisition circuit 12 over the r-bit channel link.

A character generator 1 5 of the television receiver apparatus is responsive to the character data stored in the data store 14 to produce character generating data which can be used to derive what is effectively a new picture signal for displaying the characters represented by the stored character data. As mentioned previously, different characters are assumed to be represented by respective m-bit bytes. The bits of the character code in each byte are fed in parallel from the data store 14 to the character generator 1 5 over a p-bit channel link (p=7).A character format for characters to be displayed can be a coordinate matrix composed of discrete elements arranged in rows and columns, this format being derived from a "read-only" memory which serves as the character generator 1 5 and which provides bits of character generating data in rows and columns, one row at a time. Since the character generating data is required as a modulation of a video signal in order to produce selective bright up of the screen of the picture tube 9 to achieve character display, the character generating data is produced serially (as 1's and O's) by using a parallel-to-serial convertor 1 6 to convert each row of bits of data read out from the character generator 1 5 (e.g. q=5) into serial form.

In order to effect character display on the screen of the picture tube 9 using standard line and frame scans, the logic of the television receiver apparatus in respect of character display is so organised that for each row of characters to be displayed, all the characters of the row are built up television line-by-television line as a whole, and the rows of characters are built up in succession. It takes a number of television lines to build up one row of characters. In the first television line, character data from the date store 14 in the character generator 1 5 would cause the latter to produce character generating data in respect of the first row of discrete elements for the first character of the row, then in respect of the first row of discrete elements for the second character, and so on for the successive characters of the row.In the second television line, character generating data in respect of the second row of discrete elements for each character of the row would be produced in turn, and so on for the remaining television lines concerned.

The logic of the television receiver apparatus is organised by means of a timing pulse chain circuit 17 which provides appropriate timing pulses to the data store 14, to the character generator 15, and to the data acquisition circuit 12. The circuit 1 7 is synchronised in operation with the scanning circuits 10 of the picture tube 9 by the line and field synchronising pulses LS and FS extracted from the incoming video signal VS by the synchronising separator circuit 11.

The output from the converter 1 6 is applied to a colour coder 18 which produces R1, G1 and B1 component signals for character display, these component signals being also applied to the video interface circuits 8. The colour coder 1 8 can be controlled (in a manner not shown) by selected items of the character data in the data store 14 to provide a controlled colour character display. Of course, black-and-white picture and character display is also possible, in which event the colour decoder 7 and colour coder 18 would be omitted.

Figure 2(a) shows a waveform diagram which represents a Teletext television video signal for one television line which occurs in a fiald-blanking interval and which includes coded pulse data. In this waveform diagram the line synchronising pulse for the television line concerned is represented at LS1, and the line synchronising pulse for the next television line is represented at LS2. The colour burst on the television line concerned and that on the next television line, are represented at CB1 and CB2, respectively.

Assuming the television broadcast standards for 625-line systems are employed in the United Kingdom, the period of one television line (i.e. the period between the leading edges of successive line synchronising pulses) is 64 ys, as indicated.

Further assuming the standards adopted in the United Kingdom for information transmission by digitally coded pulses in the field-blanking interval of such a 625-line system, then the television line shown would be line number 17 or 18 in an even field and line number 330 or 331 in an odd field. Such a television line is referred to as a television data line and can contain coded data pulses representing 360 binary bits which may be considered as 45 eight-bit bytes. The position of the coded pulse data in the data line is indicated at CPD. The binary bit signalling rate is approximately 7 Mbit/s, and the binary bit signalling levels are defined between black level BL and a peak white level WL. The binary '0' level is the black level BL and the binary '1' level is the level L.

Figure 2(b) shows a possible format for coded pulse data in a television data line. As mentioned above, the binary bits representing the coded pulse data are divided up into eight-bit bytes 1, 2,.. .20 . ...The first two bytes 1 and 2 comprise a sequence of clock run-in pulses which in the present example consist of a sequence of alternating bits 10101010/10101010. The third byte 3 comprises a framing or start code, e.g.

11100100, which the television receiver apparatus has to identify before it will respond to accept message information which is contained in the remaining eight-bit bytes 4, 5 ... 20 ....

This identification of the framing code is effected in known manner in the television receiver apparatus of Figure 1 by the data acquisition circuit 12.

Figure 2(c) shows in idealised form the first part of a video signal waveform VS for a television data line showing the sequence of clock run-in pulses CL and the sequence of pulses which comprise the framing code FR. The first few coded data pulses which represent alpha-numeric character or other message information are shown at DP. The line synchronising pulse is represented at LS and the colour burst at CB.

The data clock pulse generator shown in Figure 3 has a specific application in the data pulse receiver arrangement for the aforesaid BBC/IBA Teletext television transmission system. This data clock pulse generator includes a data clock pulse source 20, a phase sensitive detector 21 and a storage capacitor 22. A data slicer 23 receives data pulses DP from an input terminal 24. After level correction and possibly re-shaping (by suitable known means not shown), the data pulses DP are applied to an output lead 25 for utilisation in further circuitry, the pulses DP being clocked into this further circuitry by means of clock pulses CK which are applied to a clock pulse lead 26 by the source 20.The data pulses DP and the clock pulses CK are also applied to the phase sensitive detector 21 which is responsive thereto to produce a control signal CS on a control lead 27, this control signal CS having a value in accordance with the relative phase of the data pulses DP and the clock pulses CK.

The source 20 comprises a crystal-controlled oscillator 28 and a phase shifter 29. The oscillator 28 produces a highly stable alternating signal at the clock frequency and the phase shifter 29 is responsive in accordance with the value of a control voltage across the capacitor 22 to bring the oscillator output into phase synchronism with the data pulses DP. The control voltage consitutes the final form of the control signal CS, as will be described. A limiter 30 is provided for limiting (and squaring) the output from the source 20.

The data clock pulse generator additionally comprises a voltage-to-current converter 31, a timing circuit 32 and a re-setting circuit 33, which are all involved in the establishment of the appropriate control voltage across the capacitor 22.

The re-setting circuit 33 is so organised in relation to the coded data pulse transmission format described above with reference to Figures 1 and 2, that in each television data line it is operated by the line flyback pulse FL to connect a reference voltage RV across the capacitor 22 during the line blanking interval. This reference voltage RV sets the voltage across the capacitor 22 to a value corresponding to the centre or other selected position of its control range; that is, of the phase range afforded by the phase shifter 29.

The re-setting circuit 33 can simply comprise, as indicated, a field-effect transistor which is arranged as an electronic switch to connect the reference voltage RV across the capacitor 22 during the application of the flyback pulse FL to its gate electrode.

During the period in each television data line that the sequence of clock run-in pulses CL of the video signal VS occurs, the timing circuit 32 supplies to the voltage-to-current converter 31 a timing pulse T which causes the converter 31 to substantially increase (e.g. double) its current output from a normal rate at which it functions in response to the control signal CS (which it receives as a voltage), so that within this relatively short clock run-in period the control voltage across the capacitor 22 as produced by the current output of the converter 31 can assume in respect of the television data line a starting value corresponding to the mean phase of the sequence of clock run-in pulses CL.For the remainder of the television data line, the converter 31 operates to produce its current output at the normal lower, rate to provide a more stable control voltage for the code pulses which follow the clock run-in pulses. The initial higher rate of control voltage variation during the clock run-in period enables a reliable starting value for the control voltage to be obtained for satisfactory phase correction in respect of the code pulses. Without this initial action in accordance with the present invention, there can be insufficient time to correct adequately for phase drift between the data pulses and the clock pulses from one television data line to the next.

For producing the timing pulse T the timing circuit 32 comprises a line synchronising pulse separator 34 and a pulse generator 35. The synchronising pulse separator 34 detects the line sync. pulses LS in the video signal VS to trigger the pulse generator 35 which is responsive to produce the timing pulse T. The pulse generator 35 includes a trigger delay such that the timing pulse T occurs at the beginning of the sequence of clock pulses CL and lasts for substantially the duration thereof.

As regards the implementation of the phase sensitive detector 21 and the phase shifter 29, each of these can take any suitable known form but, preferably, the phase sensitive detector 21 is implemented as set forth in co-pending patent application No. 8039873, and the phase shifter 29 is implemented as set forth in co-pending patent application No. 8039875.

The voltage-to-current converter 31 in Figure 3 preferably takes the form shown in Figure 4, wherein it comprises two current sources 36 and 37 and an electronic switch 38. The current source 36 comprises two transistor pairs 39/40 and 41/42 of opposite conductivity type, both pairs being connected as current mirrors. The transistors 40 and 42 are connected in push-pull with their collectors connected together and to the capacitor 22, which is the capacitor 22 of Figure 3. The collectors of the other two transistors 39 and 41 are fed, respectively, with voltage pulses 43 and 44 of opposite polarity, which constitute the voltage output from the phase sensitive detector 21 in Figure 3. These voltage pulses are assumed to vary in width, in accordance with the difference in phase between the data pulses DP and the clock pulses CK.Two resistors 45 and 46 determine the current magnitude that flows into the transistors 39 and 41 in response to the voltage pulses 43 and 44.

The resultant push-pull current in the transistors 40 and 42 adjusts the charge on the capacitor 22.

The other current source 37 is provided to supply increased current into the capacitor circuit during the period of the clock run-in pulses CL. This current source 37 is the same as the source 36 in that it comprises two transistor pairs 47/48 and 49/50 of opposite conductivity type which, are connected as current mirrors, with the transistors 48 and 50 connected in push-pull with their collectors connected together However, the output at the collectors of the push-pull transistors 48 and 50 in this current source 37 is connected to the capacitor 22 via the electronic switch 38. This switch 38 comprises a field-effect transistor 51 which has the timing pulse T applied to its gate, so that the capacitor 22 receives current from this current source 37 only for the duration of this timing pulse T. The current due to the current source 37 is made proportionally different to that due to the first current source 36 by suitable selection of the values of resistors 52 and 53 relative to the values of the corresponding resistors 45 and 46 in the current source 36.

Claims (9)

Claims

1. A data clock pulse generator for clocking data pulses into a data pulse receiver arrangement, the data pulses occurring in a serial bit stream in a received bi-amplitude signal and being arranged in successive bursts of which each comprises a sequence of clock run-in pulses followed by a sequence of code pulses, which data clock pulse generator comprises an oscillator arranged for oscillation at a predetermined clock pulse frequency to produce locally generated clock pulses, together with a phase sensitive detector which is operable to produce a control signal in accordance with the relative phases of the received data pulses and the clock pulses, the control signal being used to correct the phase of the oscillator output to bring the data pulses and the clock pulses into phase synchronism, and which data clock pulse generator is characterised by including level-adjusting means wich are operable such that during the sequence of clock run-in pulses of a data pulse burst the response of the phase sensitive detector in the production of said control signal is at one rate, whereas during the following sequence of code pulses of that data pulse burst, said response is at at another, lower, rate.

2. A data clock pulse generator as claimed in Claim 1, incuding re-setting means which are operable before the beginning of each data pulse burst to set said control signal to a value corresponding to the centre of other selected position of its control range.

3. A data clock pulse generator as claimed in Claim 2, wherein said re-setting means are arranged for operation by the fly-back pulse that occurs at the beginning of each television line that contains data pulses, in a television transmission system of the character referred to.

4. A data clock pulse generator as claimed in any preceding Claim, wherein said control signal is constituted by the voltage developed across a capacitor the charge on which is determined by a current source circuit which is controlled by the phase sensitive detector to drive current into and extract current from the capacitor.

5. A data clock pulse generator as claimed in Claim 4, as appended to Claim 3, wherein said resetting means comprises a field-effect transistor which is arranged for operation as an electronic switch in response to said flyback pulse, the occurrence of said fly-back pulse causing the field-effect transistor to connect across said capacitor a reference voltage for setting the control signal to said value corresponding to the centre of its control range.

6. A data clock pulse generator as claimed in Claim 4 or Claim 5, wherein said current source circuit comprises two current sources connected in parallel, together with an electronic switch which is connected in series with one of these to current sources between it and the capacitor and is closed to connect that current source to the capacitor only during the period that the sequence of clock run-in pulses occurs.

7. A data clock pulse generator as claimed in any preceding Claim, in which the locally generated clock pulses are generated by a crystalcontrolled oscillator and are applied to a phase shifter which is controlled by said control signal to produce phase-corrected clock pulses.

8. A data clock pulse generator as claimed in any preceding Claim, embodied in a data pulse receiver arrangement of the type referred to.

9. A data clock pulse generator substantially as hereinbefore described with reference to Figures 3 and 4 of the accompanying drawings, embodied in a data pulse receiver arrangement substantially as hereinbefore described with reference to Figures 1 and 2 of the accompanying drawings.