SPECIFICATION
Logic circuitry for intercommunication between distant bus systems The present invention relates to logic circuitry suitable for interconnection in a duplex communication system for digital signals which is established between buses that are spaced apart by arbitrary distances. In such a system the novel logic circuity serves to prevent the buses becoming locked in one state, while still allowing bi-directional communication.
In a typical application, a bus may contain several lines which connect in parallel several devices in order to enable a bit-parallel, bidirectional communication over each of the bus lines, where any one device may act as a transmitter and may transmit binary signals via the bus to any or all of the remaining devices which then act as receivers. Such a bus system is defined in IEEE Standard Digital Interface for Programmable Instrumentation (IEEE Standard 488). It uses a "low for true" logic, wherein the affirmative ("true") logic state is represented by the nominal voltage level of 0 volts and the non-affirmative ("false") logic state is represented by a nominal voltage level of + 5 volts.The lines of the buses are driven by "open collector" driver circuits and are kept on + 5 volts in their non-affirmative logic states, while a signal representative of the affirmative logic state supplied to any bus line by any one of these transmitters will establish 0 volts on said bus line, disregarding the nominal voltage level of + 5 volts at the outputs of the remaining devices being connected to the bus.
Because of substantial cable capacities and various other design limitations such bus systems are limited to interconnecting about 15 devices for communication between them over distances of up to about 20 metres. It is thus desirable to establish a communication system for bidirectional data transmission between two or more buses located at arbitrary distances where each bus is connected to various devices.
In establishing such bidirectional data transmission between distant buses it may be required to communicate the logical state of some of the parallel lines directly between the buses, and it is an object of this invention to provide a means for achieving this.
In many applications it is undesirable to directly connect the distant buses, as e.g. the impedance properties of the devices connected may not be suitable to drive long cable or as the devices on different buses have different signal or chassis ground potentials.
In these cases the transmission channels may include modems, radio links, transformers, optoelectronic couplers or the like. In these cases, the bidirectional transmission channels must be divided into separate (full duplex) unidirectional transmission channels, say a forward transmission channel from a local bus to a remote bus, and a backward transmission channel from the remote bus to the local bus.
These transmissison channels may take different forms which are of no importance to this invention. Any transmission method capable of transmitting to its output the logical state provided at its input may be used.
Furthermore, there will typically be connected bus drivers and bus receivers between the ends of these transmission channels and the buses.
The purpose of such a duplex communication system with distant buses is to assert the affirmative logic state of the local bus on the remote bus and to assert the affirmative logic state of the remote bus on the local bus.
When the two distant buses were connected by forward and backward transmission channels as described, a communication loop is established in which both buses become locked-up on the 0 volts level indicative of the affirmative logic state.
It is a major object of the present invention to provide suitable logic circuitry to be connected within separate forward and backward transmission channels for digital signals both extended between distant data bus systems as described, so that a communication over the transmission channels is possible from either bus to the other without lock-up of such system in either logic state.
According to the present invention there is provided a logic circuitry to be connected within a forward transmission channel for digital signals and a backward transmission channel for digital signals both extended between a local bus connected to at least one transmitter and one receiver at a local site and a remote bus connected to at least one transmitter and one receiver at a remote site, where each bus carries a first signal representing the non-affirmative logic state when all transmitters on this bus supply these first signals to it and each bus carries a second signal representing the affirmative logic state when at least one transmitter on this bus supplies this second signal to it, wherein the logic circuitry comprises first and second identical gating circuits, a first input to be connected to a point in the forward transmission channel,a second input to be connected to a point in the backward transmission channel, a first output to be connected to a point in the forward transmission channel, a second output to be connected to a point in the backward transmission channel and wherein the first gating circuit has an inhibit input connected to a first inhibit signal path responsive to signals from a point in the backward transmission channel between an output from the second gating circuit and the local bus, the second gating circuit has a second inhibit input connected to an inhibit signal path responsive to signals from a point in the forward transmission channel between an output from the first gating circuit and the remote bus, and the first and second gating circuits have such transfer functions that the second signal is caused to appear on the remote bus via the forward transmission channel,and is inhibited from being fed back to the local bus via the backward transmission channel, if any of the local transmitters supply the second signals to the local bus and no remote transmitter has caused a signal with the second voltage level to appear on the local bus, and the second signal is caused to appear on the local bus via the backward transmission channel and is inhibited from being fed back to the remote transmission channel, if any of the remote transmitters supply the second signal to the remote bus and no local transmitter has caused the second signal to appear on the remote bus.
It is to be understood that such logic circuitry could be connected either at the local ends or at the remote ends of the two transmission channels or at any points inbetween both buses.
According to a preferred embodiment, the first gating circuit and the second gating circuit are separate modular units, the first modular unit has a first input which corresponds to the first input of the logic circuitry, a first output to be connected to an input of the forward transmission channel, a second input connected to the first inhibit signal path to receive signals from an output of the backward transmission channel, and a second output which corresponds to the second output of the logic circuitry and is connected to the second input via an output signal path, the second modular unit has a first signal input which corresponds to the second signal input of the logic circuitry, a first output to be connected to an output of the backward transmission path,a second input connected to the second inhibit signal path to receive signals from an output of the forward transmission channel, and a second output which corresponds to the first output of the logic circuitry.
With these logic modules a symmetrical arrangement can be obtained in which both buses are connected to the transmission channels in the same manner and any delays present in these transmission channels are the same for both logic modules.
When the novel logic circuitry is to be used together with buses using "low for true' logic as precedingly explained, but "high for true" logic being used between the bus extenders, it can be preferably provided that the transfer functions of each of the first and second gating circuits established between their first outputs, their first inputs and their second inputs are NOR-gating functions, and the transfer functions between the second outputs and the second inputs of each of the first and second gating means are inverting functions.
According to another preferred embodiment it is provided that the inhibit signal path of, each of the first and second gating circuits has such a delay that a signal at the second input of either gating circuit becomes effective at the inhibit input of said gating circuit before it will become effective at the first signal input thereof.
This relationship between the propagation delays at the inputs of each gating circuit would not be needed, if there were provided sampling or chopper means between the gating circuits which interrupt the respective signal path for an amount of time sufficient in which the inhibit signal has become effective at the respective gate.
In cases where the novel logic circuitry is to be used in connection with buses which receive at substantially the same point in time from external sources binary signals representing the affirmative logic state, provision should be made for an alternating interruption of the transmission paths, e.g. by suitable sampling or chopping means so that these data signals do not become simultaneously effective at both gating circuits.
A preferred embodiment of the invention is now described with reference to the accompanying drawing. This drawing illustrates a fullduplex communication system established between distant buses for binary signals, which system incorporates the novel logic circuitry to overcome a lock-up condition of these buses on the voltage level L of the signals being transmitted.
Various transceiver devices 1 through 14 are connected in parallel by a local bus 16 which may for example have other lines not shown for bit-serial, byte-parallel data transfer.
Thereby a local bus-oriented bidirectional communication system may be established over a distance of up to about 20 metres. In this system each of the devices 1 through 14 may act as a transmitter of data to bus line 16 while any or all other devices may receive the signals from this transmitter via the bus lines..
The communication between these devices may be governed by a protocol involving sequences of operation on several similar lines, but is not part of this invention. Each of these devices is connected to the buses via driver circuits 17, 18 and receiver circuits 19, 20 which typically are designed in standard transistor logic. In the passive state of a device, the bus is kept on the nominal voltage level H of + 5 volts which voltage level defines the non-affirmative logic state. A signal from any of these devices which represents the affirmative logic state established a ground connection to the bus line concerned via a transistor in an open-collector driver circuit. Thus, this nominal zero voltage level L dominates or removes the voltage level H asserted by any remaining drivers on the bus.At a distance which may by far exceed 20 metres, there is provided a corresponding bus line 16' connected in parallel to devices 1' through 14' within a distance of up to 20 metres. Thereby a remote communication path is established, as described for the local end.
From the local bus 16 to the remote bus 16' extends a forward transmission channel for binary data with identical components as a backward transmission channel extending from the remote bus 16' to the local bus 16. Each transmission channel supplies signals to one of the buses via driver circuits 21 or 21', respectively, and receives signals from one of the buses via receiver circuits 22 or 22', respectively. The driver circuits and receiver circuits may be of known design and comply with the IEEE Standard 488.
The forward transmission channel and the backward transmission channel include binary channels 23 and 23', respectively. These binary channels may take different forms and are not part of the invention, but may include transmitters, receivers and delay elements in the transmission paths.
A first modular quadrupole 24 contains a NOR-gate 25 which has one input 26 connected to the output from the receiver circuit 22, an inhibit signal input 27 connected to a second input 28 via an inhibit signal path and an output 29 connected to an input of the forward transmission channel. The inhibit signal path is at one end connected to the output of the backward transmission channel. An output signal branch in the quadrupole 24 extends from the second input 28 to a second output 30 and contains an inverter 31.
A second modular quadrupole of the same design is connected at the remote end of the system in the same manner as described with the first quadrupole.
The various logic gates may be embodied in known transistor logic and it is to be understood that they could be replaced by other combinations of gates establishing the same logic functions.
The described quadrupole in the communication system of the drawing operates as follows:
Provided both buses are in their passive states and are kept at the voltage level H by means of the driver circuits 21, 21', signals with the voltage level L will appear at the outputs 29, 29' of the NOR-gates 25 and 25', and signals with the voltage level H will be supplied by the inverters 31, 31', to the associated bus drivers 21, 21' and buses 16, 16'. As a result both binary channels and the inhibit inputs of the NOR-gates will be at ground potential and the buses will remain to be at a positive voltage level.
It is now assumed that a device asserts a signal with a voltage level L on the remote bus 16'. Binary channel 23' will switch to a voltage level H and will cause to assert a voltage level L on bus 16, as is desired. It is important that because of the voltage level H appearing on the inhibit input 27 of NOR-gate 25, binary channel 23 cannot switch to the voltage level H, although a signal with the voltage level L will propagate from the inverter 31 via the driver circuit 21 and the receiver circuit 22 to the signal input 26 of NOR-gate 25. Thereby NOR-gate 25, as well as NOR-gate 25', act as blocking gates to prevent lock-up of the whole duplex system.
With each of the NOR-gates the propagation delay in the input signal path is smaller than that of the inverter, driver circuit and receiver taken together, so that a signal at the second input 28, 28' of either quadrupole 24, 24' becomes effective earlier at the inhibit input 27, 27' of a NOR-gate than at the signal input 26, 26' thereof.
If any of the devices 1 through 14 now asserts a signal with the voltage level L on bus 16, this voltage level will not be transmitted to bus 16' as there is still the voltage level H at the inhibit input 27 of the NOR-gate 25.
Since correct voltage levels exist at both buses, it does not matter that this signal from the devices 1 through 14 does not yet become effective. If thereafter none of the devices 1' through 14' should continue to transmit a signal with the voltage level L, then binary channel 23 will switch to a voltage level H and will thereby cause a voltage level L from any of the devices on bus 16 to be asserted correctly on bus 16'.
Among the various possible modifications within the scope of the invention of the illustrated circuitry are the following:
The logic circuitry in the quadrupole could be replaced by other combinations of gates establishing the same functions.
When "low for true" logic is also implemented on the binary channels, the NORgates should be replaced by OR-gates, an inverter should be connected in each inhibit signal path and the inverters in the output signal branches of the quadrupoles should be deleted.
When the correlation between the voltage levels and the logic states it reversed, inverters can be connected at both ends of the transmission channels.
As an alternative to the provisions of the correct relative propagation delays in the inhibit input paths, means should be provided in the binary channels to disable data transmission until the correct inhibit signal has become effective at the inhibit input of the NOR-gate concerned.
In applications where signals indicating affirmative logic states may occur substantially at the same point in time on both buses, provisions should be made to provide means, such as choppers or samplers, in both trans- mission channels which alternately interrupt the signal transfer.
Furthermore, the novel logic circuitry is useful for preventing a lock-up condition in connection with any separate pairs of signal transmission paths which enable a dupley communication between two distant ends.
The inventive concept could also be implemented with other digital signals, e.g. ternary signals or signals having frequency encoded logic states.