GB2073994A - Improvements in and relating to electrical mixers - Google Patents

Abstract

An electronic mixer especially for electrical audio signals comprising a plurality of inputs (I1 to I4), a plurality of outputs (O1 to O4), a common busbar (10) through which signals can be transferred selectively from any one or more inputs to any one output, a first circuit means (12) which preferably includes shift registers (58, 60, 62, 64) stepped by timing signals from a clock (66) to deliver binary control signals controlling the switching of the inputs in timed relationship to a continuous switching sequence of the outputs effected by a second circuit means (14) which preferably includes gate circuits (82) controlled by a ring of latch means (88, 90) actuated by pairs of timing signals derived from the stepping signals for the shift registers. <IMAGE>

Description

SPECIFICATION Improvements in and relating to electrical mixers Field of invention This invention concerns electrical mixers of the type used in broadcast studios, theatres, discotheques, cinemas and the like for mixing electrical audio signals from different input channels to transmit them to separate output channels. Such device may comprise a small portable unit having electrical sockets for receiving input signals and electrical sockets for delivering output signals with a plurality of switches and typically fader or volume control to allow signals to be mixed at different relative levels.

However, such devices are not limited to portable devices such as that just described but include larger units of a semi-portable nature and large desk type console units of a relatively permanent nature capable of handling a large number of different inputs and feeding and controlling a large number of different outputs. The term mixer is intended to mean any such device whether small or large and irrespective of the number of inputs and outputs.

Background to the invention Conventionally the routing of input signals to different output sockets is done by using rotating switches associated with each input channel. By pressing the appropriate switches so different input channels can be connected to different output channels and conventionally a flow diagram is associated with the switches so that it is evident by a quick inspection of a front panel how an electrical circuit can be established between any given input and any given output.

Whilst for the smaller mixer this type of arrangement is quite satisfactory the number of switches and the complexity of the unit becomes very considerable as the number of inputs and outputs increases. In addition, because the input channel will in general be equipped with switches which are sufficient for a certain number of outputs only, it is not possible to increase the number of outputs on any given system without virtually rebuilding the mixer. This is a common problem since invariably the demands on a mixer with time tend to exceed its capabilities and this would appear to particularly the case with regard to the number of outputs which a mixer is called on to supply.

It is an object of the present invention to provide an improved form ofmixerwhich not only provides the normal facilities for routing between inputs and outputs but allows four an extension of the number of outputs to be made without the need for major re-engineering. A mixer constructed in accordance with the invention will, therefore, be capable of expanding the number of outputs which can be controlled from the inputs.

It is another object of the present invention to provide a mixer in which the routing between the inputs and outputs can be programmed independence of the number of outputs which are to be supplied.

It is a still further object of the present invention to provide a mixer in which a degree of automation can be built-in the form of pre-programmed routing through the mixer, with the facility for the preprogrammed routings to be called up quickly and easily.

The invention According to the present invention in a mixer having a plurality of inputs, a plurality of outputs and means for interconnecting any of the inputs to any of the outputs, a common bus bar is provided for transferring signals from inputs to outputs and first circuit means is provided for sequentially connecting some or all ofthe inputs to the common bus bar for short periods of time and second circuit means is provided for similarly so connecting the outputs in sequence to the bus bar, the first and second circuit means being synchronised so that only the appropriate inputs are connected to the common bus bar as each output is connected thereto.

In a simple example of a mixer having two inputs and two outputs and a requirement that input one shall appear on outputs 1 and 2 but input 2 shall only appear on output 2, the second circuit means is arranged to connect the two outputs alternately to the bus bar and likewise the first circuit means is arranged to permanently connect input 1 to the bus bar to only alternately connect the second input to the bus bar so that its sequence of connections thereto coincide with the sequence of connections of the second output to the bus bar.

This simple example is only intended to be illustrative of the principle which can of course be extended to any number of inputs and outputs and it is merely necessary for the outputs to be connected to the bus bar in sequence, the number of outputs determining the nunber of connections in a complete sequence before it is repeated to allow the system to work. The sequential switching of the inputs is dictated by the sequential switching of the outputs and it is this feature which allows a mixer constructed in accordance with the present invention to be extended so as to accommodate more or less output.

Clearly the sequential connections of the different inputs and outputs should not be noticeable in the final output signals and to this end the switching rate must be very high. Atypical switching rate is one which causes each output to be connected for a period of 5 micro seconds inturn to the bus bar. If there are twenty outputs the period of time between each connection for each output is 100 micro.

seconds. If there are only five outputs the period of time is only 25 micro. seconds.

In a preferred arrangement embodying the invention, the outputs of the mixer are continually connected in sequence of short periods of time to a common bus bar and the first circuit means includes memory means for storing a sequence of control signals for controlling the connection of each of the inputs to the bus bar. Preferably the memory means is programmable to allow each input to be connected to the bus bar for either none some or all of the sequence of time interval making up the complete scan of all the outputs.

According to another preferred feature of the invention, the means for programming the memory means comprises a key board by which binary electrical signals can be set up for inserting into the memory means associated with the first circuit means.

In order to provide for automation and to facilitate the generation of the data required for the memory means in the first circuit means, a micro processor is employed. The micro processor includes random access memory within which binary information is stored corresponding to the data required to be stored in the memory means of the first circuit means to produce the requisite switching of inputs to the bus bar. The input connections can be altered by altering the date in the memory means associated with the first circuit means and this inturn is controlled by the data in the random access memory in the micro processor.

In a preferred arrangement switch means is provided for indicating to the micro processor that a revision of the data in its random access memory is required and an electrical signal is generated in response to operation of the switch means to terminate the normal functioning of the mixer whilst the micro processor memory is updated. After entering in the required revised connections via the key board, the micro processor memory is updated and thereafter the updated information is supplied to the memory means in the first circuit means so that the latter will now control the connections of the inputs to the bus bar in accordance with the new data.

Once the new data is in the first circuit means memory the electrical signal derived from the switch means previously referred to can be negated or cancelled to allow the mixer to revert to normal functioning but now with the revised data in the memory means associated with the first circuit means so that the new routing between inputs and outputs are now available.

According to a preferred feature of the invention, the memory means associated with the first circuit means comprise shift registers, one shift register for each input, and the output of the shift register is used as the control voltage for a voltage controlled amplifier again one such amplifier for each input.

The input signal is only transmitted to the mixing bus bar when the voltage controlled amplifier associated with that input receives an appropriate signal from the shift register. Since the shift register output will either be a one or a zero, one of these states is arranged to render the voltage controlled amplifier functional and the otherto blockthe amplifier.

According to another feature of the invention, the output of each shift register is made available for recirculation to the input of the shift register through a multiplexing circuit which has two states, a first state in which information for the shift register is simply recirculated so that the routing pattern for that particular input is maintained in the shift register at all times and a second state in which the re-circulation of information is interrupted and fresh information from the micro processor is made available to the input of the shift register for insertion therein.

By providing a multiplexer for each shift register associated with each input, it is a simple matter to dump the data contained in the shift registers and substitute therefore a fresh set of data from the micro processor random access memory by switching all the multiplexors simultaneously from one state to another and feeding to the input to the first multiplexor the information to be stored in the shift registers in serial form. By interconnecting the output of each shift register with the input of the next following multiplexor so the serial information ap piied to the input of the first multiplexorwill be entered into all of the shift registers and it is merely necessary to ensure that the information in serial form is supplied in the correct sequence so that the correct data is entered into the shift registers as required.

According to another feature of the invention, a plurality of Sample and Hold circuits are provided, one for each output, each Sample and Hold circuit serving as a gate for connecting the common bus bar to its respective output. Control signals for the Sample and Hold circuits to cause them to connect the outputs in sequence to the bus bar are conveniently derived from a ring of data latches each of which operates as a bi-stable device and is switched from a first to a second state and vice a versa depending on the condition of the preceding latch.

Switch over is restricted to the timing points determined by a clock signal and all of the devices are preferably inter-connected in such a way that a signal along the common inter-connection will cause an identified 1 of the bi-stables to set and all of the others to reset (or vice a versa) so as to enable a known starting condition to be obtained. Preferably this starting condition is consistant with a control signal to the sample and hold circuit controlling the first output so that by applying the signal along the said common inter-connection, the latches are controlled into an initial condition in which the first output is supplied with the signal from the common bus bar via the appropriate Sample and Hold circuit.

By arranging that the signal along the common inter-connection overrides any other operation of the latches, so the output circuits can be frozen into this condition for as long as the signal is maintained on the common inter-connection.

In order to ensure that the Sample and Hold device associated with each output does not operate whilst data from the common bus bar is indeterminate (i.e.

during the transitions of the input shift registers) each of the ring of latches is conveniently comprised of two latches operating in tandem and two clock pulses are supplied to the ring at each input shift register transition. The first clock pulse is arranged to trigger the first latch in a pair of latches and the second clock pulse is arranged to trigger the second latch after a pre-determined interval of time which is selected so as to correspond at least to the time required for a transition of the input shift registers.In this way the Sample and Hold circuit for each output is only triggered into an active condition after a transition of the input shift registers and by arranging that each latch reverts to its non active state at the beginning of the next pair of clock pulses supplied to the ring, so the Sample and Hold circuit for each output will only remain active over a period of time during which the information on the common bus bar is coherent.

The production of the special clock pulse pairs is conveniently achieved by splitting the conventional rectangular waveform clock pulse signal and supplying two pulse shaping channels therewith, in the first channel differentiating the leading edges of the clock pulses and in the other channel integrating the leading edges of the clock pulses. After differentiation and integration in the two channels, trigger pulses are produced using NAND SCHMITtriggers.

From the differentiated leading edge will be obtained a short duration pulse which if required can subsequently be inverted to produce a short duration clock pulse atthe beginning of each timing period and from the Schmit trigger supplied with the integrated leading edge signal, is obtained a rectangular waveform pulse of duration equivalent to the original timing pulse but shifted in time by an amount which is determined by the time constant of the integrating circuit.As with the timing pulse obtained by differentiation of the leading edge, subsequent inversion can be employed to obtain a correct plurality timing pulse if so required and a combination of the short duration timing pulse from the first channel and the phase shifted timing pulse from the second channel gives a pair of timing pulses towards the beginning of each of the timing periods which is the form of signal required for the ring of pairs of bi-stable latches previously referred to.

It will be seen that if additional outputs are required, it is merely necessary to break the ring of latches controlling the outputs and insert into the ring additional pairs of latches and connect between the additional output terminals and the common bus bar a corresponding number of additional Sample and Hold circuits which are in turn connected to the added latches.When the ring of latches is completed, the timing pulses supplied thereto will simply cause the data in the latches to be circulated around the larger ring and this in turn will simply cause the larger number of Sample and Hold circuits to be connected one after the other to the common bus bar thereby connecting the outputs under their control to the bus bar, in strict rotation, and after re-programming the input shift registers with the relevant data, the mixer can be rendered functional once again with the larger number of outputs all under control.

It will be seen that by employing appropriate connectors, the addition of new latches and Sample and Hold circuits for controlling additional outputs can be effected on a plug-in module basis if so required.

The invention will now be described by way of example with reference to the accompanying drawings.

In the drawings Figure lisa block circuit diagram of a simple mixer having four inputs and four outputs embodying the invention.

Figure 2 is a more detailed block circuit diagram of the input circuits of the mixer.

Figure 3 is a more detailed circuit diagram of part of the output circuits of the mixer.

Figure 4 indicates the various timing pulses required for controlling the output circuits.

Figure 5 is a detailed block circuit diagram of part of the main control circuit for the system shown in Figure 1.

Figure 6 illustrates graphically the waveforms from the control circuit of Figure 5.

Figure 7 is a circuit diagram of another part of the main control of the system shown in Figure 1.

Figure 8 is a graphical representation of the waveforms obtaining in the circuit of Figure 7.

Figure 9 is a circuit diagram of a voltage controlled amplifier as employed in the input circuits of Figure 2.

Figure 10 is a circuit diagram of a Sample and Hold circuit as employed to connect each output to the common bus bar (Reference Figure 3).

Figure 11 is a circuit diagram of a multiplexer as employed in the input circuit of Figure 2, and Figure 12 is a view of a complete mixer unit constructed as one embodiment of the invention.

Detailed description of the drawings A diagram of an overall system embodying the invention is shown in Figure 1. The system includes four independent inputs 11 to 14 and four outputs 01 to 04. The four inputs are connectable to a common bus bar 10 via a first circuit 12 and the four outputs are also connectable to the common bus bar via a second circuit means 14.

Control signals for the circuits 12 and 14 are derived from a master control unit 16 which itself can be controlled and programmed by means of a control panel 18 which may include a visual display 20 for indicating the connections which have been set up or may include a print out device 22 which can be arranged to print out the connections established between inputs and outputs either as they are entered or in response to a suitable command given by the control panel 18. A further display device 24 may be provided to indicate by means of a numerical display those routes which have been established between the inputs and outputs.

Information is stored in memories in the master control unit 16 and in the circuit 12 (to be described hereinafter) and the insertion of data into the memories and the deletion of data from the memories controlled by a key board containing buttons labelled 0 to 9 and designated by reference numeral 26 and six special function buttons 28 to 38 inclusive, the functions of the buttons being set out below: Button 28 - function enter input data Button 30 - function enter output data Button 32 - function load data Button 34- function cancel data Button 36 - function select pre-set patch Button 38 - function look Additional special function controls 40 and 42 may be provided the functions of which are as follows:: Button 40 - function print out programmed rout ings Button 42 - function display programmed routings Still further special function button may be provided namely button 44 to allow data relating to a particular programme of routings to be stored in a memory which may be incorporated into the mixer (but is not shown in the drawings) or may be a separate memory which may for example be a cassette or a so called erasable re-programmable memory. The advantage of this further refinement is that any particular programme of routings set up using the key board and the memories in the master control 16 and circuit 12 will be lost in the event of loss of power to the unit. Typically the power supply will be internal batteries or may be derived via a power supply unit (P.S.U.) 46 from the alternating current supply mains.By providing an additional memory into which the data relating to any particular programme of routings can be loaded, so the data can be stored indefinitely whether or not the power supply to the unit is maintained or removed.

Particular description of circuits The circuits 12 associated with the four inputs 11 to 14 are shown in more detail in Figure 2. Each of the inputs is connected to a voltage controlled amplifier 48,50,52 and 54 and the outputs of the amplifier 48 to 54 are connected to a common bus bar 56.

Signals for controlling the amplifiers 48 to 54 are obtained from the outputs of four shift registers 58 to 64 and one typical set of binary data in the shift registers is shown corresponding to one particular programme of connections between inputs and outputs. To facilitate an understanding of the operation of the circuit, Figure 2A shows diagrammatically the various operating conditions of inputs and outputs during four timing intervals dictated by a master clock within the master control circuit 16.

Typically the timing intervals are five micro second durations and whether or not any particular input is connected to the common bus bar 56 during any one particular timing interval will be determined by the output state of the shift register associated with that input.

Each shift register is supplied with timing pulses (CK) from the master control circuit 16 which causes the data in the shift register to be shifted at the end of each five micro second timing interval.

The data input of each shift register is connected to the output of a multiplexing circuit 66,68,70 or 72 respectively and the detail of each multiplexing circuit and its associated connections with its related shift register is given in Figure 11.

Referring to Figure 11, each multiplex circuit is based on a Tristate buffer amplifier which is a device having an input and an output and a control input which when a control signal is present allows the device to function normally but when the control signal is absent causes the output of the device to appear as a high impedance. When the device is operating normally the output impedance is low.

The Tristate buffer amplifiers are designated by reference numeral 74 in Figure 11 and the control input is denoted by reference numeral 76.

The data input of the first Tristate buffer (i.e. that associated with input 1) is connected to the data output of a micro processor chip (to be described hereinafter) located within the master control circuit 16 whilst the input of each of the following Tristate buffer amplifiers is connected to the output of the preceeding input shift register.

A high resistance 78 is connected between the input and output of each shift register 58 to 64 and it will be seen that when the Tristate buffer 74 associated therewith is not functioning normally (i.e.

the toggle signal on line 76 is absent) the high output impedance of each of the Tristate buffers 74 will allow a recirculation of the data from the output to the input of each shift registervia its associated feedback resistor 78 (see Figure 11) and in the absence of the toggle signal on line 76, the output data from each shift register will not be transferred through the following Tristate buffer.

Data can be entered into the shift registers by presenting the data serially to the data input 80 of the first Tristate buffer and whilst the data is to be entered, supplying a toggle signal to the control inputs 76 of each of the Tristate buffers of 74. The outward impedance of each of the Tristate buffers will immediately become very low and recirculation of data via resistors 78 will be inhibited and instead data appearing at the data input 80 will be transferred via the first buffer 74 to the input of the first shift register 58 and the output of each shift register will be transferred to the input of the next shift register via the intervening Tristate buffer amplifier 74. Data for the fourth shift register 64 must, therefore, be entered first and thatforthe preceeding shift registers 62,60 and 58 in turn thereafter.

After all the data has been entered, the toggle signal is removed thereby allowing subsequent timing pulses CK to circulate the data currently stored in each of the shift registers to maintain this data for association with each of the inputs.

Referring to Figure 2A, during each four successive timing intervals, the inputs 1 and 3 are connected to the common bus 56 during the first of these timing intervals, input 2 is connected to the common bus during the second of these intervals, inputs 1 and 4 are connected to the common bus during the third timing interval and inputs 1,2 and 3 are connected to the common bus during the fourth time interval. The pattern of connections of inputs to the common bus is repeated every four timing intervals.

The function of the circuit 14 is to ensure that the outputs 01 to 04 are only connected to the common bus when the appropriate inputs are connected and it is arranged that the outputs 01 to 04 are separately connected in succession to the common bus 10 by appropriate timing signals and to a first approximation the output 01 is connected to the common bus 10 during the first timing interval of each sequence of four, output 02 is connected during the second timing interval, output 03 is connected during the third timing interval and output 04 during the fourth timing interval of each sequence, again the pattern of connections is repeated everyfourtiming intervals.

Since the outputs are disconnected from the common bus except when they are so connected, the programme of connections between inputs and outputs can be stated as follows: Inputs 1 and 3 supply output 01 Input 2 supplies output 2 Inputs 1 and 4 supply output 03, and Inputs 1,2 and 3 supply output 04.

Details of the manner in which the outputs 01 to 04 are connected to the common bus are contained in Figure 3 which should be read in conjunction with Figure 1. Figure 3 shows part ofthe circuit contained within circuit 14 of Figure 1. Output 01 is shown connected to the output of a Sample and Hold circuit details of which are shown in Figure 10. The input to the circuit is connected to the common bus 10 along with the inputs of three other Sample and Hold circuits similar to circuit 82 and each connected to one of the other outputs 02, 03 and 04.

The Sample and Hold circuit isolates its associated output from the common bus 10 except in the presence of a control signal along a line 84 feeding the Sample and Hold circuit.

Control signals for the circuits 82 are derived from a ring of latches part of which is shown in Figure 3.

The latches are arranged in pairs (for a reason which will be described later) and the control pulseforthe circuit 82 is derived from the Q output of the second latch of each pair. Each latch is a bi-stable device having a set and a re-set control input (S or R respectively) and a data input (D). When the data input is high, the Q output will be high and when the data input is low the Qoutputwill also be low. The O output will be driven high by a signal applied to the S (set) input and will be driven low by a signal applied to the R (re-set) input.

The Q output of the last of the latches is connected to the data input D of the first of the latches so as to form the ring and there are four pairs of latches in the ring for the four outputs 01 to 04, although only one of the pairs of latches is shown in Figure 3.

The latches only change the 0 output conditions in the presence of a timing pulse applied along line 86.

Timing pulses for line 86 are derived from a special circuit shown in Figure 7 and described with reference to Figure 8.

Referring again to Figure 3, the two latches associated with output 1 are denoted by reference numerals 88 and 90. Each is identical and the operation of the circuit is best understood by reference to Figure 4.

The timing pulses along line 86 are shown in Figure 4C and it will be seen that for each timing interval T there are two timing pulses a short one 92 followed by a longer one 94.

The ring of latches is provided merely to circulate a high data level around the ring and to transfer the high data level from one latch to the next latch as each timing pule appears. It is thus necessary to ensure that a high data level corresponding to a high 0 output appears in one of the latches at some instant in time whilst the 0 output of all other latches in the ring is low. To this end the toggle line 96 is connected to the S input of the last latch 91 in the ring and is connected to the re-set input (R) of all the other latches in the ring.

When a toggle pulse is applied to line 96, the Q output of latch 91 is driven high and the Q output of all other latches is driven low. At the end of a toggle pulse, the first incoming clock pulse on line 86 causes the high Q output of latch 91 to appear at the 0 output of latch 88 and the second incoming timing pulse 94 causes the high Q output of 88 to be transferred to the Q output of 90 to provide the control pulse along line 84 for the first output 01 Sample and Hold circuit 82.

Although in theory a single latch 90 would be sufficientforeach output 01, the preliminary latch of each pair is provided so as to obviate any possibility of an output such as 01, 02 etc., being connected to the common bus 10 during the transition of data within the shift registers 58, 60 62, and 64. The transition periods are shown in Figure 4A at 98, 100 and 102. It will be seen that the transition period is relatively short but is nevertheless a finite period of time and in order to inhibit the connection of an output such as 01 to the bus 10, the first short timing pulse 92 is used to generate a high Q outputforthe preliminary latch 88 and this output of 88 is shown at 104 in Figure 4D.

The subsequent longer timing pulse 94 transfers this high level to the Q output of latch 90 which is shown at 106 on Figure 4E.

The timing pulses on line 86 are derived from master clock pulses denoted by reference numeral 108. 110, 112 and which are shown diagrammatically in Figure4B.

The master control circuit 16 includes a micro computer chip (sometimes referred to as a micro processor) and reference is now made to Figure 5 for details of part of the master control circuit. The micro computer chip is designated by reference numeral 112, and is typically a micro computer chip type 8048 from INTEL INC.. The power supply connections for the chip are not shown but the data output connection and the timing pulse connections obtainable from the chip are shown in Figure 5.

To begin with the chip 112 includes a master oscillator and pulse generator circuit for providing timing pulses at the ALE output for controlling the shift registers 58 etc., associated with the inputs.

The frequency of the timing pulses is 200 kilohertz and the pulses are supplied through a Tristate buffer amplifier 1 to the output terminal 116. This supplies the timing pulses to the shift registers previously mentioned.

The buffer 114 is paralleled with anotherTristate buffer amplifier 118 which is connected between the terminal 116 and another output of the chip 112 namely a terminal labelled CK. The chip 112 is arranged to produce timing pulses at CK after a new set of data has been assembled within the chip memory (not shown) under soft wear control as will hereinafter be described. It will be seen that the buffers 114 and 118 act as a changeover switch so that terminal 116 is supplied with 200 kilohertz timing pulses from the ALE output or is connected to the CK output of the chip but never to both at the same time. Toggle signal from the TG output of the chip 112 is used to control the operation of the two buffers 114 and 118 and to this end the toggle signal is supplied to the control input of buffer 114 via an inverting amplifier 120.The toggle output TG is isolated from the toggle output terminal 122 by means of a further buffer amplifier 124.

A signal at the toggle output TG and consequently at the terminal 112 indicates that a change of data is to take place and the presence of the toggle signal is used to inhibit any normal function of the mixer. To this end the toggle system is applied as a control signal to a further Tristate buffer amplifier 126. This latter amplifier serves to control the connection of a data output terminal D of the chip 112 to the data input terminal 128 of Figure 2. It will be seen that data can only be transferred to terminal 128 in the presence of a toggle signal.

The waveforms of the pulses at the terminals 116,128 and 122 of Figure 4 are shown in Figure 6.

Terminal 122 signal is shown in Figure 6A, a typical train of data as may appear at terminal 128 is shown in Figure 6B and the timing pulses which will appear at terminal 116 are shown in Figure 6C. Itwill be noted that the frequency of the timing pulse differs as between the period when a toggle pulse such as 130 is present and a period when such a pulse is absent. This arises from the fact that the soft wear controlled timing pulses supplied from the CK output on the chip 112 and designated by reference numeral 132 will normally be at a very much lower frequency than the 200 kilohertz pulses 134 supplied from the ALE terminal of the chip 112.

Although the timing pulses are shown as being continuous, in practice there may be a gap between the end of the pulses 134 and the beginning of pulses 132 which corresponds to the time required for the chip 112 to assemble the new data which has to be transmitted by the soft wear generated timing pulses 132.

The pulses 108,110 and 112 of Figure 4 correspond of course to the pulses designated 134 or 132 in Figure 6C. However, these pulses have to effectively be split to provide the control pulses required for the timing inputs of the latches 88 90 etc., in the ring of Figure 3. The splitting up of the timing pulses 108, 110 etc., is achieved by the circuit of Figure 7.

The master clock pulses 132 or 134 are applied to terminal 136 and the signal appearing at this terminal is differentiated by a circuit comprised of capacitor C1 and resistor R1 and is intergrated by a complimentary RC circuit R2C2. The differentiated signal is converted into rectangular pulses by a NAND SCHMITtrigger device 138 in which the two inputs are strapped and the integrated signal is similarly formed into a pulse by means of a further NAND SCHMIT trigger device 140.

The narrow pulses appearing at junction 3 in Figure 7 are inverted by a further NAND SCHMIT trigger 142 whilst a further NAND circuit 144 this time without its two inputs strapped serves to combine and also invert the differentiated pulses from junction 3 and the integrated pulses from junction 6 of Figure 7 to form the two timing pulses required for the latch ring at terminal 7 in Figure 7.

To this end line 86 of Figure 3 is shown connected to terminal 7 in Figure 7.

Waveforms of signals appearing at junctions 1 to 7 in Figure 7 are shown in Figures 8A to G.

Reverting once again to Figure 5 the chip 112 includes a random access memory (RAM) not shown, into which binary data which is to be inserted into the shift registers 58 etc. is stored. The binary information can be inserted into the memory by means of the key board and in particular the button marked 26 in Figure 1. In a similar manner the key board can be used to amend or erase binary information within the RAM and once the data in the memory is correct, the contents of the memory can be transferred as a serial data stream to the shift registers 58 to 64 in the manner previously described by initiating a toggle pulse and feeding the data to terminal 128 Figure 2.

The operation is simplified by an appropriate programme contained within the memory capability of the chip 112 so that the method of inserting the binary data needed to establish a particular route between one input (for example 12) and one output (for example 03) is set up and entered into the shift registers 58 to 64 by simply adopting the following routine.

1. Depress button 28, 2. Enter number of input channel using key board 26 3. Depress button 30 4. Enter output channel no. via key board 26 5. Depress load button 32.

The act of depressing the load button 32 serves to generate a toggle pulse of predetermined duration such that the contents of the RAM within the chip 112 is transmitted in serial form to the terminal 128.

At the end of the toggle pulse, the mixer circuits resume normal functioning.

In the event that any particular route between one input and one output is to be cancelled, the same procedure is followed as outlined above except that the last button to be depressed is the cancel button 34 instead of the load button 32.

Also within the chip 112 is a read only memory containing data for establishing a number of predetermined routing patterns between the inputs and outputs. Each such routing pattern is referred to as a pre-set patch. If one of the pre-determined patterns of routing is required, the pre-set patch button 36 is depressed and the particular pre-set patch data is selected by depressing an appropriate number combination on the key board 26. Under its own internal programme the chip then transfers the pre-set patch data to the shift registers 58 to 64.

It is to be noted that in this connection an alternative is possible. The information from the read only memory (ROM) may be transferred first to the RAM within the chip and thereafter to the shift register 58 to 64. This however, effectively cancels any data already stores in the RAM and therefore cancels any established routing pattern previously set up using the key board. Alternatively the data from the ROM can be transferred directly to the shift registers 58,64 thereby preserving the data within the RAM for subsequent address and transfer to the shift registers.

As previously mentioned, the console may include a visual digital display of the inputs and outputs which have been selected at any one time by the key board. To this end the visual display conveniently comprises a first window 146 and a second window 148. The window 146 is arranged to display the numerical value of the output channel selected immediately after button 30 has been depressed and the window 148 includes a digital display device (not shown) for displaying the numerical value of the input channel selected by the key board 26 after the last depression of the key 28. Where more than nine channels of output or input are required, two digit displays are required in the windows 146 and/or 148.

A further function can be built into the programme of the chip 112 under the control of the last button 38. This is labelled look and when depressed is arranged to initiate a series of pulses for reading the contents of the RAM within the chip and displaying the stored information as digits in the two windows 146 and 148 as a succession of routings. Thus if the memory containes data which will connect input 1 to output 1 then one of the digital displays will show 1 and 1 in the two windows. If another routing which has been set up in the RAM will serve to connect output 2 to input 1 then another digital display will present the two numbers 1 and 2.

The generation of the control signal under the control of the look button 38 is arranged to last for as long as is necessary to read the entire contents of the RAM after which the control signal terminates.

The look button 38 may, of course, be used to control a print out device 22 (previously referred to) so as to print out at the same time as or instead of displaying the information in digital display devices such as the windows 146 and 148 of display 24. The print out is typically of the roll feed type as employed in desk top calculators and the like. As with the display 24, the information contained for each routing in the print out need only comprise two digits suitably separated so as to indicate on the left the for example the output numer and on the right the input channel number for each routing contained within the memory.

The VDU 20 previously referred to may also be controlled by the chip 112 and related circuitry (not shown) so as to set up on the screen a pictorial representation of the input channels and the output channels suitably identified by number and to indicate by a series of lines which input channels are connected to which output channels.

Figure 9 containes the detailed circuit of one of the voltage controlled amplifiers such as 48 50 etc., The input such as input 1 is supplied via a resistor R3 to one input of an integrated circuit chip 152. The other input of which is grounded through resistor R4. The output of the device 152 is connected to the common bus 56 which corresponds to the bus 10 of Figure 1.

The control signal for the device 152 is obtained from the positive rail via a resistor R5 and a PNP transistor 154 the basis current of which is derived from the output of one of the shift registers such as 58 in the case of amplifier 48. The output of the shift register is supplied through a resistor R6 and a light emitting diode 156 serves to show whether the device 152 is being controlled into an active state.

Clearly if one of the inputs is being used the light emitting diode will glow but in the event that it is not being used the light emitting diode will never turn on since none of the data within the associated shift register will produce a high output.

Lastly Figure 10 indicates the detailed circuit of one of the Sample and Hold circuits employed in the output circuit 14. The Sample and Hold circuit bonds to the circuit 82 of Figure 3 and the input from the common bus 10 (56 in Figure 2) is supplied to one input of another intergrated circuit amplifier 158 similar to the amplifier 152 of Figure 9. The device is an operational transconductance amplifier and is controlled along line 84 in the manner previously described. When active, a charge is built up on compensating capacitor C3 which is buffered by means of the field effect transistor 160. A resistor R7 is connected in series with capacitor C3 and the output is derived across the resistor R8 in the output circuit of the field effect transistor 160. The output signal appears at junction 162 which corresponds to one of the output terminals of the mixer unit.

A feedback circuit comprised of resistor R9 and capacitor C4 controls the operation of the amplifier in its active condition.

The input to the amplifier 158 from the common bus 10 (56 in Figure 2) is supplied to the other balanced input of the amplifier 158 and the signal is developed across a resistor R10.

Figure 12 of the drawing illustrates one form of mixer embodying the invention. The mixer shown has eight input channels and two output channels.

The input channels are contained on two plug-in modules 164 and 166 each module containing four inputs and the two output channels are contained within another plug-in module 168. The output module 168 and one of the input modules 164 are plugged into opposite sides of a central processor control unit 170 which includes the key board 26.

A power supply and fold back control circuit module 172 is shown piugged into the output module 168 to complete the mixer.

It is to be understood that the mixer shown in Figure 12 does not include a VDU display or print-out module 22 nor does it include the addition functional controls such as 40,42 and 44 previously referred to with regard to Figure 1.

Components list Tristate buffer amplifier IC (for use in m ultiflexors 66 etc and 114 etc) Type - RCA 40109 Shift registers (for use as I/P memories 58 etc) Type RCA 4006 Microcomputer chip (device 112 in Figure 5) INTEL Inc Type 8048 NAND Schmidt triggers (devices 138 etc) 1/4 - Type RCA 4093 Voltage controlled amplifiers (for use as amplifiers 152, 158 etc) Type - RCA CA 32-80

Claims (21)

1. An electronic mixer comprising a plurality of inputs, a plurality of outputs, a common busbar through which signals can be transferred selectively from any one or more inputs to any one of the outputs, first circuit means for switchingly connecting differing combinations of one or more inputs to the busbar sequentially each combination for a short period of time, and second circuit means for switchingly connecting different outputs to the busbar in sequence each for a short period oftime, and synchronising circuit means for substantially synchronising operation of the first and second circuit means so that differing selected combinations of inputs are connected to the busbar respectively at the same times as different outputs are connected thereto.

2. An electronic mixer according to claim 1, adapted to handle electrical audio signals, wherein the switching rate is sufficiently high in relation to the number of outputs that interruptions in the output signals due to inputs and outputs switching actions are not discernable to the human ear.

3. An electronic mixer according to claim 2, wherein the switching rate is one which connects each output in turn to the busbar for about 5 microseconds.

4. An electronic mixer according to any of claims 1 to 3, wherein the outputs are scanned to connect each one in turn to the busbar in a time continuous sequence.

5. An electronic mixer according to claim 4, wherein the first circuit means includes a memory for storing a sequence of control signals for controlling the switching of the inputs.

6. An electronic mixer according to claim 5, including means for entering data into the memory to allow each input to be connected to the busbar for none, some or all of each time interval covering a complete scan of the outputs.

7. An electronic mixer according to claim 6, wherein the data insertion means includes a keyboard for initiating the supply of binary electric data signals to the memory.

8. An electronic mixer according to claim 7, including a microprocessor having a RAM within which inputs switching data in binary form can be stored and updated, the RAM providing the said binary electric data signals to the memory of the first circuit means.

9. An electronic mixer according to claim 7 or claim 8, including switching means for interrupting the normal inputs/outputs switching function through the busbar at least during supply of data signals to the memory of the first circuit means.

10. An electronic mixer according to any of claims 5 to 10, wherein the first circuit means memory comprises a shift register and a voltage controlled amplifier for each input, the binary level outputs of each shift register respectively unbiocking or blocking the associated amplifier to control the switching of the inputs to the busbar.

11. An electronic mixer according to claim 10, wherein each shift register is fed at its input side through a multiplexer having two states in one of which the data in the shift register is recirculated and in the other of which data signals can be supplied to the memory while recirculation of data is interrupted.

12. An electronic mixer according to claim 11, wherein the shift registers are serially connected, the input side of each multiplexer following the first being connected to the output side of a preceding shift register.

13. An electronic mixer according to any of claims 1 to 12, including a sample and hold circuit one for each output, each sample and hold circuit acting as a gate for controlling the switching of the outputs of the busbar.

14. An electronic mixer according to claim 13, including a ring of bi-state data latch means, one for each sample and hold circuit, supplying control signals to the sample and hold circuits to control the gating actions thereof, each latch means being switched between its two states according to the state of the preceding latch means in the ring.

15. An electronic mixer according to claim 14, including a clock control providing a timing signal fed to the ring of data latch means to control the states thereof.

16. An electronic mixer according to claim 15, wherein each data latch means comprises two latches connected to operate in tandem, the first latch being triggered by the first of a pair of timing signals supplied to the ring of latch means at the beginning of an inputs switching action and the second latch being triggered by the second of said pair of timing signals which follows the first after a time period not less than the interval during which said inputs switching action is completed.

17. An electronic mixer according to claim 16 when appendant to claim 10, wherein the shift registers are supplied with clock controlled switching signals to control the inputs switching action.

18. An electronic mixer according to claim 17, wherein the pairs of timing signals for the latches are derived from the shift register switching signals, the first of said pair of timing signals by differentiating the leading edge of a switching signal and driving a Schmitt trigger with the differentiated signal,the second of said signals pair by integrating the leading edge of the switching signal, driving a second Schmitt trigger with the integrated signal, and differentiating the leading edge of the second trigger output, whereby two timing pulses are derived at the beginning of a switching signal, which timing pulses are spaced by an interval predetermined by the time constant of integration.

19. An electronic mixer according to any of claims 1 to 18, including means for displaying which inputs and outputs are selectively connected in sequence through the busbar.

20. An electronic mixer according to claim 19 when appendant to claim 8, wherein said displaying means comprises means for reading the contents of the RAM in the microprocessor and a binary signal display for displaying the read-out contents.

21. An electronic mixer substantially as hereinbefore described with reference to the accompanying drawings.