GB2039106A

GB2039106A - Number format conversion in computer Fig 3A

Info

Publication number: GB2039106A
Application number: GB7944622A
Authority: GB
Original assignee: Honeywell Information Systems Italia SpA; Honeywell Information Systems Inc
Current assignee: Bull HN Information Systems Italia SpA; Bull HN Information Systems Inc
Priority date: 1979-01-02
Filing date: 1979-12-31
Publication date: 1980-07-30
Also published as: GB2039106B

Abstract

A pure binary number of up to 4 characters, each of 8 or 9 bits, is stored in adjacent bytes in the memory of a machine using 4-byte words, with 9 bits per byte. To read the number from memory into an addressable register RX0-RX7, RA or RQ in a form suitable for arithmetic, the word (or the 2 words) storing the number are read into a data in register RDI. A byte-wise left shift by a shifter SHF left justifies the byte of the number into an intermediate register RIM, then the appropriate position of a format switch 52 is selected to right-justify the number as it enters the addressable register, to pack the characters together if necessary, and to sign extend the number if desired. The reverse format switching and shifting is performed to store the number back in memory. A 1 or 2 character number can also be right- justified to a half-word boundary.

Description

SPECIFICATION Number format conversion in computer This invention relates to apparatus implementing instructions for moving a binary number between a word addressable memory in which the number may be in a form incompatible with its use in computations, and an addressable register in which the number is in a form compatible with it being used or operated on as a pure binary number.

Digital data processing systems are optimized to handle groups of a given number of bits in parallel, or as an entity, such a group of bits being termed a word (machine word).

A word in turn is often defined as including a plurality of bytes with each byte containing a given number of bits. There is no agreed to standard for the number of bits to a byte.

Some computer equipment manufacturers have standardized their equipment to use an 8 bit byte and others to use a 9 bit byte. Here, the word byte when used without a prefix or modifier will mean a 9 bit byte.

Some data processing systems organize their memories, or working store, on the basis that each addressable memory location stores a machine word. Others are organized so that each addressable memory location will store a byte, most commonly an 8 bit byte. Either type of computing system when required to operate on, or process, binary numbers will generally restrict or limit a binary number to a given number of characters where a character in an 8 bit byte machine will be 8 bits, an octet, and in a 9 bit byte machine will be 9 bits, a nonet. A common type of word oriented data processing system has a word addressable memory with a word length of 36 bits divisible into 4 bytes.To increase the ability of such a word oriented computer to compete with 8 bit byte oriented computers, it is desirable that such a word oriented computer be able to run application programs written to run on a 8 bit byte characters addressable memory computer. Such a word oriented computer should be able to handle binary numbers of one to four characters either octets or nonets.

An advantage derived by a computer having this capability is that it saves users who are replacing a byte oriented computer with such a word oriented computer from having to rewrite their application programs. Such a conversion can be expensive and time consuming. However, to provide a word oriented computer with the capability of handling binary numbers having characters of either 8 or 9 9 bits per characters requires that the computer have the ability to store a binary number in a word organized memory location with the most significant character of the binary number, the one that contains the most significant bit of the binary number, in any of the four byte positions of a given word location in memory with the remaining characters of the binary number being stored in adjacent byte positions in decreasing order of significance.

Where 8 bit characters are stored in a 9 bit byte position, the most significant bit position of each byte will have a fill bit, normally a zero, stored in it. Depending upon the number of characters in a binary number and the byte location in which the most significant character is stored the less significant characters of the binary number may be stored in a contiguous word location in memory, or across a word boundary.

Given a binary number of from one to four characters with each characters of a given number having either 8 or 9 bits per character and with the characters being stored in a word addressable memory with the most significant character in any one of the byte positions of the given memory location, the problem is how to efficiently move the binary number between its addressable memory location or locations and an addressable register in the central processor of the system with the binary number positioned in the register so that it is ready to be processed, or operated on; i.e. added, subtracted, multiplied, divided, etc., with the bits of the number right justified with the least significant bit of the number in the least significant bit position of the register and the more significant bits of the binary number stored in ascending order of significance from right to left.In addition, with respect to some binary numbers it is also necessary to fill the higher order bit positions of the register not having stored into them a bit the binary number either a fill bit or the sign bit of the number, where ths sign bit is the bit in the most significant bit position of the binary number.

Heretofore, the manner in which this particular function has been performed has been by a software program. Such a program requires a significant number of instructions, each of which will require several clock periods to perform so that a significant amount of time is required to fetch from memory the binary number and position it in a a designated register ready for subsequent processing. The penalty in performance, measured in terms of throughput of a data processing system which must make such transformations, obviously adversely affects the ability of such a data processing system to compete effectively particularly in pertorming such programs compared to a data processing system organized to directly address the characters of the binary number.

According to the present invention there is provided a word-organized data processing system wherein each word is subdivided into a plurality of bytes, including means for converting a pure binary number between a first form in which the characters of the number are right-justified and contiguous within a single word and second form in which surcessive characters of the number occupy succe sive bytes, not necessarily within a single word, comprising: shifting means, controlled by the number of characters in the number and the byte address in memory of the first character in the number, for passing information with a shift of an integral number of bytes between 1 or 2 adjacent word locations in memory in which the number is stored and an intermediate register in which the number is stored in a third form in which the characters occupy successive bytes from the left end; and format switching means, controlled by the number of characters in the number and the length of the characters, for passing the number between the intermdiate register and a final register in which it is in the first form.

The system is viewed in such a manner that the number, in the first form, is written in the normal manner with the lowest order or units bit in the right-most position, and with the lowest order character in the right-most position when in the second form. Although a consistent and exact distinction between the terms byte and character is difficult to establish and maintain, the term byte will generally be used for a machine-determined division of a machine word, and the term character for a subdivision of the number being converted.

The length of a byte is fixed; the length of a character is not fixed (though all characters in a single number are of course the same length).

In the system to be described in detail, a machine word is 36 bits, divided into four 9bit bytes; a character mya be either 8 or 9 bits long.

A central processing unit embodying the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a portion of the central processing unit; Figure 2 is the format of an instruction; Figures 3A and 3B together are a more detailed block diagram of a part of the unit; and Figures 4, 5 and 6 illustrate various changes which may occur in the format of a number as it is moved through the unit.

Fig. 1 is a block diagram of those parts of the central processing unit (CPU) which are relevant to the execution of the Move To Register (MTR) and Move To Memory (MTM) instructions. The first step of either of these instructions is for the control logic means 11 to issue a read command to the memory locations where the instruction is stored. The address is produced by a conventional address preparation circuit 19. In response to the read instruction being issed, the MTR or MRM instruction is transmitted from memory over the memory service bus ZRMS and is stored in a two word register comprising an instruction buffer RIB 14 for storing an instruction word and descriptor register RDES 16 for storing a second word of the instruction which is also sometimes referred to as a descriptor.

Each of registers 14 and 16 is capable of storing a 36 bit machine word.

The format of an instruction 17 and a descriptor 18 are illustrated in Fig. 2. The address field Y, bit positions 0-17, of descriptor 18 stored in register 16 is the address in memory of the word in which the most significant character of the binary number to be moved to or from a designated addressable register is stored. Field C, bit positions 1 8-20, of descriptor 18 identifies or designates the byte position, of byte, of the word stored at memory location Y in which the most significant character of the binary number is stored. In these instructions field C has four possible values since a 36 bit word is divisible, or can contain, four bytes. The number of characters making up the number is designated by field L, bit positions 32-35 of descriptor 18. In these instructions the maximum value of L is limited to 4.The operational code field, bit positions 18-27, designates the instruction to be performed. Field B, bit position 22, identifies the type of character in the memory, i.e. whether the characters in the memory are 8 or 9 bit characters. The sign extended field SE, bit position 21, identifies for the MTR instruction whether the binary number being moved from the memory to an addressable register is to have its sign bit extended to fill any empty bit positions at the left-hand end of the number. The register field RECR, bit positions 14 to 17, identifies which of 10 addressable registers is to be the source of destination of the number being moved.

The instruction register RIB 14 feeds an instruction decode unit 26, which detects when the instruction is an MTR or MRM one.

For each of these two instructions, there is a chain of flip4lops, MTRA to MTRD and FIN and MTMA to MTMD and FIN respectively, driven by clock signals from a CPU clock source 30. Each chain acts effectively as a shift register, with a 1 being shifted along it, and each flip-flop when set controlling a re spective stage of the carrying out of the respective operations. The two chains share a common final flip-flop FIN, and the MTM chain has the option of skipping flip-flop MTMD.

When field 18-27 of instruction 17 has the value which designates the instruction as be ing the MTR instruction, the address field Y of descriptor 18 is transferred to address prepa ration circuit means 19 of the controller 11 and a memory read instruction is transmitted to the memory of the system. In response to such a memory command the memory will apply to the memory service bus ZRMS the 36 bits of the word stored in memory at address, or location, Y as specified in descriptor 18. Referring now to Fig. 3A, this word is stored into the upper half RDI-U of the double word data in register RDI 20 by enabling switch position ZRMS-U 0-35 of a conventional multi-position, or condition switch 22. (The other positions of switch 22 are not illustrated since they are not used in implementing the MTR instruction.) This occurs with flip-flop MTRA set. Flip-flop MTRB is set next.When this occurs, control circuit 11 will have determined, from field C of descriptor 18, the byte position of the word stored in memory location Y containing the most significant character of the binary number, and the number of such characters comprising the number from field L of descriptor 18. From this information, control circuit 11 determines if the binary number is stored across a word boundary, i.e. whether one or more characters of the number are stored into the next memory location having the adjcant address of (Y + 1). If the binary number is stored across a word boundary, then the address preparation circuit means 19 of controller 11 will issue another read instruction with the address of Y incremented by 1, to (Y + 1).This word will be stored in the lower half RDI-L of RDI register 20, bit positions 36-71, by the lower half position ZRMS-L, bit position 36-71 of the ZRMS switch 22 being enabled.

On the next clock signal, flip-flop MTRC will be set. This causes the words stored in data in register 20 to be applied through position ZRDI of switch 36 to conventional shifter 38.

(A second position of switch 36 is shown in phantom because it is not relevant at the moment.) The word in the upper half RDI-U of register 20, bit positions 0-35, will be applied to shifter 38 through the B operand bsu Z~SB and the word, if any, stored in the lower half RDI-L of register 20, bit positions 36-71 will be applied over A operand bus Z~SA to shifter 38.Knowing from field C of descriptor 18 the byte positions of the word stored in the upper half RDI-U of register 20 in which the most significant character of the binary number is stored, and knowing that the number of bits per byte position is 9, control circuit 11 determines the magnitude of the shift that must be applied to the words stored in data in register RDI 20 to left justify the bytes containing the characters of the binary number so that the most significant character occupies the highest order byte position on shifter output bus ZSHF. Bus ZSHF is a one word bus, i.e. it has 36 characters, for carrying or transmitting 36 bits of information in parallel. The amount of shift applied to the signals applied to shift 38 is equal to 9(C-1).

For example, if the most significant character of the binary number is stored in the second byte position, then to left justify the bytes in which the characters of the binary number are present, it is necessary to shift the contents of register RDI 20 by 9 bit positions to the left.

Signals representing the necessary amount, or magnitude, of the shift are applied to shifter 38 from the control circuit 11. The words applied to shifter over Z~SB and Z~SA buses are shifted to the left so that the byte containing the most significant character of the binary number is left justified.A maximum number of four bytes containing characters of the number are arranged in decreasing order of significance from left to right will be present on, or applied to, the shift output bus ZSHF of 36 bits and through switch position ZSHF of gated select switch 44 will be applied to intermediate register RIM 46 which is enabled to store them by control signals from controller 11. (Switch 44 has a second position, shown in phantom which is not relevant at the moment.) Fig. 4 is an example of the transformations that can occur to words stored in two memory locations Y and Y + 1 in implementing the MTR instruction until the binary number which was stored in these two locations in memory is stored in an addressable register RA or RO or RX 0-7.For the purposes of this explanation, it is assumed that the binary number has three characters CO, C1 and C2 and that its most significant character CO is stored in byte location B2, bit positions 18-26. Since the number of characters C comprising the number is 3, in the example, the binary number extends across a word boundary between words which has been stored at locations Y and Y + 1. The 36 bit word from memory location Y will be stored in the upper half RDI-U of data in register RDI 20, bit positions 0-35, and the word from memory location Y + 1 will be stored in the lower half RDI-L of register RDI 20, bit positions 36-71, as seen in Fig. 4A.The characters of the binary numbers in this example have 8 bits, or are octets, and are designated by C. (A 9 bit character will be designated by C'.) The first step in implementing the MTR instruction left justifies the bytes containing characters of the binary number so that the bytes are left justified when stored into intermediate register RIM 46, Fig. 4B.

Field C of the descriptor 18 controls the number of bit positions that the contents of data in register RDI 20 must be shifted to the left. The result of the left shit. is that byte B2, containing the most significant character CO, will be left justified when stored in register RIM 46 as seen in Fig. 4B. Up to this point in implementing the instruction, no distinction is made whether the characters of the binary number are octets or nonets. Flip-flop MTRD is next set. On this, the word stored in intermediate register RIM 46 will be applied to the im rmediate register bus ZRIM which is con nected to format switch 52.Format switch 52 is a one of ten gated select switch which will change the format of the signals of the machine word applied to it from bus ZRIM in such a manner as to right justify the binary number contained therein on shift output bus ZFS.

The formats designated RIM-O, Fig. 5A, and RIM-1, Fig. 5F, are the two formats of a binary number on bus ZRIM 50. In Figs. 5 B-E and 5 G-L the formats produced by each of the ten positions FS 0-9 are illustrated.

The position of switch 52 enabled is determined from the information in the instruction words stored in registers 14 and 16 of controller 11. The type of character, i.e. whether it is an 8 bit or a 9 bit character, is identified by field B, the number of characters comprising the binary number is specified by field L, and the sign extended field SE determines whether the sign bit, the most significant bit of the binary number, is to be used to fill any higher order bit positions on bus ZFS not needed or used to transmit the number. This information is used by control circuit 11 to select which switch position FS 0-9 is to be enabled. In addition the addressable register to which the binary number, the signals on format switch output bus 54, is to be stored is specified in field RECR.Eight of the ten directly addressable register are index registers RX 0-7 which are half word registers; i.e capable of storing only 18 bits or a half word.

The other addressable registers are the A register RA 60 and the Q register RQ 62, each a full word register. A further restriction is that if the binary number is to be stored in a register of register bank 56, then the binary number can have at most two characters C and these two characters must be placed on the conductors of the upper half ZFS-U of bus ZFS, bit positions 0-17. If the one or two characters of the binary number are to be stored in an index register of bank 58, the characters have to be placed on the lower half ZFS-L of bus ZFS, bit positions 18-35. Thus, the register into which the binary number is to be placed, the number of characters in the number, and whether the characters are 8 or 9 bit characters determines which switch position of format switch 52 is to be enabled.

As the binary numbers are applied to the format switch output bus ZFS by the format switch 52, they are right justified to a word or half word boundary with the bits of the binary number in order and with the least significant bit in the least significant bit position whether the binary number is made up of 1, 2, 3 or 4 characters. If the sign extension field SE is a 1, then the sign extension circuit 64 will provide a 1 in the higher bit positions of bus ZFS 54, if the bit positions are not used to store bits of the binary number and if the most significant bit of the binary number is a 1. Circuit 64 will apply a O to these positions if the most significant bit of the binary number is a 0.If the sign extension bit is a 0 then the sign extension circuit 64 will provide a O or a fill bit in any higher order bit position of bus ZFS not needed for applying the bits of a binary number to the register. The signals on the format switch output bus ZFS are applied through switch 66 and bus ZB to registers RX 0-7, RA, and RQ. The register designated by field RECR of instruction 17 will be enabled by control signals from controller 11 to store the bits on the conductors of bus ZB. The binary number stored in registers RX 0-7, RA and RQ will be in the proper format so that it can be applied to the binary arithmetic unit of CPU 10, for example. When the next clock pulse is produced by clock 30, the finish of instruction flip-flop FIN will be set, which signals the completion of the instruction.Control logic circuit means 11 is then ready to implement the next instruction to be stored in instruction registers 14 and 16.

Knowing that the characters C of the binary number are octets, which is designated by the field B of descriptor 18, the number of characters designated by field L and the register into which the binary number is to be stored which is designated by field RECR, controller 11 selects that position of the 1 of 10 gated select format switch 52 which when enabled or selected will cause the characters of the binary number to be right justified on format switch output bus ZFS. Referring to Fig. 5, it is seen that this would be switch position FS-5 in the example illustrated in Fig. 4.

With switch position FS-5 being enabled by control signals from controller 11, the fill bits in bit position 0, 9 and 18 of the word stored in register RIM will be eliminated, i.e. not connected to output bus ZFS and the character C2 will be positioned so that when stored in register RA for example the least significant bit of character C2, bit 26, will be right justified, i.e. will be in bit position 35 with the remaining bits of the characters CO, C1, C2 being arranged in order of increasing significance from right to left as illustrated in Fig.

5H. If the sign extension bit field SE, bit position 21 of the descriptor 18, is a 1 then the balance of the more significant bit positions XS on bus ZFS, bit positions 0 to 11 in this example, will have the same binary value as that of the most significant bit of the binary number; namely the bit in bit position 1 2. If the sign extension field is a 0 then the sign extension bits 0 to 11 will have stored into them fill bits, 0's.

The MTR instruction identifies the register into which the right justified binary signal is to be stored and controller 11 provides the necessary signals to enabled the addressed register to store the signals applied to it over bus ZB. Registers RX 0, 1, 4 and 5 are connected to bus ZB-U so that the conductors of the more significant bits on bus ZB, bit positions 0-18, can be stored into them. The lower half, ZB-L, the less significant bit positions of bus ZB, i.e. bit positions 18 to 35, are storable into registers RX 2, 3, 6 or 7. In the example illustrated in Fig. 4, the binary number has three characters, CO, C1, C2 so that the binary number can only be stored into either of the full word registers RA and RQ.When a binary number is stored into the addressed register, the binary number is right justified to either a full word or half word boundary with either a fill bit or the sign bit being stored into unused higher order bit positions of the addressed register depending upon the value of the sign extension bit in descriptor 18. The binary number when stored in the register designated by the instruction word 17 is ready to be operated on by subsequent instructions.

The need for the sign extension bit occurs because the binary arithmetic units of processor 10 are designed to handle 26 bits in parallel. To avoid changing the internal structure of the processor, particularly such units as the binary arithmetic unit when required to operate on binary numbers of less than 36 bits, and particularly if the binary numbers are in the signed two complement notation, the use of sign extension bits is necessary to avoid the introduction of possible computational errors.

The format of a 36 bit word identified as RIM-0 which is typicaly of the format of a word stored in the intermediate register RIM 46 when the binary number is composed of 9 bit characters is illustrated in Fig. 5A. When stored into register RIM 46 the binary number is left justified so that the characters C'O-C'3 will be position as illustrated in Fig. 5A. It should be noted that there are no fill bits present when the characters of the binary number are nonets. When the format switch 52 is placed in its 0 condition, FS-0, the contents of the intermediate register 46 are applied to the format switch output bus ZFS without change.If the number of characters C' binary number is 3, then the control signals applied to switch 54 by control circuit 11 will enable or select position FS 1 with the result that only the three most singificant characters C'0, C'1 and C'2 will be applied to bus CFS 54 and be stored into a designated register RA or RQ. If the sign extension bit is a 1, then bit positions 0 to 8 will be the same as the binary signals stored in bit position 9.

Similarly, if the binary numbers stored in register RIM has only two characters, C'O and C'1, or only one character C'O, then format switch 52 will be put in its FS2 or FS3 condition, which causes the two characters C'0 and C'1 or the character C'0 to be right justified. If the sign extension bit is a 1 then bit position 0 to 17 or 0 to 26 will have the same value as bit position 18 or 27.

If the binary number consists of not more than two characters and if the characters are to be stored in a register of index register bank 56 RX 0, 1, 4 and 5, then switch position FS-0 will be enabled if there are two characters in the number. This causes the first two characters C'0 and C'1 to be in the upper half of the word, bit positions 0-18. If only one character is to be stored in one of these four registers, switch position FS-1 will be enabled. If the characters are to be stored in the lower half bank of index registers 58, RX 2, 3, 6 and 7, then the switch position to be enabled or selected wil be FS-2 if the binary number has two characters to the number, and RS-3 if the binary number has but one.

The format designated RIM-1 in Fig. 5F illustrates the arrangement of characters C which are octets as they exist in intermediate register RIM 46 or as they are applied to bus ZRIM after being left justified so that the most significant character CO will be in the most significant byte position B0. Since the characters are octets, a fill bit designated by a diagonal line slanting from left to right will be stored in the most significant bit position of each byte storing a character, i.e. bit positions 0, 9, 18 and 27 of Fig. 5F.If the binary number consists of four octets CO-C3, then format switch 52 will be put into its position, or condition, designated as FS-4 which will cause the four octets C0-3 to be right justified with the least significant bit, bit 35 of the number, in bit position 35 and the most significant bit of the number being in bit position 4 when the binary number is placed in on bus ZFS 54. Fill bits present in register RIM 48 will be eliminated so that the bits of the binary number are arranged in order of increasing significance from right to left as illustrated in Fig. 5G. If the sign extension bit is present, then bit positions 0-3 will have the same value as bit position 4. If the binary number consists of three, two or one octets, then switch 52 will be placed in its condition FS-5, FS-6 or FS-7, which will cause the binary number to be right justified as seen in Figs. 5H, 51 and 5J.If the sign extension bit is a 1, then bit positions 0 to 11,0 to 19 or 0 to 27 will have the same value as the bit stored in bit location 12, 20 or 28 respectively.

As pointed out above, if one wants to store a half word into the bank of registers 56, the bits of the half word must be placed on the conductors, bits 0 to 17, of bus ZFS and switch position FS-8 will be enabled which puts the two characters CO, C1 in the upper half of a word ready for storage in whichever one of registers RX 0, 1, 6 or 7 is enabled pursuant to the designation of the addressable register in field RECR of instruction 17. If the sign extension bit is a 1 then when switch 52 is in condition FS-8, bit positions 0 and 1 will have the same value as the bit stored in bit position 2. If switch 52 is in condition FS-9, only a single octet CO will be present and right justified against the half word boundary 71 between bit positions 17 and 18.

If the sign extension bit is a 1 the bit stored in bit locations 0 to 9 will be the same as that stored in bit position 10, as illustrated in Fig.

5L.

The format switch 52 comprises a set of 10 banks of AND gates, each bank including 36 individual gates, and a single bank of 36 OR gates, each OR gate being fed by 10 AND gates from the corresponding positions in the 10 banks of AND gates. Each AND gate has 2 inputs, an enable input and a data input. The data inputs are selected from the 36 bits of bus ZRIM and O's according to the scheme explained with reference to Fig. 5. The controller 11 includes a decoding logic circuit, not shown, which is fed by the B, L, SE and RECR fields of the instruction and determines from these fields, by conventional logic circuitry, which of the positions FS-0 to FS-9 of switch 52 is to be selected and supplies an enable signal to the appropriate one of the 10 banks of AND gates.

Consider now the move to memory MTM instruction. This will be implemented, or executed, after a pure binary number has been stored into one of the addressable registers which includes the two banks 56 and 58 of half word registers and the two full word registers RA 60 and RO 62. The binary number stored in one of the addressable registers will normally have been produced by an arithmetic unit of CPU 10 which is not illustrated, after operating on, or manipulating, binary numbers to produce a result, a binary number, which is stored in one of the addressable registers prior to its being written into, or stored in, memory.

The characters of a binary number stored in any one of the addressable registers will be right justified against a half word or full word boundary, i.e. with the least significant bit of the binary number occupying the least significant bit position of the register. Registers RA 60 and RQ 62 are full word registers, that is they have 36 bit positions, so that a binary number having up to four characters of either 8 or 9 bits can be stored in either of registers RA or RQ with the characters of the binary number being right justified against, in this case, a full word boundary which is between bit 35 and 36 of registers 60 and 62.To move a binary number from one of the addressable registers, the move to memory instruction, the format of which is illustrated in Fig. 2, will have been read out of memory and stored in the double word instruction register 14 and 16 of control logic circuit or controller 11.

After receipt of the MTM instruction, which includes an insruction word 17 and a descriptor 18, the control circuit 11 will produce the necessary control signals to implement the instruction. The addressable register identified in field RECR will be enabled, as well as the appropriate positions of the selector switch 71 or 72 if one of the registers RX 0-7 is designated in field RECR, and the signals stored in that register will be applied to one of the input buses to the bank of selector switches 73 which selects the signals that will be applied to bus ZGR and through it to format switch 74.Depending upon the character type of the binary number, i.e. whether they are octets or nonets and the addressable registers in which the binary is stored, one of the switch positions FSA-O to FSA-2 will be enabled, or selected by signals from controller 11 so that the characters of the binary number will be positioned or reformated, if necessary, so that in the word on format output bus ZFSA there is only one character per byte and so that bytes of the word containing characters of the binary number are right justified, i.e. the byte containing the least significant character will be right justified against a half word or full word boundary.

If the characters are nonets, then irrespective of the addressable register in which the binary number was stored, the initial position FSA-O will be enabled which will pass the signals on bus ZGR through format switch 74 unchanged to format switch output bus ZFSA.

If the characters of the binary numbers are octets, and if the designated addressable register is a full word register RA or RQ, then position FSA-1 will be enabled which unpacks the character of the binary number so that only one octet is present in a byte position on format switch outputs bus ZFSA with the bytes containing characters of the binary number being right justified against a full word boundary. The occet in each byte location is also right justified within its byte and the most significant bit position of each byte containing an octet will have a fill bit, normally a 0, placed in it.

If the characters of the binary numbers are octets, and if the designated addressable register in which the binary number is stored is one of the half word register RX 0-7, position FSA-2 of format switch 74 will be enabled, which unpacks the octets of the binary number applied to format switch 74 so that only one octet is positioned or present in a byte position on format switch output bus ZFSA with the bytes containing characters of the binary number being right justified against the half word boundary. The octets in each byte location on bus ZFSA are also right justified within its byte, and the most significant bit position of each byte will have a fill bit stored in it.

The bits of the format switch output word on output bus ZFSA will be applied to and stored into intermediate register RIM 46. The format switch output word stored into inter mediate register 46 will contain from 1 to 4 characters, with one character per byte and with the byte containing the least significant character of the binary number being right justified against a full word or half word boundary.

This intermediate register 46 is shown in phantom here because it is the register 46 also shown and discussed in Fig. 3A. The phantom position of switch 74 is the position ZRDl of switch 36. Likewise, the shifter 38 is shown in phantom as it has already been shown in Fig. 3A, and the phantom position of the switch 71 is the position ZRDl of the switch 36 of Fig. 3A.

Controller 11 will then cause the word stored in intermediate register 46 to be applied to shifter 38 over the two busses ZS-A and bus ZS-B by enabling switch ZRIM-A 48 and switch ZRIM-B 50. Controller 11 will, since the number of characters in the binary number is specified in field L, descriptor 12, the register from which the binary number was obtained is specified in field RECR instruction 17, and the byte position in the first word to be stored into memory into which the byte containing the most significant character of the binary number is to be positioned or stored is specified in field C of descriptor 18, apply control signals to shifter 38 to caust it to rotate the words applied to it over buses ZS-A and ZS-B to place the byte containing the most significant character of the binary number in the desired byte position in the word on the shifter output bus ZSHF.Switch position ZSHF of selector switch 96 in response to control signals from controller 11 selects the bytes on bus ZSHF to be applied to and stored in data out register RD~ 12.

Only those byte positions of switch position 94 will be enabled which permit the byte containing the most significant character of the binary number and any other bytes containing characters of the binary number in lower order byte positions within the word boundaries of bus ZM to be applied to and stored into data out register 12. Byte positions of greater significance than the one into which the byte containing the most significant character of the binary number is stored will be filled with fill bits, or 0's.

If the bytes containing the less significant characters of the binary number cross or overflow a word boundary on bus ZM, then in order for the remaining bytes containing such less significant characters of the binary number to be stored in memory, the contents of the intermediate register 46 will be applied to the shift 38 a second time and shifted as related above so that the byte containing the most significant character will be in the byte position designated by field C of descriptor 19. In this instance, the control signals applied to position ZSHF of switch 96 will enable the byte positions of position ZSHF so that such overflow bytes, left justified against the left word boundary of bus ZM and placed in order of decreasing significance, will be applied by bus ZM to data out register 12.As a a result, a second word containing the overflow characters is stored in register 12 ready for storage in an adjacent or contiguous memory location; namely the memory location having an address of Y + 1, for example.

Obviously the first data out word stored into register 12 which contains the most significant character of the binary number will be the first word read out of register RD~ for storage in memory as the result of a memory write instruction having been issued to memory through register RD~ by control circuit 11. Such a write instruction causes the next word stored in register 12 to be stored in memory at memory location Y. After the first data word containing a character of the binary number is transferred to memory from register 12 and if an overflow condition exists, then the second data word stored in register 12 containing the lower order, or less significant, characters of the binary number will be issued to memory for storage at location Y + 1, in response to the issuance of second write instruction.In this manner the bytes of the words stored in memory containing characters of the binary number will be arranged in order of decreasng significance from left to right with respect to the byte containing the most significant character of the number.

The carrying out of the MTM instruction is controlled by the controller 11 by means of the flip-flop chain MTMA to MTMD and FIN.

When an MTM instruction is detected, flipflop MTMA will be set. On the next clock pulse, flip-flop MTMB will be set, and this will control the selection of the binary number from the appropriate one of the addressable registers and its passage through the format switch 74 to the intermediate register 46.

Next, flip-flop MTMB is set. This controls the passage of the word in the intermediate register 46 through the shift 38 to the data out register 12. The shifter is also supplied with control signals controlling the amount of shift or rotation necessary to place the byte containing the most significant character of the binary number in the byte position in the word on shifter output bus 52 designated by field C. The shifter rotates the signals applied to it to the left the designated amount, 0, 1, 2 2 or 3 byte positions, as will be explained below.Switch position ZSH# of selector switch 96 will be enabled so that only those byte positions of the first shifter output word on bus ZSHF are applied to bus ZM which includes the most significant character of the binary number and any other byte positions containing less significant characters of the binary number in decreasing order of significance within the word boundaries of the shifter output word. The first data out word on bus ZM is stored in data out register RD# 12. When the first data out word is stored in register 12, it is ready to be stored, or written, into memory.The address preparation circuit 19 will have issued a write instruction to the memory preparing the memory system to store the next word on data out bus ZRD~ (which is the first word containing a character of the binary number at the memory location specified by field Y of descriptor 18.

If the byte position into which the byte containing the most significant of the binary number is placed plus the number of characters in the binary number exceeds 4, then an overflow condition will exist. An overflow condition means that one or more bytes containing less significant characters of the binary number will have to be placed in a second data out word to be written into memory at a contiguous memory location. If there is an overflow condition, then overflow flip-flop FF~VR 99 will be set. This causes flip-flop MTMD to be set on the next clock pulse. The contents of register RIM 46 will again be applied to shifter 38 and will be shifted, or rotated, as when flip-flop MTMC was set.The output word on shifter output bus ZSHF will also be the same, but in this case position ZMl of selector switch 96 will be enabled so that the bytes containing the less significant characters of the binary number which overflowed a word boundary, or are positioned in a higher order byte position than the byte position containing the most significant character, are present in the output word applied to bus ZM for storage in R~ 12. As a result only bytes containing overflow characters of the binary number will be positioned in order of decreasing significance from left to right, with the byte containing the most significant overflow character being left justified against a word boundary of the second data out word.When MTMD is set, the memory instruction preparation circuit 19 will issue a second write to memory instruction having the address of Y + 1 and will cause the second data out word stored in register RD~ to be read into memory for storage at location (Y + 1). The next clock pulse sets the end of instruction flip-flop FIN, which signals that the instruction has been completed.

If there is no overflow condition, then flipflop MTMD will not be set, but flip-flop FIN will be set on the next clock pulse after flipflop MTMC was set; this ends the execution of the MTM instruction with only a single data out word being written into memory at location Y.

The operation of the format switch 74 will be explained by reference to Fig. 5. Position FSA-O effects the reverse of the format change of position FS-O of switch 52, converting the format of Figs. 5B to that of Fig.

5A (actually, this is no change). Position FSA-O is used if the characters are nonets. Position FSA-1 effects the reverse of the format change of position FS-4 of switch 52, converting the format of Fig. 5C to that of Fig. 5F. Position FSA-1 is used if the characters are octets and the word is stored in addressable register RA or RQ. Position FSA-2 effects a slight modification of the reverse of the format change of position FS-8 of switch 52, converting from the format of Fig. 5K to the format of Fig. 5F but with the right-hand two bytes B2 and B3, bit positions 18 to 25, set to O's (filler bits). Position FSA-2 is used if the addressable register is one of the index registers RXO to RX7 and the characters are octets.

Fig. 6 illustrates the changes which may occur to a binary number stored in the addressable register RA, as illustrated in Fig. 6A, and consisting of four nonets C'O-C'3. Format switch position FSA-O will be enabled, which applies the signals on bus ZGR to bus ZFS unchanged for storage in the intermediate register 46 as illustrated in Fig. 6B. The format switch output word stored in intermediate register 46 will then be applied to shifter 38 over buses ZS-A and ZS-B so that the words applied to shifter 38 are as illustrated in Fig. 6C. In this example, the most significant character C'O is to be positioned in the byte position B2 so that the words applied to shifter 38 are shifted or rotated to the left two byte positions, or eighteen bits.Knowing that the byte containing the most significant nonet C'O is to be placed in byte position B2 and that the binary number has four nonets, in this example, the overflow condition exists since 2 + 4 is greater than 4 so that overflow flip-flop 99 will be set. When the first data out word Dldl is stored into data out register 12, the higher order byte positions BO and B1 of position ZSHF will not be enabled so that only the characters C'O and C'1 will be present in byte positions B2 and B3 in the word on bus ZM, as illustrated in Fig. 6E. On the next clock signal, signals from controller 11 are applied to shifter 38 as well as the contents of intermediate register RIM so that the words applied will be shifted to byte positions illustrated in Fig. 6D, the same as before. Since this is an overflow condition, byte positions B2 and B3 of switch ZSHF will not be enabled but byte positions BO and B1 will be so that the characters C'2 and Cl3 will be placed in positions BO and B1 of the second data out word D~-2, which will have the format illustrated in Fig. 6F.

The structure of the format switch 74 is similar to that of switch 52.

Claims

1. A word-organized data processing system wherein each word is subdivided into a plurality of bytes, including means for converting a pure binary number between a first form in which the characters of the numbers are rightjustified and contiguous within a single word and a second form in which successive characters of the number occupy successive bytes, not necessarily within a sin gle word, comprising: shifting means, controlled by the number of characters in the number and the byte address in memory of the first character in the number, for passing information with a shift of an integral number of bytes between 1 or 2 adjacent word locations in memory in which the number is stored and an intermediate register in which the number is stored in a third form in which the characters occupy successive bytes from the left end; and format switching means, controlled by the number of characters in the number and the length of the characters, for passing the number between the intermediate register and a final register in which it is in the first form.

2. A system according to Claim 1 including a plurality of addressable registers any one of which may be selected as the final register.

3. A system according to either previous claim, wherein numbers may be converted from the second form to the first form.

4. A system according to Claim 3 including means for effecting sign extension on conversion of a number to the first form.

5. A system according to either of Claim 3 and 4 including a two-word data in register into which the word or words containing the number can be passed from the memory, and which feeds the shifting means.

6. A system according to any previous claim, wherein numbers may be converted from the first form to the second form.

7. A system according to Claim 6 including a one-word data out register fed by the shifting means and feeding the memory, and means for filling the data out register first with the left part of the number and second with the right part of the number if the number occupies two adjacent words in the second form.

8. A system according to any previous claim, wherein the number of bits in a byte is 9 and the number of bits in a character is either 8 or 9.

9. A system according to any previous claim, wherein the number can also be converted between the second form and a modification of the first form wherein the number is right justified to a half-word boundary within a single word.

10. A data processing system substantially as herein described and illustrated.