GB2026237A - Junction gate field effect transistors - Google Patents
Junction gate field effect transistors Download PDFInfo
- Publication number
- GB2026237A GB2026237A GB7925044A GB7925044A GB2026237A GB 2026237 A GB2026237 A GB 2026237A GB 7925044 A GB7925044 A GB 7925044A GB 7925044 A GB7925044 A GB 7925044A GB 2026237 A GB2026237 A GB 2026237A
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- GB
- United Kingdom
- Prior art keywords
- slots
- regions
- gate
- conductivity type
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 18
- 238000001465 metallisation Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 9
- 230000001419 dependent effect Effects 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 5
- 238000000992 sputter etching Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims 1
- 230000001681 protective effect Effects 0.000 claims 1
- 239000007788 liquid Substances 0.000 abstract description 2
- 108091006146 Channels Proteins 0.000 description 14
- 238000002955 isolation Methods 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
Abstract
A vertical channel junction gate field effect transistor includes gate regions 15 which are formed at the bottom of slots 6-8 formed in a major surface of a body of semiconductor material, which gate regions define channels of the transistor. Narrow source regions 11 are formed in the major surface of the body between the slots so that the current path is vertically downward from the source regions between the gate regions at the bottom of the slots to a drain region 13 disposed over the lower surface of the semiconductor body. The gate regions may be joined together by a region (9/10) of the same conductivity type extending from the major surface across one or both ends of the slots. Surface metallisation 16 at the bottom of the slots may be provided to improve the conductivity of the gate regions. The drain region may be of the same or of opposite conductivity type to the channel. The slots may be formed by orientation dependent etching using a liquid etchant or by directional etching using sputter or plasma techniques. <IMAGE>
Description
SPECIFICATION
Field effect transistors
This invention relates to field effect transistors. A limitation of field effect transistors was that they were incapable of handling a large amount of power without extensive interdigitated gate structures designed to increase the cross-sectional area of the channel without increasing its length. Recently proposals have been made to overcome this problem by arranging the channels of field effect transistors vertically through the semiconductor wafer on which the transistor is formed, but the high frequency figure of merit of junction gate field effect transistors made in this way have not been particularly high because of a large amount of parasitic capacitance inherent in the structures.For high frequency applications the figure of merit of a junction field effect transistor is given by Yfs/C, where Yfs is the transconductance of the transistor and C is the gate input capacitance.
It is an object of the present invention to provide a structure and technique for manufacturing an improved vertical channel junction gate field effect transistor.
According to the present invention there is provided a junction gate field effect transistor including a body of semiconductor material of a first conductivity type, the body having first and second major surfaces bearing source and drain connections respectively, one or more narrow source regions of the first conductivity type being defined in the first major surface and connected to the source connection wherein there are disposed within the body one or more gate regions of opposite conductivity type to the first conductivity type, the gate regions su bstantially surrounding parts of the body beneath the source regions which form channels of the transistor, and there are provided one or more slots along the sides of the souce region or regions extending from the first major surface to at least part of the gate region or regions.
The transistor according to the invention can be constructed using silicon as the semiconductor material. Transistors according to the invention can have advantages over both gallium arsenide field effect transistors and silicon MOSFETs atfrequencies below 10 MHz because of the much lower excess noise which they produce. It has been calculated that transistors according to the invention will be capable of operation up to 5 GHz and because of their inherently high packing density will enable power field effect transistors to be manufactured with a power capability of many watts using less area of silicon wafer than alternative constructions using bipolar configurations. In addition to high frequency amplification, a transistor according to the invention can usefully be used for the amplification of a small signal from a high impedance detector.
It should be noted that the structure is compatible with standard integrated circuit processing with one extra step, the etching of the slots, added.
Gate contacts in the form of a metal film may be applied to the gate region or regions at the bottom of the slot or slots, thereby reducing the gate resistance and enhancing the high frequency gain of the transistor. The slots may be parallel coextensive straight slots formed by orientation-dependent etching using a liquid etchant or by plasma or sputter etching. In one example of the invention the slots are 2lim deep and 3lim wide with a space of 4lim between adjacent slots. The slots need not be completed to form a complete narrow rectangle, but may be left open which would allow some leakage of current from source to drain which may be acceptable in certain applications.If it were required to complete the rectangles of gate region surrounding the channels then isolation diffusion from the first major surface may be provided using the same conductivity type inpurity as the gate region but extending from the surface to surround the source regions.
According to a second aspect of the invention there is provided a method for manufacturing a vertical channel junction gate field effect transistor in which slots substantially surrounding source regions of the transistor are cut through a major surface of a body of semiconductor material and gate regions of opposite conductivity type to that of the body of semiconductor material are formed at the bottom of the slots.
In order that the invention may be fully understood and readily carried into effect it will now be described with reference to the accompanying drawings, of which:
Figure 1 is a plan view of one example of the transistor according to the present invention:
Figure 2 is a longitudinal cross-section of the transistor of Figure 1 taken along the line A-A:
Figure 3 is a longitudinal cross-section of the transistor of Figure 1 taken along the line B-B:
Figure 4 is a transverse cross-section of the transistor of Figure 1 taken along the line C-C: and
Figure 5 shows a modification of the transistor of
Figure 1, the view shown corresponding to Figure 3.
It will be appreciated that the illustrations of the embodiments of the invention shown in the drawings are purely diagrammatic and do not imply any particular relationship between the dimensions.
Referring now to Figures 1 to 4, the transistor shown is formed on a body 1 of semiconductor material having a source metallisation 2 of U-shaped configuration on its upper surface. Gate metallisation 3 is formed also on the upper surface. The source metallisation 2 has connection regions 4 indicated by cross-hatching in Figure 1, and the gate metallisation 3 has a connection region 5 also indicated by cross-hatching. Three longitudinal slots 6, 7 and 8 are formed on the outside of and between the legs of the source metallisation 2. Isolation regions 9 and 10 of p±type conductivity are formed extending from the upper surface of the body 1 and across the ends of all three slots 6, 7 and 8.The body 1 itself has an upper surface layer 11 of n+conductivity type, a region 12 of n-type conductivity in which the channels of the transistor are formed, and a lower region 13 of n±conductivity type to which a source connection, not shown in the drawings, is applied. On the upper surface of the body 1 there is formed a film 14 of silicon oxide which serves to insulate the source and gate metallisations 2 and 3 from the upper surface except at the connection regions 4 and 5. As shown in Figures 3 and 4, p±conductivitytype gate regions are formed along the bottom of each of the three slots 6, 7 and 8, which regions extend from the isolation region 9 to the isolation region 10, so that the channels which extend from the source metallisation 4 downwardly to the drain region 13 are surrounded by the type conductivity gate regions.In order to improve the conductivity of the gate regions, metallisations 16 are formed at the bottom of the slots 6, 7 and 8, although the actual connection of the regions 1 5 to the gate metallisation 3 is through the isolation region 10. In orderto passivatethe p-n junctions between the gate and source regions, a film of silicon oxide is grown on the vertical walls of the slots, as indicated at 17 and 18 in Figure 3.
In the operation of the transistor shown in Figures 1 to 4, current flows vertically from the source contact 2 formed on the upper surface of the body 1 through to the drain region 13 at the bottom; the current flow is controlled by carrier depletion from the gate p+ diffusion which is effective at the bottom of the vertical slots. As shown, three gate slots are joined together at the end to form two narrow rectangular channels extending vertically through the body of the transistor. If desired and the application of the transistor is such that some leakage current is acceptable between source and drain when the device is biassed beyond pinch off, then the isolation regions 9 and 10 could be omitted.
If the alternative method of connection to the metallisation 16 described above with reference to
Figure 5 were provided, the isolation region 10 would be omitted.
In the manufacture of a transistor as shown in
Figures 1 to 4, an epitaxial layer of n-type conductvity material could be formed on a substrate on n+ conductivity type material forming the drain region 13. In the epitaxial region which is equivalent to the region 12 the isolation diffusions 9 and 10 of p+ conductivity type are then formed, followed by an overall n+ diffusion in the central region to define the source region or regions for the transistor, these regions being the region 11 shown in Figures 1 to 4.
If doped oxide sources are used, the isolation regions and overal n+ diffusion in the central area could be formed simultaneously. The slots 6, 7 and 8 are then etched through the n+ region into the epitaxial layer and in a typical device these will be 2m deep by 3um wide with 411m between the slots.
For devices for which a lower performance is acceptable, these dimensions could be increased to facilitate processing. With these dimensions it is assumed that the epitaxial layer has a resistivity of approximately 1.5 ohm-cm. Increasing the slot dimensions would require a higher resistivity epitaxial layer but the breakdown voltage of the device would be correspondingly increased. The slots 6, 7 and 8 may be produced by directional etching technique such as plasma or sputter etching. Alternatively, if the transitor is made on a (110) orientated slice, the slots may be wet etched using an orientation dependent etchant. A small degree of undercutting is required, but this will normally occur automatically.
Afterthe slots 6, 7 and 8 have been etched, they are thermally oxidised to a thickness of 0.1 micron and the p+ conductivity type gate regions are then produced at the bottom of the slots. Two processes are suggesed for achieving this. One method is to implant boron, for example, with sufficient energy to penetrate the thin oxide coating at the bottom of the slots but insufficient to penetrate a thicker oxide coating on the upper surface. As implantation takes place normal to the surface there will be no implantation through the sidewalls of the slots. A second method is to use sputter or plasma etching to remove the oxide coating from the bottom of the slots, the coating on the sidewalls remaining because of the directional nature of these etching methods. The upper surface oxide will only partially removed because of its greater thickness.A p-type doped oxide is then deposited pyrolytically on to the slice to a thickness of approximately 0.2 micron and the gate regions formed by the normal diffusion baking. By either technique the p-type dopant is introduced to form the region 15 with a depth of the order of 1 micron. This could be done in a phosphorus furnace ambient thereby introducing a phosphorus passivating glaze on to the slice at the same time.
The contacts are then etched through the dielectric for both source and gate connections and then an aluminium deposition is applied normal to the surface to form the source and gate connections 2 and 3 and the metallisation 16 at the bottom of the slots.
If a (110) orientated slice is etched with an orientation dependent wet etchant, the ends of the slots will be sloping and it would therefore be possible for the metallisation 16 to continue up the sloping end of the slots to join the gate contact 3 directly so that the connection through the isolation region 10 is not required.
Using plasma or sputter etching to form the slot will result in vertical end and sidewalls to the slots so that metallisation up the end walls of the slots could not be possible as just described. However, in order to reduce the resistivity of the gate it would be possible to etch away part of the body where the gate connection 3 is to be deposited so that there is no end wall to the slots adjacent to the gate metallisation 3. This alternative is shown in Figure 5 where the metallisation 16' at the bottom of the slot is in direct connection with the gate contact 3' which is formed on top of an oxide coating 14' which insulates it from the epitaxial layer 12.
Although the invention has been described with reference to a channel of n-type conductivity with p-type gate regions, it is to be understood that these conductivity types could be reversed although at the expense of the lower mobility of the carriers in a p-type channel field effect transistor.
In another alternative construction the drain region 13 is of opposite conductivity to the region 12 in which the channels are formed, so asto provide a forward biassed p-n junction at the drain connection.
The effect of this junction is to inject minority carriers into the channels and thereby lower the channel resistance and consequently the heat dissipated by the current through the channels.
Claims (18)
1. A junction gate field effect transistor including a body of semiconductor material of a first conductivity type the body having a first and second major surfaces bearing source and drain connections respectively, one or more narrow source regions of the first conductivity type being defined in the first major surface and connected to the source connection, wherein there are disposed within the body one or more gate regions of opposite conductivity type to the first conductivity type, the gate regions substantially surrounding parts of the body beneath the source regions which form channels of the transistor, and there are provided one or more slots along the sides of the source region or regions extending from the first major surface to at least part of the gate region or regions.
2. A transistor according to claim 1 wherein at the second major surface of the body there is provided a low resistivity drain region of said first conductivity type to which the drain connection is connected.
3. A transistor according to claim 1 wherein there is provided at the second major surface a low resistivity drain region of the opposite conductivity type to the channel region, to which drain region a drain connection is connected.
4. A transistor according to claim 1, 2 or 3 including a plurality of source regions beside and between which the slots are provided, and the gate regions include parts extending along the bottom of the slots.
5. A transistor according to claim 4wherein the gate regions include regions extending from the first major surface to join the regions formed at the bottom of the slots and extending across the ends of the slots, a gate contact being formed connected to one of the regions extending to the first major surface.
6. A transistor according to claim 4 wherein a recess is formed in the first major surface at one end of the slots of substantially the same depth as the slots which recess is connected to one end of each slot and there is provided at the other end of the slots a region of the opposite conductivity type extending from the first major surface to join the regions formed at the bottom of the slots.
7. A transistor according to any of claims 4, 5 and 6 6 wherein the slots are coextensive straight slots which are slightly longer than each source region.
8. A transistor according to any preceding claim wherein metallisation is deposited at the bottom of each slot and the walls of each slot are coated with a protective film of oxide.
9. A transistor according to any preceding claim including a semiconductor substrate forming a drain region wherein the body of semiconductor material is formed as an epitaxial layer on the substrate.
10. A field effect transistor substantially as described herein with reference to Figures 1 to 4 of the accompanying drawings or modified as described with reference to Figure 5.
11. A method of manufacturing a vertical channel junction gate field effect transistor in which slots substantially surrounding the source regions of the transistor are cut through a major surface of a body of semi-conductor material and gate regions of opposite conductivity type to that of the body of the semiconductor material are formed at the bottom of the slots.
12. A method according to claim 11 wherein the body is formed by epitaxial deposition on a substrate, the substrate forming a drain region of the transistor.
13. A method according to claim 12 wherein the substrate is of the same conductivity type as the epitaxial layer.
14. A method according to claim 12 wherein the substrate is of the opposite conductivity type to the epitaxial layer.
15.A method according to claims 11 to 14wherein the slots are parallel coextensive straight slots and are formed by orientation dependent etching or by a directional etching technique.
16. A method according to any of claims 11 to 15 wherein the gate regions are formed at the bottom of the slots by ion implantation after the slots have been formed.
17. A method according to any of claims 11 to 15 including coating the inside of the slots with oxide, etching away the oxide from the bottom of the slots by sputter or plasma etching, depositing a doped oxide in the slots and diffusing thè dopant from the oxide into the bottom of the slots to form the gate regions.
18. A method of manufacturing a vertical channel junction gate field effect transistor substantially as herein described with reference to the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB7925044A GB2026237A (en) | 1978-07-19 | 1979-07-18 | Junction gate field effect transistors |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB7830293 | 1978-07-19 | ||
| GB7925044A GB2026237A (en) | 1978-07-19 | 1979-07-18 | Junction gate field effect transistors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2026237A true GB2026237A (en) | 1980-01-30 |
Family
ID=26268264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB7925044A Withdrawn GB2026237A (en) | 1978-07-19 | 1979-07-18 | Junction gate field effect transistors |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2026237A (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2480501A1 (en) * | 1980-04-14 | 1981-10-16 | Thomson Csf | SURFACE-ACCESSIBLE DEEP GRID SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME |
| EP0038248A1 (en) * | 1980-04-14 | 1981-10-21 | Thomson-Csf | High power vertical channel junction gate field effect transistor and process for its manufacture |
| US4403396A (en) * | 1981-12-24 | 1983-09-13 | Gte Laboratories Incorporated | Semiconductor device design and process |
| US4543706A (en) * | 1984-02-24 | 1985-10-01 | Gte Laboratories Incorporated | Fabrication of junction field effect transistor with filled grooves |
| US4566172A (en) * | 1984-02-24 | 1986-01-28 | Gte Laboratories Incorporated | Method of fabricating a static induction type recessed junction field effect transistor |
| FR2572584A1 (en) * | 1984-10-29 | 1986-05-02 | Japan Res Dev Corp | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH A RECESSED GRID STRUCTURE, IN PARTICULAR A STATIC INDUCTION TRANSISTOR |
| US4620213A (en) * | 1980-04-14 | 1986-10-28 | Thomson-Csf | Deep-grid semiconductor device |
| US4713358A (en) * | 1986-05-02 | 1987-12-15 | Gte Laboratories Incorporated | Method of fabricating recessed gate static induction transistors |
| EP0317802A1 (en) * | 1987-11-25 | 1989-05-31 | BBC Brown Boveri AG | Turn-off power semiconductor device and method of making the same |
| US5143859A (en) * | 1989-01-18 | 1992-09-01 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a static induction type switching device |
| US5264381A (en) * | 1989-01-18 | 1993-11-23 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a static induction type switching device |
| US5861643A (en) * | 1996-08-26 | 1999-01-19 | Chartered Semiconductor Manufacturing, Ltd. | Self-aligned JFET |
| US6034332A (en) * | 1995-05-22 | 2000-03-07 | Fujitsu Limited | Power supply distribution structure for integrated circuit chip modules |
| US6921932B1 (en) * | 2002-05-20 | 2005-07-26 | Lovoltech, Inc. | JFET and MESFET structures for low voltage, high current and high frequency applications |
| US7262461B1 (en) | 2002-05-20 | 2007-08-28 | Qspeed Semiconductor Inc. | JFET and MESFET structures for low voltage, high current and high frequency applications |
-
1979
- 1979-07-18 GB GB7925044A patent/GB2026237A/en not_active Withdrawn
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2480501A1 (en) * | 1980-04-14 | 1981-10-16 | Thomson Csf | SURFACE-ACCESSIBLE DEEP GRID SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME |
| EP0038238A1 (en) * | 1980-04-14 | 1981-10-21 | Thomson-Csf | Method of manufacturing of a semiconductor device having an inset grid accessible from the surface |
| EP0038248A1 (en) * | 1980-04-14 | 1981-10-21 | Thomson-Csf | High power vertical channel junction gate field effect transistor and process for its manufacture |
| US4620213A (en) * | 1980-04-14 | 1986-10-28 | Thomson-Csf | Deep-grid semiconductor device |
| US4403396A (en) * | 1981-12-24 | 1983-09-13 | Gte Laboratories Incorporated | Semiconductor device design and process |
| US4543706A (en) * | 1984-02-24 | 1985-10-01 | Gte Laboratories Incorporated | Fabrication of junction field effect transistor with filled grooves |
| US4566172A (en) * | 1984-02-24 | 1986-01-28 | Gte Laboratories Incorporated | Method of fabricating a static induction type recessed junction field effect transistor |
| FR2572584A1 (en) * | 1984-10-29 | 1986-05-02 | Japan Res Dev Corp | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH A RECESSED GRID STRUCTURE, IN PARTICULAR A STATIC INDUCTION TRANSISTOR |
| US4713358A (en) * | 1986-05-02 | 1987-12-15 | Gte Laboratories Incorporated | Method of fabricating recessed gate static induction transistors |
| EP0317802A1 (en) * | 1987-11-25 | 1989-05-31 | BBC Brown Boveri AG | Turn-off power semiconductor device and method of making the same |
| US5143859A (en) * | 1989-01-18 | 1992-09-01 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a static induction type switching device |
| US5264381A (en) * | 1989-01-18 | 1993-11-23 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a static induction type switching device |
| US6034332A (en) * | 1995-05-22 | 2000-03-07 | Fujitsu Limited | Power supply distribution structure for integrated circuit chip modules |
| US5861643A (en) * | 1996-08-26 | 1999-01-19 | Chartered Semiconductor Manufacturing, Ltd. | Self-aligned JFET |
| US6921932B1 (en) * | 2002-05-20 | 2005-07-26 | Lovoltech, Inc. | JFET and MESFET structures for low voltage, high current and high frequency applications |
| US7262461B1 (en) | 2002-05-20 | 2007-08-28 | Qspeed Semiconductor Inc. | JFET and MESFET structures for low voltage, high current and high frequency applications |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |