GB1604761A - Control systems for a copier-duplicator - Google Patents

Description

(54) CONTROL SYSTEMS FOR A COPIER/DUPLICATOR (71) We, XEROX CORPORATION, of Xerox Square, Rochester, New York, United States of America, a corporation organised under the laws of the State of New York, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to copier/duplicators such as electrophotographic reproduction machines, and particularly to control systems for such machines.

Electrophotographic copying machines are well known within the prior art and typically employ mechanical or combinations of mechanical and electrical control logic for system control. Such control means is responsible for maintaining synchronism between the various operational stations of the reproduction machine and to ensure proper operation of the machine during the various operating modes.

These control devices have become increasingly complex as the level of sophistication has increased within the reproduction machine itself. With the advent of variable magnification machines and color copiers the logical control means necessary to achieve proper synchronization and operation has become increasingly complex and expensive. Consequently, attempts to obtain efficient operation of these machines has developed utilizing digital computing device controllers which are programmed to carry out a sequence of operational tasks. Some of these digital device controls are quite specialized and govern only particular localized tasks or operations of the machine such as disclosed in U.S. Patent 3,876,106. System operation as a whole has also been achieved in the prior art utilizing computers with relatively large CPU and memory storage units. Examples of these prior art devices are disclosed in U.S.

Patents 3,936,182, 3,914,047 and 3,940,210.

With the advent of larger and more complex photoreproduction machines the various tasks needed to be performed by the machine have become increasingly large.

Particularly, an operator may select from a variety of modes of operation, each one designating a particular sequence of operations which must be stored in the computer control means. In some cases the advantages of speed and efficiency of the computer control system has been outweighed by its prohibited cost and large physical dimensions required to store and execute programs defining the desired number and permutations of operational tasks. Still further cost and size restraints come into play when system flexibility is desired by way of expanding the computer control to various other controlled devices or operating stations as would be typical in the offering of a single model copier with various optional attachments. Thus, special purpose hardware may typically be employed as an alternative or addition to the utilization of the central digital computing controller.

Yet another disadvantage of the prior art in computer control devices lies in malfunctioning of the computers due to noise and radio frequency interference resulting primarily from the computer being exposed to the various electrical transients produced by operation of solenoids, motors, relays and the like. Consequently, there exists a need for an ever expanding digital computer capability and at the same time a need to isolate and remove the central controller from the environment of the reproduction machine to achieve error free operation.

It is an object of the present invention to provide a control system for a copier/ duplicator in which the above disadvantages are overcome.

According to the present invention, there is provided a control system for a copier/duplicator having a plurality of operating components, comprising in combination: A master microprocessor controller having memory for storing an operation program controlling said copier/duplicator, at least one active area controller, said active area controller being separate from said master controller, said active area controller having a microprocessor and a memory storing an operational program for controlling at least one of said copier/ duplicator operating components, and at least one passive area controller for controlling another of said copier/duplicator components in response to control data from said master controller, said active and passive area controllers each having ports for transmitting data to and receiving data from said master controller upon command of said master controller.

In one embodiment of the invention a master microprogram controller is operatively connected to various devices within the operating stations of the photographic reproduction machine and an active microprogrammed controller is used for controlling a particular device or devices (or positions thereof) such as those devices associated with a particular operating station. The master and active controller are interconnected via an optical link which serves to isolate the master controller from the direct I/O environment. Additional optical links may be provided to interface the master controller with a plurality of passive controllers which serve to latch the output of the master controller to the various controlled devices and serve to forward sensed output data from the operating station to the master controller for processing.

The master, passive, and active controllers are all operably connected to one another to control the various devices of the machine.

Inventions related to the present one are the subject matter of applications 8104324 (Patent No. 1,604,762) and 8104325 (Patent No. 1,604,763).

A control system for a copier/duplicator in accordance with the invention will now be described, by way of example, with reference to the accompanying drawings, in which FIGURE 1 is a block diagram of the overall master/area communication system; of a control system according to the invention; FIGURE 2 is a schematic illustration of various mechanical components of a copier/duPlicator; FIGURE 3 is a block diagram showing the major components of the master unit and an active and passive area controller; FIGURES 4A and 4B illustrate the master I/O interface and its input and output lines for interconnection to an area controller; FIGURE 4C shows a fiber optic interconnection link utilized for the communication channels; FIGURES 5 and 6 illustrate the transmission format for data communicated between the master and area controllers; FIGURES 7A and 7B show input and output port connections between the host machine and the area controller; FIGURE 8 shows a block diagram of the area microprocessor and its interface circuitry within the area controller; FIGURE 9 is a block diagram illustrating input and output port connections for a pseudo interrupt operation; FIGURE 10 is a block diagram showing the different computer states in accordance with the present invention; FIGURE 11 is a flow chart illustrating the overall structure of a machine state; FIGURE 12 is a flow chart of the state checker module for controlling changes of state within the machine; FIGURE 13 is a block schematic diagram showing the major portions of the paper path controller utilized in accordance with the invention; FIGURE 14 is a block diagram showing the major components of the RDH/ ADF control console controller; FIGURE 15 is a schematic drawing illustrating the major mechanical and electrical sensors and actuators utilized in the RDH/ADF control console controller as well as the servo controller.

FIGURE 16 illustrates a block diagram of the servo controller showing the key components thereof; FIGURE 17 is a schematic drawing of the key platen scanning components; FIGURE 18 is a block diagram showing the port structure utilized for the master-servo controller communication path; FIGURE 19 is a block diagram showing the input and output port connections utilized in the process area controller; FIGURE 20 is a flow chart showing the overall sequence goveming the communications between the process controller and the master unit.

System Overview FIGURE 1 is a block diagram of the overall Master/Area Communication System (MACS) utilized in controlling the copier/duplicator in accordance with the instant invention. MACS comprises a moster unit 1 including a master controller 2 in combination with a master I/O interface 4. The master controller 2 contains a microprocessor and memory units which govern the various tasks and operational procedures utilized in operating the copier/duplicator. The master I/O interface 4 is responsible for interconnecting the various address and data bytes from the master controller 2 to a plurality of area controllers 6, 8, 10, 12 and 14 which are responsible for specific tasks in the operation of the copier/duplicator.

Each area controller 6-14 is dedicated to performing a group of functions which are physically and/or logically related. The area controllers take on two general forms, an active controller which has its own processor control capabilities and a passive controller which has no processing capabilities per se and is simply utilized to latch outputs from the master controller and feed inputs thereto on the command of the master controller. FIGURE 1 illustrates five area controllers but it is within the scope of the invention to utilize any number of area controllers consistent with the address capabilities of the master controller. Illustrated in FIGURE 1 are three passive area controllers, namely, the paper path controller 6, RDH/ADF control console controller 8 and finishing station controller 14. Two active controllers are illustrated, namely, the RDH/platen servo controller 10 and processer controller 12.

The master controller 2 is responsible for the majority of system control processing tasks whereas the area controllers are responsible for the machine control functions.

Input and output data are transmitted between the master controller 2 and the area controllers 6-14 in a serial communications path via Master/Area Communication Channels 16 which may take the form of a plurality of fiber optic connections. The utilization of fiber optics interconnection for the MACS transmission channels greatly reduces control susceptibility to electromagnetic interference generated in the machine. Typically, it is desirable to physically position the area controllers in dose proximity to the particular device or devices controlled thereby.

Machine Description For a general undersanding of an electrophotographic printing machine in which the features of the present invention may be incorporated, reference is had to FIGURE 2 which depicts schematically the various components thereof. Although the control logic employed in the electrophotographic printing machine of FIGURE 2 is particularly well adapted for use therein, it should become evident from the following discussion that it is equally well suited for use in a wide variety of printing machines and is not necessarily limited in its application to the particular embodiment shown herein.

Inasmuch as the practice of electrophotographic printing is well known in the art, the various processing stations for producing a copy of an original document are herein represented schematically. Each processing station will be briefly discussed hereinafter.

As in all electrophotographic systems of the type illustrated, a drum 110 having a photoconductive surface 112 entrained about and secured to the exterior circumferential surface of a conductive substrate is rotated, in the direction of arrow 114, through the various processing stations. One type of suitable photoconductive material is a selenium alloy such as described in U.S. Patent No. 2,970,906 issued to Bixby in 1961. Preferably, the conductive substrate is aluminum.

Initially drum 110 rotates a portion of photoconductive surface 112 through charging station A. Charging station A employs a corona generating device, indicated generally by the reference numeral 116, to sensitize a partion of photoconductive surface 112. When energized, corona generating device 116 charges the portion of photoconductive surface 112 therebeneath to a relatively high substantially uniform potential.

Thereafter, drum 110 rotates the charged portion of photoconductive surface 112 to exposure station b. Exposure station B is arranged to produce a light image of an original document or series of documents being reproduced. In the electrophotographic printing machine depicted in FIGURE 2, exposure station B operates in one of two modes. In one mode, a plurality of original documents are recirculated in an automatic document handling system (ADH 132) so that sets of collated copies may be formed by the printing machine. In the other mode of operation, a single original document if placed on the platen 122 and reproduced by the printing machine. If the platen scan optics are used, mirrors 118 and 120 are moved into the operative position depicted in FIGURE 2. Lamp 124 moves across the original document disposed on platen 122 to illuminate incremental portions thereof.

The light rays transmitted from the original document are reflected by full rate mirror 126 to half rate mirror 128. Half rate mirror 128 reflects the light rays through lens 130 onto mirrors 118 and 120. These mirrors reflect the light image of the original document onto the charged portion of photoconductive surface 112.

Drum 110 rotates in synchronism with the movement of the platen scanning optics.

Thus, the charged portion of photoconductive surface 112 is irradiated to record an electrostatic latent image thereon corresponding to the information areas of the original document disposed on platen 122.

In the automatic document handling system for making pre-collated copy sets, the repeated collated imaging of a set of original documents is obtained by placing and retaining the original documents on an elongated windable document holding web 132. The web 132 is wound between two spaced web scrolls 133a, 133b positoned and wound so as to obtain the document between the turns of the web scrolls.

The web is repeatedly wound and unwound from one scroll to the other scroll (recirculated) to repeatedly expose individual documents thereon in an exposed portion of the web extending between the scrolls.

During the forward movement of web 132, a lamp (not shown) illuminates the original documents disposed thereon. Mirror 134 reflects the light rays toward stationary mirror 136 which, in turn, reflects the light rays toward rotating mirror 138.

Rotatable mirror 138 transmits the light rays through lens 140. The light image transmitted through lens 140 is reflected by mirror 142 onto the charged portion of photoconductive surface 112. In the ADH mode of operation, mirrors 118 and 120 are positioned remotely from the optical light path.

In the reverse scan mode, i.e. web 132 advances in the opposite direction to the forward movement, mirror 134 rotates 90C about its axis and reflects the light rays transmitted from the original document onto mirror 144. Thus, mirror 138 directs the light rays received from mirror 144 through lens 140. Once again, the light image transmitted through lens 140 is reflected by mirror 142 onto the charged portion of photoconductive surface 112. Thus, in either mode or operation, an electrostatic latent image is recorded on photoconductive surface 112.

As drum 110 continues to rotate in the direction of arrow 114, the electrostatic latent image recorded thereon is advanced to development station C. Development station C includes a developer unit 146 having a housing 148 with a supply of developer mix contained therein. The developer mix comprises carrier granules having toner particles adhering triboelectrically thereto. Preferably, the carrier granules are formed from a magnetic material with the toner particles being made from a heat settable plastic. Developer unit 146 preferably is a magnetic brush development system. In a system of this type, the developer mix is brought through a directional flux field to form a brush thereof. As depicted in FIGURE 2, developer unit 146 includes a pair of developer rollers 150 and 152. Each developer roller includes a stationary magnetic member having a non-magnetic, rotatable tubular member interfit telescopically thereover. The tubular member is rotated to advance the developer material into contact with the electrostatic latent image recorded on photoconductive surface 112. The developer material is advanced to developer roller 150 and 152 by paddle wheel 154 disposed in the sump of housing 148. Developer rollers 150 and 152 advance the developer mix into contact with the electrostatic latent image and the toner particles are attracted electrostatically thereto forming a toner powder image on photoconductive surface 112. As successive electrostatic latent images are developed, the toner particles within the developer mix are depleted. Additional toner particles are stored in toner cartridge 156. A sample electrostatic latent image is recorded on photoconductive surface 112 and developed. The density of the toner particles adhering thereto is detected via an ADC sensor 157 (not shown) and compared to a reference density.

The error signal developed thereby controls the dispensing of toner particles from cartridge 156. In this manner, the concentration of toner particles within the developer mix is maintained substantially constant. Developer rollers 150 and 152 are electrically biased to a suitable voltage. This voltage is adjustable and depends upon the original document as well as the duration of time that the printing machine is activated. After the toner powder image has been developed on photoconductive surface 112, corona generating device 158 applies a charge thereto so as to pre-condition toner powder image for transfer.

Ideally, carrier granules remain in housing 148 of developer unit 146. However, inasmuch as the sealing arrangements is imperfect, carrier granules may adhere to photoconductive surface 112 of drum 110. A scavenging roller 160 is provided for removing these carrier granules. Scavenging roller 160 comprises a magnetic member and a rotatable, non-magnetic tubular member interfit telescopically thereover. The tubular member rotates relative to the magnetic member. In this manner, the magnetic carrier granules are attracted from photoconductive surface 112, while the toner powder images remain undisturbed thereon.

With continued reference to FIGURE 2, a sheet of support material is advanced by sheet feeding apparatus 162 or 164 from either tray 166 or tray 168. Conveyor system 170 advances the sheet of support material to transfer station D. Rollers 172 speed up or slow down the advancing sheet of support material so as to ensure that it moves into contact with drum 110 in a timed sequence so that the toner powder image developed thereon contacts the advancing sheet of support material at transfer station D.

Transfer station D includes a corona generating device 174 which charges the backside of the sheet of support material to a level sufficient to attract the toner powder image from photoconductive surface 112.

After transfer of the toner powder image to the sheet of support material, a vacuum stripping system 176 separates the sheet from photoconductive surface 112 and advances it to fusing station E. If vacuum stripper 176 fails to separate the sheet from photosensitive surface 112, a redundant mechanical finger, i.e. stripper finger 198 activated by solenoid 199 (not shown), is provided to ensure separation of the sheet therefrom.

Fusing station E includes a fuser assembly, indicated generally by the reference numeral 178. Fuser assembly 178 fuses the transferred toner powder image to the sheet of support material. A suitable fuser comprises a heated fuser roll 180 and a resilient backup roll 182 in contact therewith. In this manner, the sheet of support material advances between fuser roller 18G and backup roller 182 with the toner powder image contacting fuser roller 180.

After the toner powder image is permanently affixed to the sheet of support material at fusing station E, a series of rollers advance the copy sheet either to finishing station F or to duplex tray 183 when duplex copies are being reproduced in the ADH mode of operation. After web 132 with the original documents thereon has advanced through one pass, the odd numbered sheets are copied. During the next forward scan, the even numbered sheets are copied and the information contained therein placed on the reverse side of the copy sheet. This sequence may be reversed.

Tray 133 is arranged to hold a plurality of sets of copies therein. Each sheet of support material having the toner powder image permanently affixed to one surface thereof is advanced from tray 183 by sheet feeding apparatus 184 onto duplex conveyor 185. Duplex conveyor 185 advances the copy sheet to conveyer system 170 where the sheet once again is advanced to transfer station D so as to receive the toner powder image corresponding to the second side thereof. Once again, the reverse side of the copy sheet passes through transfer station D and fusing station E. However, at this time the copy sheet is advanced to finishing station F.

After the toner powder image has been permanently fused to the copy sheet, either the duplex or simplex copy sheets are advanced by a series of rollers 186 to finishing conveyers 188. Finishing conveyors 188 advance the copy sheets to trays 190 or 192. The sheets are stacked in one tray, e.g. tray 190 with the odd sides up and the even sides face down, while in the other tray, e.g. tray 192 with the even sides up and the odd sides down. This orientation is required because of the forward and reverse movements of web 132. After the requisite number of copies have been stacked in the appropriate tray, i.e. sufficient copies to define a collated set thereof, staplers 194 and/or 196 are actuated to permanently secure the sheets to one another. In this manner, sets of collated copies are stored in trays 190 and 192 with each set having the copies thereof stapled to one another.

Residual toner particles are removed from photoconductive surface 112 at cleaning station G. Initially, discharge lamp 204 floods photoconductive surface 112 to assist in the dissiDation of any electrostatic charge remaining thereon prior to the cleaning thereof. Residual toner particles are then brought under the influence of a corona generating device 200 adapted to neutralize the remaining electrostatic charge on photoconductive surface 112 and that of the residual toner particles.

The neutralized toner particles are cleaned from photoconductive surface 112 by a rotatably mounted fibrous brush 202 in contact therewith. In addition, subsequent to cleaning, a discharge lamp 206 illuminates photoconductive surface 112 to dissipate any residual electrostatic charge remaining thereon prior to the charging thereof for the next successive imaging cycle.

Master/Area Communication System FIGURE 3 illustrates a more detailed block diagram of the master controller and the active and passive area controllers of FIGURE 1. For simplicity of illustration only one passive area controller such as the paper path contrcller 6 and a single active controller such as the process control controller 12 is illustrated. The master controller 2 comprises a central processing unit and system controller identified as a master microprocessor 300. A number of existing microprocessor systems may be utilized to practice the present invention. For example, the INTEL 8080A-2 CPU and INTEL 8238 System Controller by Intel Corp., Santa Clara, Calif., U.S.A.

The master microprocessor 300 is shown connected to memory units utilized to stole program memory and for temporary storage of various control and sense parameters.

The memory units comprise a read only memory (ROM) 302, a random access memory (RAM) 304 and a non-volatile memory (NVM) 306. The ROM memory may be for example a 48KB (bytes) mask programmable ROM, while the RAM may comprise a 2KB (byte) static MOS scratch pad memory and a 1 KB (bit) flag storage MOS RAM (bit D7 of RAM). The ROM may be fabricated, for example, using 2KX8 ROM chips model No. 8316As and the RAM memory may be implemented using lKX1 chips, model No. 2102. The NVM may be fabricated using 512X1 RAM chips model No. 52222 (American Microsystems Inc.). Equivalent chips may of course be utilized as for example the NVM may be fabricated from 256 X4 chips (model No. 5101L) if desired. The memory units are interconnected to the master microprocessor 300 by means of a tri-state master bus 308 which is also interconnected to the master I/O interface 4. The tri-state master system bus comprises eight data lines D0-TS through D7-TS, sixteen address lines A0-TS through A15-TS and a number of control and clock lines. The master microprocessor 300 is supplied with clock signals from the clock source 310 (INTEL clock generator 8224 for example) and is powered by an external power supply 312. Power for the various circuits in the master controller 2 as well as the master I/O interface 4 are first filtered by means of a filter circuit 314. A power normal signal is also fed to the master controller along line 316 from the power supply to indicate that power is up to normal operating levels. A reset signal from reset circuitry 318 is utilized to reset the various registers throughout the master controller and master I/O interface during a power up or initialization sequence. The power supply 312 also supplies power to the various remote controllers by means of lines 320.

The passive area controller exemplified by the paper path controller 6 comprises an area I/O interface circuit 340, latches 342 and drivers 344 which provide outputs to one or a plurality of machine controlled devices. Sense data is supplied from various sensing means to represent the current device operational state whose function is governed by the particular passive controller of interest. The sensed data is fed to buffers 346 and subsequently to the area I/O interface 340 for transmission along the mast area communication channel 16 to the master unit 2. The active area controllers are similar in function to the passive area controllers and likewise contain an area I/O interface 340, latches 342 and drivers 344. Sensed data may be provided to the master unit 2 through buffers 346, the I/O interface 340 and the communication channel 16. Additionally, however, the active area controller contains an area microprocessor/interface 348 which is separate and distinct from the master microprocessor 300. Shown in FIGURE 3 the area microprocessor/interface 348 is connected by means of an area system bus 350 to a plurality of latches 354 which feed drivers 344 to control various machine parameters. The area microprocessor/ interface 348 may additionally provide input information to latches 352 for subsequent feeding to the master unit 2 via the area I/O interface 340. The area microprocessor/ interface 348 may also be utilized to control analog data to various machine devices and to sense analog data from various machine sensing means utilizing D/A converters 364 and A/D converter 366 respectively. Data which is not controlled by the area microprocessor/interface 348 may be fed to and from the master unit 2 by means of the direct paths 360 and 362 as illustrated in FIGURE 3.

The servo control area controller 10 is similar to the process controller 12 and supplies a machine clock signal to the master unit 2 along channel 370 (see dotted line in FIGURE 3). This signal is derived from the photoreceptor drum of the copier/duplicator and is passed along a fiber optic link of channel 370 to provide au interrupt signal to the master microprocessor 300. The machine clock signal thus enables a synchronization of the master microprocessor 300 to the actual copier/ duplicator machines operation.

The Master Area Communication System utilizes a set of bi-directional communication channels 16 which independently couple each area controller 6--14 to the master unit 1. Each channel 16 comprises three groups of signal lines, namely, data-in, data-out and clock. The data-in and data-out lines are defined relative to the master controller and in the description set forth herein this terminology has been maintained throughout even in relation to data in area controllers 6-14. Data transfers between the master and area controllers is in bit serial form in eight bit increments (bytes).

An I/O transaction may be an input only transaction or a combined input/output transaction as specified by an initiating command byte from the master unit 1. A!l transmissions are in synchronism with and at the same rate as the 1.25 MHz clock signal from the master unit ;. All MACS communication is initiated by and under control of the master unit 2. Communication is always between the master unit 1 and the area controllers and communication never takes place directly between the area controllers.

D received address lines AO--TS through A18-TS as well as a plurality of control lines from the master svstem bus 308 to effectively decode and control the data on the master data bus 414. Shifting of the registers is synchronized with a 1.25 MHz dock signal from clock generator 426 which provides a 1.25 MHz clock signal to each of the area controllers. These clock signals are fed along line 428 to drivers 402 for transmission via fiber optic links 398 to the area controllers.

Output data from ACB register 422 and SDO register 418 is likewise shifted at the 1.25 MHz rate to a master data out line 425 and subsequently to drivers 402 and fiber optic links 398. Output data is also fed via a turnaround test line 430 to multiplexer 406 to optionally provide input data to the CCB register 412 and SDI register 410 in a master test mode of operation.

The control logic 424 decodes the address bits on the master system bus 308 address lines to determine if the address decode corresponds to the master I/O interface 4 so that the input and output registers may be appropriately gated.

The area I/O interface 340 comprises area input register 450, area output register 452 and control logic 454. The control logic 454 decodes the address received from the ACB register 422 of the master I/O interface 4 and selects particular groups of the input and output lines for providing or receiving data respectively. Each area controller is provided with a plurality of output ports 456 and input ports 458. In the preferred embodiment there are eight input ports and eight output ports wherein each port may contain as many as eight separate lines. Consequently, there may be sixtyfour separate input signals and sixty-four separate output signals to and from any given area controller. More specifically in terms of the detailed implementation of the control logic, input and output ports may be defined in terms of buffers and latches.

Output data bytes are stored in output ports or latches either for direct use by the machine or for use by other circuits in the area controller such as the area microprocessor/interface 348 (FIGURE 3). Input data bytes selected for transmittal to the master unit 2 are routed through buffers or input ports. Data is fed to the input ports directly from the host machine. In the case of data from the area microprocessor sent to the master unit I, the data is fed to latches which are used as input ports.

The particular I/O interface 340 shown in FIGURE 3 is common to both active and passive area controllers.

MACS Optical Link The master/area communication channel 16 may comprise data channels implemented by simple wire conductors or, alternately, by fiber optic links as illustrated in FIGURE 4C. The fiber optic apparatus shown in FIGURE 4C is common to both the clock and data lines, and a separate driver and receiver circuit are utilized for each channel 16. The light source is typically an LED and the received data from amplifier 400 is passed through a discriminator to produce two level logic signals.

MACS I/O Instructions and Operational Overview Preparatory to all serial communications over MACS, the master microprocessor 300 first generates a Master Command Byte into the MCB register 416 via the master system bus 308 and particularly the master data bus 414 forming part thereof. The Master Command Byte is effectively a ten (10) bit area command address word which spe'cifies which of the six possible area controllers is to participate in the MACS communication. Actual data transfer of the data in the SDO register 418 follows immediately the transfer of the Master Command Byte. The command information specifies both the type of transfer, such as input (read) or input/output (duplex transmission) as well as the specific group of eight bits to be sensed (input operation) or to be sensed and set (duplex operation). The contents of the MCB register 416 are uneffected by the transmission of the Area Command Byte inasmuch as the contents of the MCB register 416 are shifted into the ACB register 422 and then serially shifted f-om the ACB register 422 to all of the area controllers. The MCB register 416 can only be altered by a subsequent MCB write operation directed by the master microprocessor 300.

In relation to FIGURES 3 and 4, the master microprocessor 300 initiates and controls communication over MACS through the master I/O interface 4 via the master system bus 308. Both control and data transfers are performed through execution by the master microprocessor 300 of a sequence of memory reference instructions to specific dedicated addresses. These addresses are decoded directly off of the master system bus 308 and interpreted by the master I/O interface 4 to cause a desired I/O operation to occur.

Two memory addresses are dedicated for writing into the MCB register 416 by the master microprocessor 300. The "LOAD MCB" instruction is utilized to load the MCB register with a Master Command Byte in preparation for an I/O transmission. This instruction is utilized together with a subsequent write operation namely, the "LOAD SDO AND START TRANSMISSION" instruction which loads the output data byte from memory (via the master data bus 414) into the SDO register 418. Additionally, the "LOAD SDO AND START TRANSMISSION" instruction constructs and loads the Area Command Byte into the ACB register 422 from the MCB register 416. One bit of the ACB register is set by the parity generator 420 and a second bit of the ACB register is set by a command signal indicating a duplex or read only transmission, the R/D bit. Finally, the "LOAD SDO AND START TRANSMISSION " instruction is effective to start the actual MACS transmission. The Area Command Byte residing in the ACB register 422 is transmitted first followed by the Data Out Byte residing in the SDO register 418.

A second dedicated memory address is utilized for writing into the MCB register.

This alternate address is utilized in executing the "LOAD MCB AND START TRANSMISSION" and is effective to load a Master Command Byte from memory (master data bus 414) into the MCB register 416. Additionally, this instruction constructs and loads the Area Command Byte into the ACB register 422 appropriately setting the read/duplex bit and the parity bit. Finally, the instruction is utilized to start the actual MACS transmission. "LOAD MCB AND START TRANSMIS SIMON" consequently eliminates time delays associated with loading the SDO register 418 when initiating input only MACS transmissions (R/D bit equals zero).

The start of a MACS transmission for both the input only or combined input/ output (duplex) operation causes the broadcast of the serial bit stream from the least significant bit position of the ACB register 422 simultaneously to all area controllers.

Each area output register 452 of the area controllers simultaneously receives the transmitted Area Command Byte from the ACB register 422 followed by the Data Out Byte transferred from the SDO register 418. The Data Out Byte is serially shifted through the ACB register 422.

The transmission format for data in the various registers is illustrated in FIGURES 5 and 6. With reference to FIGURE 5, the data bits Dolt7 from the master data bus 414 are parallel loaded into the master ccmmand bit register 416 during a "LOAD MCB" instruction for example. Bits DO-D2 are termed the Byte Address bits C1--C3 and are utilized to select a group of eight input (sensed) lines as well as a group of eight output signals from a designated input and output port of a designated area controller. The designation of the area controller is made by means of Channel Select bits, CS1CS3 which correspond to bits D4D6 respectively from the data bus. Data bits D3 and D7 are not utilized in the MCB register 416 although bit D7 is available as a reserve command bit for special use if desired.

In a typical transmission operation the contents of the MCB register 416 are parallel loaded into the ACB register 422 (with the exception of bit D3). As shown in FIGURE 5, Byte Address bits C1--C3 are loaded into bits 1-3 of the ACB register 422, and the Channel Select bits CSl-CS3 are loaded into bits 4-6 of the ACB register 422. The 0th bit of the ACB register 422 is loaded with a "one" bit to indicate a Start of Transmission (ST). Bit 7 of the ACB register 422 is loaded by the parity generator 420 to provide either an even or odd parity over the preceding ACB bits (t6. Bit 8 of the ACB register 422 is loaded from the reserve command bit D7 of the MCB register 416 whereas bit 9 of the ACB register is loaded with a "R/D" bit indicative of a read only (R) operation or a duplex (D) input/ output operation as dictated by the type of instruction being executed by the master microprocessor 300. Consequently, the ACB register 422 contains the necessary byte and channel selection bits supplied by the MCB register and the Area Command Byte is transmitted prior to the actual Data Out Byte from the SDO register 418.

The terminology "Area Command Byte" is utilized to refer to all of the bits in the ACB register 422 even though the register is ten bits long. Typically, however, a byte is eight bits long and in particular, the Data Out Byte is composed of the eight bits L1-L8 stored in the SDO register 418 as shown in FIGURE 6. FIGURE 6 illustrates the transmission format of data being sent to and from the master unit as would apply, for example, in a typical duplex operation. The Area Command Byte always precedes the Data Out Byte sent from the master I/O interface 4. Upon receipt of the ST bit, each area controller examines the Byte Address C1--C2 for potential selection of a group of eight input lines and eight output lines (the input and output ports). Next, each area controller samples the Channel Select bits CS1- CS3 and compares their value with a three-bit identification value (hard-wired) unique to each area controller. The single area whose unique identification value matches the received channel select value determined by the Channel Select bits CS1CS3 will remain active and proceed to interpret the data transfer command as an input only or duplex operation and to act upon the Data Out Byte as required.

All other areas cease to participate further in the MACS transmission. The active area controller selected transfers the value of the selected group of eight input bits (designated by the Byte Address) to its area input register 450 (see FIGURE 4) and shifts this data, as a Data In Byte back to the master unit 1 in a time sequence as illustrated in FIGURE 6. As seen therein, the first bit of the Data In Byte is transmitted after the parity bit from the master controller is received in the area controller.

The last Data In bit is transmitted while the fifth bit is being received from the Data Out Byte. Consequently, the duplex operation involves the simultaneous transmission and reception of data by the master I/O interface 4. The selected area not only transmits the Data In Byte but also selects the designated group of eight output lines specified by the Data Out Byte received from the master I/O interface 4. Area timing is such that, for duplex operation, the Data In Byte is shifted back to the master unit 1 overlapped in time with the Data Out Byte. An entire duplex transfer requires eighteen shift clocks to be completed as illustrated in FIGURE 6.

After the Input Data Byte has been loaded into the SDI register 410 (FIGURE 4) the master controller 2 may read the input data by executing a "READ SDI" instruction or alternately "READ SDI AND START TRANSMISSION" instruction The "READ SDI" instruction completes the I/O operation and transfers the data from the SDI register 410 to the master controller 2 via the master data bus 414. The master I/O interface 4 then waits for the next I/O command. The "READ SDI AND START TRANSMISSION" instruction automatically reinitiates data transfer utilizing the previously established Master Command Byte which remains stored in the MCB register 416. Now, however, the input only mode is selected, e.g.

bit R/D of the ACB register is set to "0". In the input only mode, the SDO register 418 contains all zero's inasmuch as it is serially loaded with zero's during a data transfer. The utilization of the 'READ SDI AND START TRANSMISSION" instruction is advantageous for rapid multiple readings of input data as required for effective digital filtering of inputs. Typically, for example, software filtering utilizing this rapid multiple reading technique requires three consistent consecutive input data bytes If three such consistent consecutive bytes are received, the data is taken to be free from error.

The master I/O interface 4 also provides facilities for reading the CCB register 412 and MCB register 416 for interrupt processing and diagnostic purposes.

Table 1 listed below shows the specific addresses utilized by the master microprocessor 300 of the master controller 2 for control and data transfers.

TABLE 1 ADDRESS (HEX) READ FUNCTION WRITE FUNCTION

EDFC READ MCB LOAD MCB EDFB READ SDI & LOAD SDO & START I O START l,'O EDFA READ SDI LOAD MCB & START I O EDF9 READ STATUS WRITE STATUS EFFS READ CCB NO OP Simultaneous Area Operation In addition to communication between the master unit 1 and the specific area controllers 6-14, the master unit 1 may communicate with all of the area controllers simultaneously. To achieve simultaneous communication, the Channel Select bits are set to address 7 (CS3, CS2, CS1=111) in the Master Command Byte. Each area controller recognizes address 7 as a simultaneous mode transmission and consequently a common data byte may be simultaneously transmitted to each area controller. A common Output Data Byte is thus fed to the same output port in all area controllers as specified by the Byte Address bits C1--C3 (Cl-C3 = 111 is used in practice).

Additionally, this procedure allows the master unit 1 to read inputs for more than one area controller with a single I/O transaction. Inasmuch as the input lines are "ORed" together into a single serial input register, namely, the SDI register 410, mutually exclusive bit positions are assigned within the common Input Data Byte to the area controller during the simultaneous mode transmission. All bit positions within the common Input Data Byte not specifically assigned to an area controller are strapped to a value of "0" to avoid interference at the master unit 1. The simultaneous area operation may be utilized, for example, to effect a pseudo-interrupt procedure which is effectively a polling of various input data lines to the master unit 1 from each (or any desired number) of the area controllers. The master microprocessor 30Q has a single interrupt line which is actuated by the machine clock signal along channel 370 (FIGURE 3). This interrupt however, initiates a polling of the area controllers under a simultaneous addressing mode (address 7) to sample selected lines of the area controllers as a pseudo-interrupt byte. As a result, a single interrupt line of the master microprocessor 300 may be expanded into a plurality of pseudo-interrupt inputs from the area controllers.

Status Read and Write Commands In addition to the memory read and write commands listed in Table I, the master microprocessor 300 may execute status read and write instructions (also listed in Table I) to sense and control certain discrete master controller functions. The master microprocessor 300 operating under program control consequently may execute read and write memory reference instructions to address X'EDF9'. Data bytes transferred across the master data bus 414 during status read and write operations are called Master Status Read Bytes and Master Status Write Bytes respectively. The function of each bit in the Status Bytes is set forth in Tables 2, 3 and 4 below.

TABLE 2 Master Status Read Byte MASTER DATA BUS BIT POSITION BIT NAME FUNCTIONAL DESCRIPTION OF BIT 7 CLKFT Clock Fault; when set indicates that no shift clock is being transmitted to the areas. If this FLAG is set, the-software will inspect bit 6 to determine the polarity of the clock.

6 ASHFTCLK Area Shift Clock State; direct indication of the state of the CLOCK output to the area controllers.

5 4 3 - Not defined 2 1 - 0 HOLD Transmission incomplete. Equals "1" only when transmission is in progress.

TABLE 3 Master Status Write Byte MASTER DATA BUS BIT POSITION BIT NAME FUNCTIONAL DESCRIPTION BIT 7 CLKEN When set to "0", disables the clock to all area co.ltrollers.

(Forces clock low). When set to a "B", enables the clock to each area controller.

6 - Not defined.

5 RC3 Receiver Control Bit 3 4 RC2 Receiver Control Bit 2 3 RC1 Receiver Control Bit 1 RC3, RC2, RC1 are defined in Table 4.

2 CFTOK Area C/F'Test OK Flag. When set to a "1", causes the Area C/F test passed light (LED) to be on, when set to a "0", extinguishes the light.

1 MTOK Master Test OK Flag. When set to a "1", causes the "Master test pass" light (LED) to be On, when set to a 0, extinguishes light.

0 PARTIY When-set to a "1", creates parity error in the parity bit transmission, by complementing correct parity. Whe set to a "0", correct parity is generated.

TABLE 4 Master Status Write Byte-Receiver Control Bits.

RC3 RC2 RC1 Input Selected 0 0 0 The 'ORed' serial data input lines from all areas is selected. This setting is for normal MACS operations.

0 0 1 The serial data input line from the single Area specified by the RC bits (Area 1, 2. . .6) is selected. These RC settings are test modes to isolate a failing Area Controller.

1 1 1 The serial data output line from the Master SDO/ACB registers is selected.

This is a Master turnaround test mode to isolate Master failures. At the completion of serial transmission in this mode, the SDI/CCB registers will contain the contents of the SDQ/ACB registers.

Port Structure Figures 7a and 7b represent the general port structure for both passive and active area controllers. Shown interconnected to the area I/O TS bus 460 (from left to right in the drawing) are output ports OP7, OPO, OP1, OP5, OP6, OP2, OP3 and OP4.

Output ports OPS and OP6 are dedicated output ports connected in the active area controllers to an Area Data System bus 1500 (ADS bus) which forms the data bus portion of the Area System Bus 350 of FIGURE 3. In the passive area controllers output ports 5 and 6 are connected to drivers 1502 for direct connection to the host interface (host machine switches, relays, sensors, etc.) as indicated by the triangle containing the letter "H". Output ports, 2, 3 and 4 in passive area controllers have their inputs connected directly to the area I/O TS bus 460 as indicated in dotted lines. For active area controllers output ports OP2, OP3 and OP4 are connected to the ADS bus 1500 as illustrated by the solid interconnection lines. Each line from both the input and output ports actually consist of eight individual lines coresponding to data bits DeD7.

In a similar fashion the input ports are shown in Figures 7a and 7b interconnected to the area I/O TS bus 460 and to the ADS bus 1500. Input ports 3, 4 and 5 are connected to the ADS bus 1500 in active area controllers, and input port 6 is a dedicated input port from the ADS bus 1500 to the area I/O TS bus 460 on active area controllers. In passive area controllers IP6 is connected via a pull up and diode network 1504 to the host interface as are all of the host connected input ports in both active and passive area controllers. It is noted that all input ports with the exception of IP6, are implemented by means of tri-state buffers (National Model No. DM8097, for example) whereas input port 6 is a data latch wherein data is strobed in and out as demanded by the input and output control mechanism (the master microprocessor and the area microprocessor). For example, the data latch 1508 may be the Intel model no. 8212. In practice, all output ports are also data latches (model no. 8212), and all such latches which interconnect directly to the host interface are fed to drivers 1502 (as for example model no. 7406). Output port OP7 is shown interconnected to a multiplexer 1510 which feeds IP7 via a pull up network 1504. One input to the multiplexer 1510 is also supplied from an inverter 1512 which is fed by an Area Microprocessor Response signal (AMR signal) generated at the interrupt output of the data latch 1508 associated with input port 6. Interrupts are also provided to the area microprocessor via two interrupt signals, one supplied from output port 5 and another from output port 6. Particularly, data latch 1508 of output port 5 provides an Area Microprocessor Attention-1 signal (AM--ATTN1) which is supplied by inverter 1514 to the tri-state buffer 1506 of input port 5. Similarly, data latch 1508 of output port 6 provides an interrupt signal called Area Microprocessor Attention-2 signal (AM-ATTN2) which is fed to the same tri-state buffer 1506 of input port 5 via an inverter 1516. These two attention bits are utilized to designate to the area microprocessor that data is ready in the data latch 1508 associated with output ports 5 and 6 to be read onto the ADS bus 1500.

It is pointed out that the data latches 1508 forming the output ports 5 and 6 are effectively "interrupting input ports " with respect to the area microprocessor/interface 348. As such, data may be strobed into the input terminals of these data latches via an input strobe signal STB (OPS STB or OP6 STB) at which time an interrupt signal is automatically generated and may be utilized to interrupt the area microprocessor.

The interrupt signals are termed AM-ATTN1 from output port 5 and AM-ATTN2 from output port 6. Data may be strobed from these data latches onto the ADS bus 1500 upon reception of a low signal at the DS1 device select terminal of the data latches 1508. For a more complete description of the data latches 1508 reference is made to the Intel 8212 data sheets as appear on pages 5-101 through 5-104 of the Intel 8080 Microprocessor System User Manual referred to above.

Area Microprocessor and Interface A blocked diagram of the area microprocessor 348 showing its interconnection to the area system bus 350 is illustrated in Figure 8. The area microprocessor/interface 348 comprises an area microprocessor 1600 which may be, for example, the Intel 8080 utilized in the master controller 2. The area microprocessor/interface 348 further comprises an external read only memory 1602, clock generating means 1604 and a number of buffer units for data going into and out of the area microprocessor 1600 and data readout from the external ROM 1602. These buffer units are identified as external ROM buffer 1606, input buffer 1608 and output buffer 1610. The area microprocessor controls the input and output buffers by means of a selection circuit 1612 which receives a number of control lines 1614 from the area microprocessor 1600 and a number of address lines 1616 from the Area Address System bus (AAS bus) 1620. The AAS bus 1620 is a twelve bit address line identified as lines LADR0-LADR11. The ADS bus 1500 is an eight line data bus identified as DB0-DB7. The selection circuit 1612 provides output signals along lines 1622 to control each of the buffers 1608 and 1610 thereby controlling data to and from the area microprocessor 1600. Selection circuit 1612 also supplies selection signals to the external ROM 1602 which additionally receives part of the address lines from AAS bus 1620. The address lines of AAS bus 1620 passed through buffers 1621 as shown.

The area microprocessor/interface 348 further comprises an interrupt circuit 1626 connected to a clock output CLKB of the area microprocessor 1600 and to additional control lines (NRST and NINTA) to provide an external interrupt signal which is synchronized with the area microprocessor clock (2MHz). The interrupt circuit provides an interrupt signal along line 1628 to the area microprocessor 1600. A CLK2 detection circuit 1630 is also provided to detect the presence of the CLK2 signal from the area clock generator circuit within each area controller. If the CLK2 signal is not present, the detection circuit provides an NRST signal to the area microprocessor 1600 along line 1632 to maintain the microprocessor in a reset condition. The CLK2 signal would not, for example, be present during a power-off condition or a system malfunction. Both the interrupt circuit 1626 and the CLK2 detection circuit 1630 are supplied by the 1600 CLKB signal from the microprocessor via line 1634.

The external ROM 1602 comprises, for example, Intel 8708 programmable read only memories wherein the chip select (cos) signal is supplied from a LADR1K and NLADR1K signals from selection circuit 1612. The external ROM buffer 1606 comprises, for example, a model no. 8097 HEX buffer (National Semiconductor, for example) and the device selection inputs thereto are both connected to a not memory read control signal from the area microprocessor 1600 NMEMRD. Upon reading information from the external ROM 1602 the area microprocessor 1600 generates a logical "0 " as the NMEMRD signal to gate the external ROM buffer 1606 and additionally generates an appropriate address to indicate an external memory address. The area microprocessor 1600 contains 1K memory in an internal read only memory and may address 3K additional memory bytes in external memory. Consequently, when the address on the AAS bus 1620 is greater than 1K, the selection circuit 1612 is utilized as the chip select signal to strobe information from the external ROM buffer 1606.

Once data has been strobed from the external ROM 1602 through the external ROM buffer 1606 it is passed through the input buffer 1608 into the area microprocessor 1600 for processing. Output data is fed via the output buffer 1610 to the ADS bus 1500. The selection circuit 1612 gates the input and output buffers.

Pseudo-Interrupt Operation In reference to Figures 7a and 7b, it is noted that each area controller has an output port 7 and input port 7 dedicated to psuedo-interrupt operation. The pseudo-interrupt operation is selected by setting CS1-CS3 to octal 7 (Channel Select byte 111).

Upon receipt of the 111 Channel Select byte all area controllers will be responsive to the C1--C3 Byte Address. For the simultaneous mode operation the Byte Address is likewise set at 111 designating the output port 7 and the input port 7. Inasmuch as all of the areas are simultaneously gated for transmitting input data to the master controller, only selected bits from each area controller are enabled so that mutually exclusive bit positions are used with the results wire "ORed" by the master I/O interface 4. Thus, data received will not contain any overlapping bit information. FIGURE 9 is a diagram of the output port example, bit position 3 of output port 7 is connected to logic circuit 1720 for selecting either the input sense terminal 1701 or 1702 for interconnection to bit 3 of IP7 via line 1722. Logic circuit 1720 comprises inverter 1724, AND gates 1726 and 1728 and OR gate 1730. Bits 5 and 6 of OP7 are utilized as selection control lines to a four-one multiplexer 1732 (model no. 74153) to select one of the four input sensed terminals 1703--1706. Similarly, bit 4 of OP7 is used to condition the presence or absence of the duplex tray information from sense terminal 1707 via AND gate 1734. All terminals in IP7 not utilized are strapped to 0 volts so as not to interfere with data being transmitted from other area controllers on the unused bits.

The control console area controller 8 utilizes bits 4 and 7 to condition the ADF sensor and RDH leading edge sensor respectively into respective bits 1 and 7 of IP7.

AND gates 1736 and 1738 together with inverter 1740 and 1742 are utilized for this purpose. The input sense terminals for the control console 8 comprise the RDH leading edge sense terminal 1746, the ADF sense terminal 1747 and the A track sensor terminal 1748.

The servo controller 10 is an active area controller having a platen leading edge sense terminal 1750 feeding bit 7 of IP7, and also supplies bit 4 of IP7 with the Area Microprocessor Response signal (AMR signal) from the interrupt output signal of data latch 1508 of IP6 (see FIGURE 7b). The platen leading edge sense signal from 1750 is conditioned via AND gate 1752 from bit 7 of OP7.

TABLE 5 PSEUDO INTERRUPTS

INPUT OUTPUT BIT AREA BIT POSITION CONTROLLER PSEUDO-INTERRUPT INPUT POSITION D7 MACAS/Console MACAS Lead Edge Sensor D7 = 0 Servo Platen Lead Edge Sensor D7 - 1 D6 I Paper Path Reg. Lead Edge Sensor D6 = 0 D5 = 0 Paper Path Reg. Trail Edge Sensor 1 =0 =1 Paper Path Reg. Trail Edge Sensor 2 = 1 = 0 Paper Path ~ Reg. Trail Edge Sensor 3 = 1 = 1 D5 j Process Control Process Control pP Resp. None D4 Servo Servo gP Response None D3 Paper Path Main Tray Hold Stn. Sensor D3 = 1 Paper Path Aux Tray Hold Stn. Sensor D3 = 0 D2 Paper Path Bi-Level Xport Sensor None D1 MACAS/Console ADF D4 = 0 Paper Path Dup. Tray Hold Stn. Sensor MACAS/Console A Track Sensor None It is important to note that inasmuch as the output data from all of the area controllers is wire "ORed" at the input to the master I/O interface 4, the data bits are mutually exclusive as to the information conveyed thereby. Consequently as an example, if output bit position 4 (D4) in OP7 is a logical " 1 " then AND gate 1734 will strobe the information on duplex tray terminal 1707 into bit 1 (D1) of the input port 7 (IP7). At the same time inverter 1740 of FIGURE 27 will prevent the strobing of information on the ADF terminal 1747 into bit position 1 of IP7. Conversely, if bit 4 of the output data byte strobed into OP7 is a 0, then information on the ADF terminal 1747 will be strobed into D1 of IP7 whereas the duplex tray information on terminal 1707 will be excluded. The software in the master microprocessor 300 must in fact keep track of the output data byte transmitted during the simultaneous mode operation in order to interpret the received data sent on a subsequent transmission from the area controllers under the simultaneous area operation.

Machine Clock Interrupt The speudo interrupt polling technique outlined above is implemented every time a machine clock interrupt is received. The machine clock interrupt is derived from the servo controller 10 from a phase lock loop (PLL) circuit whose nominal output frequency is 800 Hz. The PLL provides a continuous clock source which is in phase lock with the machine clock output of a photo-receptive drum encoder whenever the drum is up to speed. The signal from the PLL (LOCK signal) is true whenever the machine clock is within a defined speed range of the PLL. The signal is available to the master controller as in input bit accessible through normal MACS transactions. The machine clock interrupt signal output from the PLL is transmitted from the servo controller to the master controller via a dedicated fiber optic link (line 370 of FIGURE 3).

Real Time Interrupt The real time clock interrupt (RTC) consists of a counter which may be programmatically initialized to provide an RTC interrupt frequency ranging from 75.1 Hz to 19.23 KHz. The counter is mechanized into stages. The first stage is driven by the free-running 1.25 MHz clock and divides this frequency down by 65 providing a 19.23 KHz output. The 19.23 KHz clock is used as both an input to the second counter stage, as well as the free-running source for the selectable slow clock used in the generation of the reset to the area microprocessor in active remotes. The second counter stage is loaded from an 8-bit programmable register each time the counter overflows, and depending on the value stored in the register, divides down the 19.23 KHz clock from 1 to 256 times further. Thus, the output of the second stage is in the range of 75.1 Hz to 19.23 KHz, and controls a flip-flop whose output feeds into a priority circuit which also receives the machine clbck interrupt signal.

Software is utilized to control the master microprocessor and area microprocessors.

Software controlled events may be foreground events which are keyed to the machine cycle (photoreceptor drum rotation) or background events which need not be critically synchronized to the machine cycle. Foreground events have priority over background events. The software is partitioned so that it runs in one of several "states" which correspond to the status of the machine. In each state a set of subroutines is called repetitively to monitor the machine status and control the changes from state to state.

In addition, when the host machine is in the print state, a set of event which are syn chronized to the motion of the paper through the machine are called to control the copy process. FIGURE 10 diagramatically illustrates the various states and the permissible transitions between the states. When the system is initialized by power-on or reset, the self test programs are run which check the ROM and RAM memories as well as the non-volatile memory. All flags and variables are initialized and the NOT READY state is entered if the self test programs are successfully passed. The various machine states as illustrated in FIGURE 10 may be summarized as follows: NOT READY - The machine is not yet ready to run. This state may result from various factors such as interlocks being open, insufficient fuser temperatures, insufficient electrostatic voltages or faults existing in any selected features. The NOT READY state is entered after power up initialization, after a job has run or after a technical representative component control or remote control diagnostic state is completed. A job may be programmed in this state but not started.

READY - This state is entered from the NOT READY state when the machine is ready to run. A job may be programmed.

PRINT - This state is entered when a job is started and is the state in which copies are produced. It always exists to the RUN NOT PRINT state.

RUN NOT PRINT - This state is entered whenever the PRINT state is terminated and controls the stopping of the machine. When all functions of the machine have stopped, it goes to the NOT READY state.

TECH REP - This state may be entered when the machine is not running and is utilized by the technical representative for operation of special diagnostics for component control checking.

COMPONENT CONTROL - This state allows selected components of the machine to be exercised.

REMOTE DIAGNOSTICS -- This state is entered when the machine is in READY, NOT READY, or TECH REP states and the carrier is detected by a data modem which permits access to the machine via a telephone line.

Referring to FIGURE 11, it may be seen that each state is normally divided into PROLOGUE, LOOP and EPILOGUE sections. The program responsible for checking on the current status of the machine in taking care of changes from one state to another is called the state checker routine. Entry into a given state (PROLOGUE) normally causes a group of operations to be performed. These PROLOGUE operations consist of operations that are performed only once at the entry into the given state. For complex operations, a call is made to an applications subroutine. Relatively single operations such as turning on devices, clearing memories, presetting memories, etc. are done directly. Once the PROLOGUE is completed the main body (LOOP) is entered. The state checker routine remains in the LOOP until a change of state is requested and honored. On a change of state request, the state EPILOGUE is entered wherein a group of operations are performed following which the state moves into the PRO LOGUE of the next state to be entered.

The state checker routine, which is the basic background operating program, monitors the current state of the machine and controls changes from one state to another and executes the various background routines which may be arranged at intervals such as 10 ms and 100 ms timeouts. During the 20 ms and 100 ms timeout conditions, a call list is executed to perform certain background operations appropriate to the state of operation of the machine. The real time clock (RTC) may also be utilized to set 10 ms flags or 100 ms flags which are not generally included in call lists and may be performed only under certain specified or desired conditions such as in controlling the interactive display (blinking message), paper tray elevator checker, etc.

In reference to FIGURE 12, if the carry condition code is set, then the 10 ms timer has timed out by the real tome clock interrupt handler and the appropriate subroutine associated with this timed-out feature is called and executed. After execution, the QTABLE is updated, and the state checker than checks to see if a new state has been requested. If so, the EPILOGUE for the present state is called and then the PROLOGUE for the next state is called.

time clock in the event of simultaneous interrupts. The real time clock interrupt handler schedules all of the background task through either 20 ms or 100 ms flags via the call list or by passing a subroutine pointer for any timer that times out. The machine clock interrupt schedules and calls all of the foreground events which control the actual copy making process in the PRINT state.

The machine clock interrupt routine increments a counter (modulo 256) and checks if the top event in an ordered table (QTABLE) is supposed to be done on this count. If the top event is due, it is removed from the QTABLE and executed. Events are added to the QTABLE by a background subroutine (Q@UPDATE) whenever the last entry in the QTABLE is less than 30 counts from the present count time. The copy table contains the next event to be done for each pitch currently in process. The closest event of those in the copy table is moved to the end of the QTABLE and the copy table is updated to the next event in the event table. The event table is a list in RAM of the master microprocessor of the events that are called for the current jobs.

The event table will be dependent, of course, upon the particular job selected by the operator such as, simplex/duplex operation, magnification, etc. If the new entry in the QTABLE has the same count as the last previous entry, then the new entry is incremented by one since no two events in the QTABLE may be scheduled on the same count. Events are added to the end of the QTABLE until the last event is 30 or more counts from the present event time. When a new sheet is added to the program, those events which would be ahead of the The EPILOGUE is used to change those flags, variables, timers or outputs that should be changed before leaving a state, and the PROLOGUE is used to change those flags, variables, timers or outputs that are initialized when entering the new state.

If the 20 ms flag has been set by the real time clock, then all of the subroutines in the 20 ms list are called and executed. When all of the 20 ms subroutines have been called, the 20 ms flag is cleared and, if the 100 ms flag has been set by the real time clock, one of the 100 ms calls is executed or one of the 100 ms timeouts is executed.

Foreground events have highest priority and are goverened by the machine clock interrupt handler (800 Hz) and the real time clock handler (10 ms). These two interrupts are fed to a priority circuit which selects the machine clock over the real last entry in the QTABLE are counted and the count and event information is kept in a catch-up table. These events are sequentially counted down by the machine clock and called at the correct time.

Paper Path Area Controller The functions of the paper path area controller are illustrated in block diagram form in FIGURE 13. As shown therein, output data from the data latches and drivers (data latch 1508 and drivers 1505 of FIGURE 7) may provide as many as sixty-four output data lines to various system devices within the paper path environment. Similarly, the tri-state buffers 1506 may handle as many as sixty-four input lines each line provided by a pull-up and diode protection network as required. The output latches and drivers are identified by number 2000 in FIGURE 13 and the various input buffers together with any associated pull-up and diode networks are indicated as element 2002. The latch and river network 2000 supplies for example six output signals to control various functions of the main/auxiliary tray control unit. Six additional lines are provided for the registration unit 2006, four lines to control the drum mechanism 2008, six lines to control the billing meters 2010, seven lines to control the duplex tray unit 2012, four lines to control various jam sensors and paper path diverters generally designated 2014, one line to control the mirror selection unit 2016 for RDH/ platen operation, and five lines connected to a relay panel 2018 for various miscellaneous operation controls. Input lines as shown may also be provided from these same above-enumerated units as well as from miscellaneous interlocks identified generally as 2020.

RDH/ADF Control Console - Controller 8 An overall block diagram of the input and output lines for the RDH/ADF control console 8 is illustrated in FIGURE 14. As can be seen, a plurality of input and output lines are connected to provide function controls for the RDH/ADF operating modes.

These function controls may include, for example, sensing and controlling vacuum sources, scroll position, various pinch rolls and the like. The functions controlled by these input and output lines do not typically include servo functions which are separately controlled by the active area controller 10. It may also be seen that various input and output lines are connected to an interactive display which is located on the operator console of various jam conditions. Additionally, the interactive display may provide sequential step information for various non-jam modes of operation in the machine. An audible alarm is also provided by means of control lines to an auditron as indicated.

A plurality of front panel input and output lines are also provided as a means to allow operator control of machine modes and job requirements. For example, the operator may select a number of copies for a multiple copy run, whether the machine is to be operated in the RDH or platen mode, the magnification desired, contrast information, simplex/duplex information paper size and the like. Various LED and seven-segment displays are provided to assist the operator in programming the particular job as required. Table 6 shows input and output signals utilized in the area controller 8, namely, those signals utilized as the function controls for the RDH/ADF mechanism as well as for the interactive display. It is noted in Table 6 that the input signals for the function controls and the inter-active display are identified by the labels CCI1--CCI19 (Control Console Inputs). Similarly, outputs are labeled CCO1-CCO16 (Control Console Outputs). It is also noted that the term RDH (recirculating document handler) is interchangeable with the term MACAS, the latter term used extensively in the computer listings.

FIGURE 15 shows in more detail the key input sensors and output devices under the control of the RDH/ADF Control Console 8. Elements corresponding to those of FIGURE 2 are similarly labeled. The web 132 is rolled around scrolls 133a and 133b.

Scroll 133a may be moved into different positions to allow manual or automatic (ADF) loading, and for run positioning. The Automatic Document Feeding (ADF) apparatus may be provided on the machine as an optional feature and is shown in dotted lines.

Also illustrated in FIGURE 15 are three vacuum blower motors 2040a-c used to bold the document securely against web 132. A shutter 2042 reduces the effect of vacuum motor 2040b to allow ease of document loading. Pinch rollers 2044 provide the driving means for web 132. A gate 2046 is utilized for initial document registration during document loading, and sensors are utilized to indicate the gate finger up or down position. Sensors are also provided to monitor registration apertures positioned along the edge of web 132. These "tracks" (A and B) are used to provide position and speed information to the servo control area controller 10.

TABLE 6 FUNCTION CONTROLS INPUTS ID NO. INPUT SIGNAL CCI1 Vac. Sensor #1 CCI2 Vac. Sensor #2 CCI3 Vac. Sensor #3 CCI4 Vac. Shutter Position CCI5 ADF Feed Tray CCI6 ADF Feed Head CCI7 Mirror For/Rev CCI8 Scroll Position #1 CCI9 Scroll Position #2 CCI10 MACAS # Track CCI11 Track B1 CCI12 Track B2 CCI13 Pinch Roll Sense CCI14 Gate Sense CCI15 MACAS Lead Edge CCI16 Multisheet Feed ADF CCI17 MACAS Cover ILK INTERACTIVE DISPLAY INPUTS CCI18 Orientation Request CCI19 Index Reference FUNCTION CONTROLS OUTPUTS CCO1 Front Blower CC02 Middle Blower CC03 Rear Blower CC04 Mirror For/Rev CCOS Vac. Shutter CC06 MACAS Patch CC07 ADF Pinch Roll CC08 MACAS Pinch Roll CCO9 MACAS Gate CCO10 ADF Reverse CCO11 MACAS Cover Detent CCO12 MACAS Cover Lock CCO13 ADF Motor Control INTERACTIVE DISPLAY OUTPUTS CCO14 Lamp Driver 21 CC015 Lamp Driver #2 CCO16 Motor RDH/Platen Servos - Controller 10 The area controller 10 governs the RDH and platen servos as diagramatically illustrated in FIGURE 16. The prime purpose of the servo remote controller 10 is to control' four motors, namely, the RDH motor 3000, the platen motor 3002, the reduction optics motor 3004 and the scroll motor 3006. The RDH motor 3000 controls the movement of web 132 when utilizing the pre-collating feature available for the recirculating document handler. A tachometer 3010 and an encoder 3012 provide various input signals to the area controller 10 as shown. A similar tachometer 3014 and encoder 3016 are associated with the platen motor 3002 and additionally provide input signals to the area controller 10. The platen motor 3002 is utilized to drive the scanning lamp 124 (FIGURE 2) for platen scan mode operation of the machine.

Reduction optics motor 3004 provides the drive means for positioning lens 130 (FIGURE 2) enabling use of the variable magnification feature of the machine.

Encoder 3020 is utilized to provide position signals to the area controller 10 which signals are indicative of the position of lens 140.

Scroll motor 3006 is utilized to position the scroll carrying web 132 to provide paper feed input, run position, ADF feed positioning and the like.

FIGURE 17 shows the major optical scanning elements of the machine which are used during platen scan operations. The stand-by position for the scanning lamp 124 (which is physically connected to a carriage together with mirror 126 as indicated by dotted lines) is shown as position A, and is used during RDH operations as well as machine stand-by. Position A is termed the home or garage position. In utilizing the platen scanning mode of operation, the operator selects the desired copy paper size, the desired magnification and initiates platen scan by pushing the start scan button.

From the copy paper size and magnification information, the master unit caliculates the required velocity and end of scan (EOS) position of the lamp 124. This informa tion is fed to the servo controller 10 to control the lamp motion. Prior to a document scan an initialization or dummy scan is made while other machine devices are prepar ing for the platen scan mode (copy paper feed, etc.). During this initialization scan, the carriage moves to the leading edge (LE) sensor, position B. A document pre-scan takes place from position B to position C after which follows the document scan proper from left to right in FIGURE 17. The distance between position B and C is quite small and the LE sensor will remain active, generating the LE signal until the lamp moves off the sensor going from left to right (document scan) in FIGURE 17. The end of scan (EOS) occurs at position D which, of course, is variable depending on the copy paper size and magnification selected. The lamp 124 remains at the EOS position until the end of the initialization step after which a true document scan takes place, e.g.

position D to position C for retrace and pre-scan and position C to position D for document scan. After scanning, the lamp 124 remains at position D until another document scan is requested, and, if none occurs within a particular time-out alloted, the lamp 124 moves back to the home or garage position A.

The lens 130 is controlled by the reduction optics motor 3004. A lens home signal is generated by a fixed sensor which, together with encoder signals, enables control of the position of lens 130 to enable selection of the desired magnification.

Master/Servo Software Communications The servo controller 10 is an active area controller and is similar in overall structure to the process control controller 12 illustrated in FIGURE 3. As such, a number of input sense signals and output drive signals go through the controller and are not specifically controlled by the area microprocessor 1600 of the active servo controller 10. Other input and output signals, are however controlled by the area microprocessor 1600. Thus, control of the functions of the servo controller 12 is divided in that some functions are passed to the master unit 1 for control and other functions are controlled directly by the area microprocessor 1600. The area and master microprocessors are programmed to cooperatively function to produce all of the necessary control signals which are within the realm of the servo controller 10.

Communications between the area microprocessor 1600 and the master I 0 interface 4 is illustrated in Figure 18. Figure 18 is similar to Figure 7B except that two input ports and two output ports are dedicated to master microprocessor/area microprocessor communications.

The servo controller/master communications instruction set consists of a group of single-byte and two-byte instructions. The instructions set is also divided into command instructions and data instructions. The command instructions result in a load motion change, i.e. RDH stop, platen start scan, etc. The data instructions determine a speed or position for the appropriate load instruction.

All of the command instructions and some of the data instructions are single-byte in length. These are called command bytes and are read by the area microprocessor from its command byte input port (the area microprocessor input port is effectively the master output port, e.g. the area microprocessor command byte is present on OP6 of Figure 18.) The data instructions which require a calculation by the master microprocessor 300 are two bytes long. The first byte is the command byte which identifies the particular servo system (scroll, RDH, reduction or platen) and tells what the data represents. The second byte, the data byte, contains the actual data that gets stored into the area microprocessor memory. In the case of the two-byte instructions, the command byte is read from the command byte input port (OP6 of Figure 18), and the data byte is read from the databyte input port (OP5 of Figure 18). The command byte comprises eight bits. Bits C3 designate the particular instruction field designating the desired instruction. Bits 4 and 5 are utilized to designate a normal operation/ diagnostic mode instruction and a data/command instruction, respectively. For example, when bit 5 is set the particular instruction is a command instruction; otherwise, it is a data instruction. Bits 6 and 7 comprise the system or " S " field. These bits identify the particular servo to which the instruction pertains. Bit 6 is designated S1, and bit 7 is designated S2. The following code is utilized: S2 S1 Servo 0 0 Scroll 0 1 RDH (MACAS) 1 0 Reduction 1 1 Platen The data byte format is quite straightforward, D7-D0 corresponding to bits 7 and 0, respectively, in the data field with bit 7 being the most significant bit and bit 0 being the least significant bit.

Status return information, as seen in FIGURE 18, is fed from the area microprocessor to the master microprocessor via input ports IPS and IP6. The status return byte is used by the servo controller to communicate to the master unit the present status of the servo system program. When the status of one of these systems changes, the appropriate bits of the byte are changed. The change is initiated in response to an instruction from the master unit with the corresponding execution of the servo controller microprocessor. The new status is loaded into the status return port (IP6) which initiates, when polled, a' pseudo-interrupt for the master unit.

The format of the status return byte is similar to the command byte format. Bits 0--3 corespond to the instruction field command instructions. Bit 4, represents the ready/busy (not ready to receive instructions), status of the servo controller microprocessor. Bit 5, is cleared if the error checking routine within the servo controller microprocessor detects a transmission fault. Bits 7 and 6, correspond with the S-field of the com

Process Controller 12 The area process controller 12 (PCR) is an active area controller and contains an area microprocessor 1600. The process controller cooperates with the master microprocessor in providing process control of various devices within the copier/duplicator.

The process controller may be located in the power supply unit and is utilized for all A/D conversions, control of the developer unit (ADC control) electrometer, high voltage corotron outputs, lamp outputs and various developer outputs including the tdner dispenser motor. The process controller also provides D/A conversions in order to generate the needed analog signals to control various voltages and currents. The PCR may be incorporated in a closed loop system. In particular, analog data is digitized and processed either in the PCR microprocessor or in the master microprocessor. The processed data is subsequently converted into analog form via the D/A converters in the PCR. The analog data is then applied to control the very devices which were sensed thus completing the closed loop control. Other devices may, of course, be operated in open loop control systems.

FIGURE 19 illustrates the process control area microprocessor 1600 and its interconnection to the various output and input ports.

A letter "M" is utilized as a prefix to the OP or IP port designation to indicate a master input or output port. For example, the master output port 5, MOP5, is an input port 5, IPS, with respect to the area processor 1600.

Master/PCR Software Communication FIGURE 20 shows a flow chart for the PCR communication with the master unit.

The attention flag is set when the master loads information into the command and data ports. The PCR reads the data byte first and then reads the command byte following which the attention flip flop is reset. The command and data bytes are added together and echoed to the master for a communication error check. Upon receipt of an acknowledge command from the master, the instruction is executed by the PCR.

The master may command the PCR to perform an A/D reading or to read and store a setpoint for the internal RAM of the area microprocessor. The digital value of the setpoint is converted into an analog signal to provide appropriate analog voltage or current control. The PCR periodically checks analog voltages or currents, compares their value to the setpoint value and provides new data for the output registers if required (with subsequent D/A conversion) to maintain the setpoint value. The PCR also provides digital output signals to turn on and off device power and voltages. The master also transmits acknowledge signals and " OK to send " signals to the PCR. The PCR may communicate to the master by providing three basic responses: the A/D reading response (the digital value of the analog signal requested), a fault code response (indicating which of a plurality of circuit boards has a fault therein), and the communications response (the echo sum of the data and command bytes).

When the master communicates to the PCR for a A/D reading, the master may designate which of three separate filter techniques should be employed. The PCR will then sample the analog values, convert them to digital form and provide the appropriate filtering requested, namely, the pitch event filtering, the noisey signal filtering and the fast read and negative peak filtering. The pitch event filtering is essentially a sum of eight separate readings; the noisey signal filtering is essentially the sum of sixteen separate readings; and the fast reading or negative peak filtering is a single analog reading. The master unit may also specify the range utilized in the A/D and D/A conversions. A 1X range corresponds to a 32 mv/bit conversion factor while a luX range corresponds to a 3.2 mv/bit factor. The 1X range of course has a very large dynamic range (08 volts) as compared to the 10X dynamic range (e0.8 volts).

WHAT WE CLAIM IS: 1. A control system for a copier/duplicator having a plurality of operating components, comprising in combination: a master microprocessor controller having memory for storing an operational program controlling said copier/duplicator, at least one active area controller, said active area controller being separate from said master controller, said active controller having a microprocessor and a memory storing an operational program for controlling at least one of said copier/ duplicator operating components, and at least one passive area controller for controlling another of said copier/duplicator components in response to control data from said master controller, said active and passive area controllers each having ports for transmitting data

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (20)

**WARNING** start of CLMS field may overlap end of DESC **. Process Controller 12 The area process controller 12 (PCR) is an active area controller and contains an area microprocessor 1600. The process controller cooperates with the master microprocessor in providing process control of various devices within the copier/duplicator. The process controller may be located in the power supply unit and is utilized for all A/D conversions, control of the developer unit (ADC control) electrometer, high voltage corotron outputs, lamp outputs and various developer outputs including the tdner dispenser motor. The process controller also provides D/A conversions in order to generate the needed analog signals to control various voltages and currents. The PCR may be incorporated in a closed loop system. In particular, analog data is digitized and processed either in the PCR microprocessor or in the master microprocessor. The processed data is subsequently converted into analog form via the D/A converters in the PCR. The analog data is then applied to control the very devices which were sensed thus completing the closed loop control. Other devices may, of course, be operated in open loop control systems. FIGURE 19 illustrates the process control area microprocessor 1600 and its interconnection to the various output and input ports. A letter "M" is utilized as a prefix to the OP or IP port designation to indicate a master input or output port. For example, the master output port 5, MOP5, is an input port 5, IPS, with respect to the area processor 1600. Master/PCR Software Communication FIGURE 20 shows a flow chart for the PCR communication with the master unit. The attention flag is set when the master loads information into the command and data ports. The PCR reads the data byte first and then reads the command byte following which the attention flip flop is reset. The command and data bytes are added together and echoed to the master for a communication error check. Upon receipt of an acknowledge command from the master, the instruction is executed by the PCR. The master may command the PCR to perform an A/D reading or to read and store a setpoint for the internal RAM of the area microprocessor. The digital value of the setpoint is converted into an analog signal to provide appropriate analog voltage or current control. The PCR periodically checks analog voltages or currents, compares their value to the setpoint value and provides new data for the output registers if required (with subsequent D/A conversion) to maintain the setpoint value. The PCR also provides digital output signals to turn on and off device power and voltages. The master also transmits acknowledge signals and " OK to send " signals to the PCR. The PCR may communicate to the master by providing three basic responses: the A/D reading response (the digital value of the analog signal requested), a fault code response (indicating which of a plurality of circuit boards has a fault therein), and the communications response (the echo sum of the data and command bytes). When the master communicates to the PCR for a A/D reading, the master may designate which of three separate filter techniques should be employed. The PCR will then sample the analog values, convert them to digital form and provide the appropriate filtering requested, namely, the pitch event filtering, the noisey signal filtering and the fast read and negative peak filtering. The pitch event filtering is essentially a sum of eight separate readings; the noisey signal filtering is essentially the sum of sixteen separate readings; and the fast reading or negative peak filtering is a single analog reading. The master unit may also specify the range utilized in the A/D and D/A conversions. A 1X range corresponds to a 32 mv/bit conversion factor while a luX range corresponds to a 3.2 mv/bit factor. The 1X range of course has a very large dynamic range (08 volts) as compared to the 10X dynamic range (e0.8 volts). WHAT WE CLAIM IS:

1. A control system for a copier/duplicator having a plurality of operating components, comprising in combination: a master microprocessor controller having memory for storing an operational program controlling said copier/duplicator, at least one active area controller, said active area controller being separate from said master controller, said active controller having a microprocessor and a memory storing an operational program for controlling at least one of said copier/ duplicator operating components, and at least one passive area controller for controlling another of said copier/duplicator components in response to control data from said master controller, said active and passive area controllers each having ports for transmitting data

to and receiving data from said master controller upon command of said master controller.

2. A control system as recited in Claim 1 wherein said area controllers each include means for sensing the condition of the operating components controlled by said controllers and transmitting the data obtained back to the said master controller.

3. A control system according to claims 1 or 2 wherein said master controller comprises: a command register for storing an address corresponding to an area controller desired to be selected for transmission of an output data wuld, an output data register for storing said output data word, an output data register for storing input data from said selected area controller, means for transmitting said output data word from said output data register to said selected area controller, and means for receiving said input data from said selected area controller in said input data register.

4. A control system as recited in Claim 3 wherein said master controller includes a clock generator for generating clock signals and means for transmitting said clock signals to each of said area controllers for synchronizing said area controllers with said master controller.

5. A control system according to any of the preceeding Claims, said area controllers each including: means for receiving command words from said master controller, and means for providing input data to said master controller in response to said command words, said area controllers having selected input data bits ORed together to provide cer- tain input data, said area controllers simultaneously transmitting said selected input data bits to said master controller in response to a predetermined command word from said master controller.

6. A control system as recited in Claim 5 wherein said master controller further comprises means for transmitting an address to an identified individual area controller, each of said area controllers having decode logic means for decoding said address.

7. The control system according to any of the preceeding claims, including an address and data bus from said master controller, interface means connected to said address and data bus including: means connected to said address bus for storing a command byte, means connected to said data bus for storing an output data byte, means for transmitting said command and output data bytes along a first communication path to said area controllers; means for storing an input data byte, said input data storing means being connected to receive data along a second communication path from said area controllers and connected for providing said received data to said data bus of said master controller, and means for generating a simplex bit in said command byte for initiating a simplex mode of operation in a selected area controller wherein data is read by said master controller from said selected area controller or for generating a duplex bit for initiating a duplex mode of operation in a selected area controller wherein data is both read by said master controller from said selected area controller and written into said selected area controller by said master controller.

8. The control system as recited in Claim 7 wherein said duplex command bit from said master unit utilizes said data bus and a common dedicated address for both said read and said write commands, and said interface means comprises means for decoding said address to provide a first function associated with said read command and a second, different function, associated with said write command.

9. The control system as recited in Claim 8, wherein said first function includes reading from said input byte storing means and said second function includes writing into said output byte storing means.

10. A control system according to Claim any of the preceeding claims including a fiber-optic communication path between said master controller and said area controllers.

11. A copier/duplicator including the control system as recited in Claim 1 wherein said copier/duplicator includes: a document exposure station, a recirculating document handler including document transport means for trans porting original documents to and from said document exposure station, and drive means for said document transport means, one of said area controllers controlling said drive means to control the speed of said transport means.

12. A copier/duplicator as recited in Claim 11 wherein said one area controller comprises a servo control circuit for controling said drive means speed.

13. A copier/duplicator including the control system as recited in Claim 1, or a copier/duplicator according to Claim 11 wherein said copier/duplicator includes: photoreceptor means for receiving images of said documents, dniiment imagine means including a platen for supporting documents to be imaged, platen scanning means, anu means Ior variabiy magnifying the document image onto said photoreceptor means, another of said area controllers controlling the length of scan of said scanning means for each variable magnification.

14. A copier/duplicator as recited in Claim 13 wherein said other area controller further controls the speed of scanning of said platen scanning means.

15. A copier/duplicator as recited in Claim 14 wherein said other area controller comprises a servo circuit for controlling said scanning speed.

16. A copier/duplicator including the control system according to Claim 1 wherein said copier/duplicator comprises: a document exposure station, a recirculating document handler having means for transporting said original documents to and from said document exposure station, a platen for supporting documents to be imaged, platen scanning means, drive means for said document transporting means and said platen scanning means, photoreceptor means for receiving an image of said document from either said document exposure station or said platen, and means for variably magnifying said document image onto said photoreceptor means, said active area controllers including a servo area controller for controlling said drive means to control the speed of said document transporting means and the speed of said scanning means, said servo controller including servo controlled circuit means, and a process area controller for controlling at least one of said other devices.

17. A copier/duplicator as recited in Claim 16 wherein said servo controlled cir c'iit means comprises tachometer means for generating an analog signal indicative of the operating speed of said document transporting means and said platen scanning means.

18. A copier/duplicator recited in Claim 17 wherein said servo controller includes analog-to-digital conversion means for receiving said analog signal and converting said analog signal to digital signals.

19. A copier/duplicator as recited in Claim 16 wherein said servo controller includes means for controlling the length of scan of said platen scanning means for each variable magnification selected.

20. A control system substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.