GB1600627A - Apparatus and method for data transfer - Google Patents

Description

(54) APPARATUS AND METHOD FOR DATA TRANSFER (71) We, HONEYWELL INFOR MATION SYSTEMS INC., a Corporation organised and existing under the laws of the State of Delaware, United States of America of 200 Smith Street, Waitham, Massachusetts 02154, United States of America, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed to be particularly described in any by the following statement: the present invention relates to data transfer in computers in which data may be stored in two different formats.

Because of the present structure of the data processing industry, manufacturers wishing to sell their equipment can do so only if such equipment is compatible with that of the dominant manufacturer in the industry. These conditions apply, for example, where the sale is directed to replacing the dominant manufacturer's equipment at the prospective customer's site. Thus, it is important that the prospective customer not be forced to reprogram in order to accommodate the replacement equipment, or to make other changes not otherwise required. Even if it is not a replacement sale, it may still be necessary for the equipment offered for sale to be compatible with other customer equipment procured from the dominant company.

Under these conditions, compatibility is often achieved by the smaller manufacturer through the slavish imitation of the dominant company's equipment, at least of those portions that bear on compatibility.

On the other hand, where the smaller manufacturer independently develops data processing equipment, the aforesaid market conditions dictate that such equipment incorporate features that make it compatible with that of the dominant company. Frequently, such compatibility is achieved only at the expense of equipment throughput, or of other factors by which equipment performance is measured, thereby making such equipment less competitive.

The present invention applies to a data processing system wherein, for reasons unrelated to the invention, the main memory stores data in a form incompatible with that commonly employed in the equipment of the dominant company in the industry. To the extent that such data was originally generated in the aforesaid commonly employed form, processing of the data read out from the subject memory, such as arithmetic manipulation, must be carried out in the original form.

More specifically, data words originally employing data characters in 8-bit form are stored in 9-bit form in the main memory of applicants' data processing system, using a binary 0 in the first bit position of each character. When such data is recalled for arithmetic processing, e.g. by transfer from memory to a receiving register, it must be restored to 8-bit form. Conventionally, the transfer and attendant conversion of data is carried out by appropriately programming the central processing unit of the data processing system. To do so however, as many as half a dozen separate instructions may be required since the CPU ordinarily is not specifically designed to carry out such an operation other than through its generalized capabilities. Thus, where frequent transfers are required, the throughput of the system is adversely affected and whatever competitive advantage may otherwise be incorporated in the equipment, may be lost.

Accordingly the present invention provides a computer system comprising: a memory in which data is stored as words of 1 or more bytes, each byte being stored in a 9-bit location, and each word consisting of either 9-bit bytes or 8-bit bytes each of which is extended by a filler 0 in the most significant position for storage in the memory; and data transfer means responsive to a transfer instruction specifying the byte type of the word to transfer a word from the memory to receiving register means, comprising: an intermediate register having right hand and left-hand portions and into which the bytes of the word are transferred with right justification from the memory, means which alternately (i) right-end around shift the intermediate register by 8 bits and (ii) right shift the right hand portion of the intermediate rigister by 1 bit for each byte of the word if the bytes are 8-bit bytes, and means which transfer the word from the intermediate register to the receiving register means.

A computer system in accordance with the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 shows the format of a transfer instruction used in the system; Figs. 2A and 2B together are a flow chart showing the operation of the system; Figs. 3A and 3B show the state of the intermediate register of the system at various stages of operation; and Fig. 4 shows the format of the transfer instruction in more detail.

With reference now to the drawings, Fig.

1 illustrates a single transfer instruction consisting of two 36-bit words, i.e. an instruction word 10 and a descriptor word 12. The format used, which governs the size of the double word and the fields within each word, is determined by factors unrelated to the present invention. Only those fields which are used for instructions are illustrated in Fig. 1, the bit positions of the pertinent fields being numbered in the drawing. Some of the fields are variable in size and the bit positions for those cases have been omitted since they will vary with the particular situation.

The contents of bit positions 14--17 of the instruction word contain the RECR field which identifies the chosen receiving register to which the data is to be transferred. Where a data word or selected characters thereof are to be transferred, such transfer is made, in accordance with the instruction, to one of a pair of receiving registers designated as A register and as Q register respectively. Where only the contents of certain specified bit positions are to be transferred, the receiving register consists of one of eight index registers identified as X0-X7, which is again specified by the transfer instruction. The specific receiving register to which the information is transferred is chosen in accordance with the requirements of data processing following the transfer of the data to the receiving register.

Bit positions 18-27 of the instruction word contain the OP CODE field which identifies the nature of the operation to be carried out in accordance with the instruction. In the present case, the operation called for is to move data from main memory to a receiving register.

In the descriptor word, the Y field contains the address of the operand in the main memory. The length of the Y field will vary in accordance with the particular situation. The C field identifies the first character that is to be transferred. The SE field in bit position 21 is the "signextended" field which determines the contents of certain bit positions subsequent to their being vacated pursuant to the manipulation of data characters during transfer.

The B field in bit position 22 of the descriptor word determines whether or not the 9-bit data characters in memory are to be transferred to the selected receiving register without being converted. Finally, the L field specifies the total number of characters which are to be moved in a single transfer to the receiving register.

It is important to note that in the present system the instruction illustrated in Fig. 1 exists as firmware, i.e. as standard logic circuits in read-only memory which are permanently set, or wired, in accordance with the instruction and descriptor words respectively. In essence, then, the pre-set logic circuits of the read-only memory constitute and function as the equivalent of, a hard-wired control circuit which manipulates the overall circuit to carry out the transfer instruction. Our system consists of apparatus and a method for effecting the desired data transfer under the control of the aforesaid firmware, as will become apparent from the discussion below.

Figs. 2A and 2B together illustrate in flow chart form the operation of the system.

As will become clear from the explanation below, the transfer of data from the main memory to the chosen receiving register, and the attendant conversion of the date from a first to a second form, involves the use of an intermediate register (IMR) which temporarily stores and is used to manipulate the data to be transferred.

Figs. 3A and 3B illustrate the contents of the IMR for the respective stages following -the steps shown on the flow chart of Fig. 2.

As will be seen from Fig. 2, a START signal, or the equivalent, is generated when it is desired to move data from the main memory to the IMR. The particular operation to be carried out is specified in the OP CODE field of the instruction, as shown in Fig. 1, in bit positions 18-27 of the instruction word 10.

In Fig. 3, the respective steps of the operation during which changes occur in the contents of the intermediate register are designated by numbers along the left hand margin. Thus, Step (0) illustrates the contents of the IMR following the move indicated by block 14 in Fig. 2A. As shown, the result of the move from memory is to place a double data word consisting of 8 characters into the IMR. The respective characters so moved are designated by the letters Q. R, S, T, U, V, W, X in the drawings. The subscript (0--8) beneath each letter in Step (0) denotes a 9-bit character or byte, the first bit being designated as bit 0 and the last bit being designated as bit 8.

As illustrated in Step (0) of Fig. 3A, upon the completion of the move of the double word from the main memory location addressed by the field Y of the instruction, a total of 8 characters, each consisting of 9 bits, is disposed in the IMR. As previously explained, for reasons unrelated to the present system, each 9-bit character carries a 0 in the first bit position which must be removed if the character is to be used for such purposes as binary arithmetic manipulation.

For purposes of an illustrative example, it will be assumed that YC=2 and L=3. Since Y designates the address in memory of the double word to be transferred, and C designates the starting position of successive characters within the word to be transferred, YC=2 indicates that the portion of the double data word to be transferred to the receiving register will begin with character 2, i.e. the third character on character S. L=3 indicates that a total of 3 characters are to be transferred, i.e.

characters S, T and U.

As seen from block 16 in Fig. 2A, the next step calls for right shifting the IMR by 9[8-(YC+L)] bit positions. For the values assumed, this becomes a right shift of 27 bit positions so that only the characters Q, R, S, T and U are retained in the IMR, as seen from Step (1). The designation "e" in Fig. 3 indicates the bit positions that have been emptied, the contents of which are meaningless and ignored.

Next, the status of the B field is determined, as indicated by the decision box 18 in Fig. 2A. As will be seen from Fig.

1, the B field contains only a single bit position. The contents of this position determined whether or not the selected data characters are to be transferred in their original 9-bit form or in 8-bit form.

As shown in Fig. 2A, if B=l, the IMR is manipulated in a manner different from that when B=0. This is illustrated by blocks 20 and 22 respectively, as well as by the corresponding Steps (2) and (5) respectively in Fig. 3. Step (2) has been expanded to show certain sub-steps in order to illustrate the operation performed. When B=l, the IMR is at first right-end-around shifted by 8 bit positions, Step (2a). The result of right shifting is to take the contents of the last 8 bits of character U, located in bit positions 28-35 of the RH register portion, and to shift them out serially in reverse order from the RH portion into bit positions 07 of the LH portion of the IMR. The contents of the latter bit positions are properly designated Us 8, indicative of the fact that U0, i.e. bit 0 of the character U, is not present in the LH register portion. Instead, U0 is shifted to bit position 35 of the RH portion and resides there at the conclusion of Step (2a).

As shown by block 20, the right-endaround shift of the entire IMR is followed by a right hand shift of the RH portion only by 1 bit position, Step (2b). This is effective to dispose of bit U0 which, as the first bit of the 9-bit character U, contained a binary 0.

Further, each of characters Q, R, S and T respectively has now moved a total of 9 bit positions to the right over the position each occupied upon the completion of Step (1).

As will be seen from block 20 in Fig. 2A, the above-described step, consisting of the two operations discussed, is repeated (L-l) times; For the assumed example where L=3, it is. repeated twice again. Upon the completion of the iteration of this step, the status of the IMR is as shown in Step (2finial) of Fig. 3A. As indicated by the subscript (1--8) of characters S, T and U respectively, each character now contains only the last 8 bits of the erstwhile 9-bit character. The first bit of each character, i.e. the initial binary 0, has been eliminated by the preceding operation and the resulting bit position spaces between the characters have been closed. Thus, the 8-bit characters S, T and U occupy only the bit positions 23 in the LH register portion. The remaining bit positions of the LH portion are empty upon the conclusion of Step (2), as indicated in the drawing. Further, bit positions 0--17 of the RH register portion are now empty, while the 9-bit characters Q and R occupy the remainder of the RH portion.

If the sampling of the B field by the decision means 18 indicates that Bfl, the RH register portion is left shifted by 9(4--L) bit positions, as indicated by block 22. In the assumed example, this results in a left shift in the RH portion of 9 bit positions and bit positions 27-35 are emptied, as illustrated by Step (5) in Fig. 3B. Since only the RH register portion is left shifted, the aforesaid operation in the removal of character R. The contents of the LH portion of the IMR remain unaffected by this operation.

Following Steps (2) and (5) respectively, the SE field is sampled as illustrated at 24 and 26 respectively in Fig. 2A. If SE=I, the action indicated by block 28 of Fig. 2A is carried out. Specifically, the LH portion of the IMR is right shifted by [9(L)+Ll bit positions. The first bit of the last character shifted by the last shift, i.e. bit Sl, is extended to the vacated bit positions of the LH register portion.

The operation is illustrated by Step (3). In the assumed example, the contents of the LH register portion are right shifted by 12 bit positions, such that the 8-bit characters S, T and U now appear in right justified position in the LH register portion. Bit positions 0--11, which are vacated by the aforesaid shifting, are then each filled with the contents of Sl, i.e. with the first bit of the character S. As will be apparent from block 30 in Fig. 2A, as well as from Step (4) in Fig.

3A, the shift operation is the same if Sex .

In the latter case, however, bit positions l 1 of the LH register portion are filled with 0's instead.

Similarly, following Step (5), the SE field is sampled by decision box 26. As indicated by block 34, if So=1, the RH register portion is right shifted by 9(P-L) bit positions. The first bit of the last character shifted, i.e. bit S0, is extended to the bit positions 08 of the RH register portion which are vacated by the last-recited shift.

Step (7) in Fig. 3B illustrates the state of IMR following this operation. If SEÍ, the operation indicated by block 32 is carried out. Here again the RH portion is right shifted by 9(4--L) bit positions, but the vacated bit positions are filled with 0's. Step (6) illustrates the latter operation.

Fig. 2B is a continuation at the indicated points (A) and (B) of the flow chart of Fig.

2A. Upon the conclusion of Steps (3), (4), (6) and (7) respectively, the RECR field is sampled, for the presence of data indicative of a desired transfer to the A or Q registers respectively, at 36 and 38 respectively in Fig. 2B.

Following the sampling of the RECR field by decision box 36, the L field is sampled by decision boxes 40 and 42 respectively. If RECR=A or Q, decision box 40 determines the truth of the statement lsL14. As indicated by block 44, if the foregoing statement is true, as would be the case in the assumed example if no fault had occurred, the contents of the LH register portion, as they appear in Step (4), are transferred to receiving register A or Q, depending on the instruction. If the statement 1 < L14 is false, a fault is indicated as shown at 46 in Fig. 2B.

If the sampling by decision box 36 indicates that RECR A or Q, decision box 42 samples the L field and determines if the statement 11L12 is true. The latter condition, although not applicable to the assumed example, is discussed here in order to fully illustrate the system. As indicated by block 46, if the statement is true, the contents of bit positions 18 to 35 of the LH register portion, as they appear in Step (4), are transferred to the chosen index register.

If, on the other hand, the statement l < Lc2 is false, a fault is indicated, as shown by block 48 in Fig. 2B.

Similarly, in response to the sampling of the RECR field by decision box 38, a pair of further decision boxes 50 and 52 respectively, sample the L field. If RECR=A or Q and the statement 1 < L < 4 is true, the contents of the RH register portion, as they appear in Step (6), are transferred to the selected receiving register A or A in accordance with the operation indicated by block 54. If the statement l < L < 4 is false, a fault is indicated. as illustrated by block 56.

If decision box 38 indicates that RECR*A or Q, and the statement l < L < 2 is true, the contents of bit positions 18 to 35 of the RH register portion, as they appear in Step (6), are transferred to the chosen index register in accordance with the operation indicated by block 58. If the statement I < L < 2 is false, a fault is indicated as illustrated at 60 in Fig. 2B.

From the foregoing discussion it will be apparent that the present system affords the opportunity of using a single instruction to effect a transfer of data from the memory portion of a computer system to a receiving register, while simultaneously converting from the form in which the data is stored in memory to a form that is usable for subsequent arithmetic manipulation. The instruction itself may be stored as firmware, i.e. in hardware form as a set of microinstructions. For example, the microinstructions may be embedded in the logic circuits of a read-only memory which generate appropriate signals to carry out the various operations.

The present system lends itself to being carried out in a variety of different embodiments. Specifically using the control unit section of a general purpose computer system, the system illustrated in Fig. 2 may be implemented in a variety of ways by means of discrete microinstructions. From this, it may be desirable for the transfer instruction of Fig. I to be elaborated somewhat, as shown in Fig. 4. The instruction word 10 incorporates a field I in bit position 28 and a field MF in bit positions 29 to 35. The I field may contain an inhibit bit which, when present, inhibits interrupts of the operation at the conclusion of the transfer of the desired data from memory to the receiving register. The MF field specifies that address modification, if any, is to be performed on the address carried by the descriptor word.

The descriptor word 12 carries an address "y" which specifies the address of the operand in the main memory. For an indirect word,, the "y" field specifies the address of the operand descriptor in main memory which may, for example, identify the final memory location from which the desired data is to be transferred. The Y of Fig. I refers to the final memory address after all address modifications that are to occur have been performed.

AR refers to the address register and is properly part of the "y" address. If the modification field MF so directs, AR will select one of the 8 address registers.

WHAT WE CLAIM IS: 1. A comptuter system comprising: a memory in which data is stored as words of 1 or more bytes, each byte being stored in a 9-bit location, and each word consisting of either 9-bit bytes or 8-bit bytes each of which is extended by a filler 0 in the most significant position for storage in the memory; and data transfer means responsive to a transfer instruction specifying the byte type of the word to transfer a word from the memory to receiving register means, comprising: an intermediate register having right hand and left-hand portions and into which the bytes of the word are transferred with right justification from the memory, means which alternately (i) right-end around shift the intermediate register by 8 bits and (ii) right shift the right hand portion of the intermediate register by 1 bit for each byte of the word if the bytes are 8-bit bytes, and means which transfer the word from the intermediate register to the receiving register means.

2. A computer system according to claim 1 wherein in data transfer means include means which right justify the left-hand portion of the intermediate register after the right-around-shifting and right shifting if the bytes are 8-bit bytes.

3. A computer system according to any previous claim wherein the data transfer means include sign extension means responsive to a sign extension bit in the transfer instruction to fill any vacant bit positions on the left of the word in the intermediate register with the extreme lefthand bit of the word, after the right-aroundshifting and right shifting if the bytes are 8bit bytes.

4. A computer system according to any previous claim, wherein the receiving register means comprises a plurality of registers not all of the same length and the transfer instruction specifies which of those registers is to receive the word, and including means which check that the length of word is not greater than the length of the specified register.

5. A computer system substantially as herein described with reference to the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (5)

**WARNING** start of CLMS field may overlap end of DESC **. "y" which specifies the address of the operand in the main memory. For an indirect word,, the "y" field specifies the address of the operand descriptor in main memory which may, for example, identify the final memory location from which the desired data is to be transferred. The Y of Fig. I refers to the final memory address after all address modifications that are to occur have been performed. AR refers to the address register and is properly part of the "y" address. If the modification field MF so directs, AR will select one of the 8 address registers. WHAT WE CLAIM IS:

1. A comptuter system comprising: a memory in which data is stored as words of 1 or more bytes, each byte being stored in a 9-bit location, and each word consisting of either 9-bit bytes or 8-bit bytes each of which is extended by a filler 0 in the most significant position for storage in the memory; and data transfer means responsive to a transfer instruction specifying the byte type of the word to transfer a word from the memory to receiving register means, comprising: an intermediate register having right hand and left-hand portions and into which the bytes of the word are transferred with right justification from the memory, means which alternately (i) right-end around shift the intermediate register by 8 bits and (ii) right shift the right hand portion of the intermediate register by 1 bit for each byte of the word if the bytes are 8-bit bytes, and means which transfer the word from the intermediate register to the receiving register means.

2. A computer system according to claim 1 wherein in data transfer means include means which right justify the left-hand portion of the intermediate register after the right-around-shifting and right shifting if the bytes are 8-bit bytes.

3. A computer system according to any previous claim wherein the data transfer means include sign extension means responsive to a sign extension bit in the transfer instruction to fill any vacant bit positions on the left of the word in the intermediate register with the extreme lefthand bit of the word, after the right-aroundshifting and right shifting if the bytes are 8bit bytes.

4. A computer system according to any previous claim, wherein the receiving register means comprises a plurality of registers not all of the same length and the transfer instruction specifies which of those registers is to receive the word, and including means which check that the length of word is not greater than the length of the specified register.

5. A computer system substantially as herein described with reference to the accompanying drawings.