GB1450457A - Telecommunication exchange systems - Google Patents

Abstract

1450457 Automatic exchange systems PLESSEY CO Ltd 31 Dec 1974 [2 Jan 1974] 00010/74 Heading H4K In a T-S-T time division switching network, a path checking procedure is provided whereby check words are inserted into a receive time stage store and their arrival at a transmit time stage store is notified to a central control. Fig. 1 shows a standard T-S-T network for interconnecting 4 wire TDM highway pairs such as JAI and JX1 and Fig. 2 shows in schematic form the additional circuitry which is associated with each highway pair junction equipment for the purposes of carrying out the path checking procedure, Figs. 4, 5, 7 and 8 (not shown) illustrating this circuitry in detail. When a call is to be set up the central control CC nominates one of the junction equipments, e.g. JEAI to be the "master" and the other, e.g. that associated with highway pair JX1, to be the "slave". Referring to Fig. 2, a path check is initiated by the super-highway controller, associated with the "master" junction equipment, which sends a time addressed message to the receive equipment RTS over leads PCS, this message passing through the path check control store updating logic in synchronism with the scanning of the related incoming channel, e.g. on highway pair JA1 to change the stored state of that channel in a 32 word R.A.M. path check control store from S0 to S1 (the states S0-S7 are defined in Fig. 3, not shown), there being 32 channels on each incoming highway. The "master" receive equipment then causes on successive scans changes between states S1 and S2 in the check control store so activating the pattern injection logic to cause "odd" bit i.e. 10101010 and even bit, i.e. 01010101 patterns to be injected into the selected receive channel during alternate junction frames. Concurrently the "slave" junction equipment receives a message to set the corresponding location of its check control store to state S7, this location corresponding to an outgoing channel, e.g. on highway pair JX1. The slave transmit equipment TTS then searches for the odd bit pattern injected by the master receive equipment using the path check pattern extraction logic. When the odd bit pattern has been received and confirmed the location of the slave check control store is set to S6 and the even bit pattern is searched for. On detection thereof the slave check control store location is set to S5 to initiate the injection of the. odd and even bit patterns into the return path through the network. At the master transmit equipment, the detection of the pattern transmitted from the slave receive equipment sets the master check control store location to S3 to terminate the pattern injection at the master end. Subsequently the termination of the receipt of the check pattern causes the slave check control store location to be set to S0 thereby stopping the pattern injection at the slave junction equipment. The termination of the check pattern is then detected at the master junction equipment and the appropriate check control store location switches to S4. A message is then passed over leads CPU to central control CC to indicate that a path has been set up and successfully checked. The master control store location is then reset to S0. Such a check is performed each time a path is set up through the network. The detailed arrangement includes means for compensating for clock rate differences between the highway pairs and. the exchange so as to enable the test patterns to be injected into the correct time slots.