GB1448198A - Coin counting machines - Google Patents

Abstract

1448198 Counting coins CONTROL SYSTEMS Ltd 22 Nov 1973 [23 Nov 1972] 54186/72 Heading G4D A coin counting apparatus has an. inclined path 1 down which coins of various denominations are slid; an array of photo-electric detectors 6 arranged to be selectively obscured by coins of different sizes ; and a logic circuit (Figs. 4A+4B) arranged to increment a counter 25a-25d by increments representative of values of the coins as indicated by their size. The detectors 6 may include photo-cells 8 and light guides 7; they are illuminated by a parallel beam from source 5. Each photo-cell 8 is coupled by an inverter 14 to a NAND gate 15; the lowest denomination cell 8 is coupled to the second input of each NAND gate 15. Each gate 15 provides an output, which sets a bistable 16, only if its cell and the cell of the lowest denomination is obscured; this reduces the sensitivity of the apparatus to random shadows. One output of each bi-stable 16 is connected to a respective NAND gate 18; the opposite output of each bi-stable is connected to a second input of the NAND gate 18 of the next lowest denomination; a third input of each NAND gate 18 is energized by a bi-stable 17 when the lowest denomination cell is uncovered; thus only the highest NAND gate, i.e. that corresponding to the coin, is enabled. The NAND gates 18 are connected via coding trees to a set of NAND gates 19 arranged in groups of three per decade: the lowest group represent 1, 2 and 4 tenths of units, the next 1, 2 and 4 units, 1,2 and 4 tens of units and so on. The outputs of the groups are parallelled into lines a, b, c feeding a full adder circuit 21. The decade groups are strobed by pulses 23 on five outputs 1-5 of an eight phase clock 26, 28, 29. A counter consists of four eight bit recycling shift registers 25a-25d which are shifted continuously by the clock; the corresponding stages of the registers represent the decades of the count in 1-2-4-8 code and due to the shifting the individual decades are presented one after the other to lines 25e in phase with the clock. The new value for that decade, on lines a, b, c is added to the current total on lines 25e by the adder 21 and returned to the shift registers which thus in the course of five clock pulses accumulate the value of the coin coded in gates 19. The sixth clock pulse resets the bi-stables 16 and the eighth enables gate 17a which readies the circuit for the next coin. The coin path is such that only one coin can be presented during one complete clock cycle. The values on lines 25e are decoded at 33 and applied to seven segment displays.