GB1307538A - Semiconductor structures and methods for forming such structures - Google Patents

Semiconductor structures and methods for forming such structures

Info

Publication number
GB1307538A
GB1307538A GB2845070A GB2845070A GB1307538A GB 1307538 A GB1307538 A GB 1307538A GB 2845070 A GB2845070 A GB 2845070A GB 2845070 A GB2845070 A GB 2845070A GB 1307538 A GB1307538 A GB 1307538A
Authority
GB
United Kingdom
Prior art keywords
region
layer
conductivity type
base
buried
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2845070A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1307538A publication Critical patent/GB1307538A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137Collector regions of BJTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/761PN junctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0112Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

1307538 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 12 June 1970 [30 June 1969] 28450/70 Heading H1K A semi-conductor structure to reduce isolation areas in integrated circuits comprises a substrate 10 of one conductivity type having a semi-conductor layer 23 of the same conductivity type on one surface, with a buried layer 15 of the opposite conductivity type adjacent the substrate surface and surrounded by a second buried region 21 of the one conductivity type. The layer 23 which may be epitaxially deposited has diffused within it an annular region 24 of the opposite conductivity type so as to reach down from the layer surface and contact the buried region 15, so enclosing a portion 25 of the layer 23. A second diffusion of the opposite conductivity type may be made within the enclosed portion 25 to form a region 26. Contacts e.g of aluminium may be made to regions 26, 25 and 24, the region 26 forming the emitter of a transistor, portion 25 the base, and regions 24 and 15 the collector. The second buried region 21 prevents inversion at the substrate-layer 23 interface. In an alternative embodiment, by suitable doping of the layer 23 during deposition, the out diffusion from region 15 causes a thin intrinsic region (31), step 12A, (not shown) to be formed in enclosed portion 25. Further doping of the same conductivity type as the layer is then required to form the base region. The double diffusion process, i.e. of the base and subsequently the emitter enables the thickness of the base to be accurately determined. An integrated structure using two complementary transistors, one being formed with a further region within region 26, is also described. The devices may be formed from a silicon substrate using photoresist techniques and arsenic, boron, gallium or phosphorus as dopants. In a reference to Specification 1,300,174, the emitter region 26 may be replaced by a Schottky-barrier junction.
GB2845070A 1969-06-30 1970-06-12 Semiconductor structures and methods for forming such structures Expired GB1307538A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US83780369A 1969-06-30 1969-06-30

Publications (1)

Publication Number Publication Date
GB1307538A true GB1307538A (en) 1973-02-21

Family

ID=25275477

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2845070A Expired GB1307538A (en) 1969-06-30 1970-06-12 Semiconductor structures and methods for forming such structures

Country Status (4)

Country Link
CA (1) CA992668A (en)
DE (1) DE2031533A1 (en)
FR (1) FR2048029A1 (en)
GB (1) GB1307538A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109979873A (en) * 2017-12-27 2019-07-05 无锡华润上华科技有限公司 Isolating device and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109979873A (en) * 2017-12-27 2019-07-05 无锡华润上华科技有限公司 Isolating device and preparation method thereof
CN109979873B (en) * 2017-12-27 2021-05-11 无锡华润上华科技有限公司 Isolation device and preparation method thereof

Also Published As

Publication number Publication date
FR2048029A1 (en) 1971-03-19
CA992668A (en) 1976-07-06
DE2031533A1 (en) 1971-02-18

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees