GB1191507A - Data Processing System having Improved Arithmetic Portion Therein. - Google Patents

Abstract

1,191,507. Data processing systems. GENERAL ELECTRIC CO. 12 Sept., 1967 [4 Oct., 1966 (2)], No. 41582/67. Heading G4A. In a data processing system including a memory for storing instruction words and data words and an arithmetic unit, the arithmetic unit includes a number of programme accessible registers for storing numbers having different significances and different instructions are available for handling the numbers according to said significances. In particular numbers are available in a variety of floating-point formats, the arrangement being such as to allow selective manipulation of the contents of these registers to achieve varying degrees of precision and flexibility in arithmetic operations, particularly division. As shown (Fig. 1), a memory 6 stores 36-bit words in a number of different floating point formats. Thus, each word may comprise an 8-bit exponent and a 28-bit mantissa or the exponents and mantissas may be stored in separate single words or the exponents may be stored in single words and the mantissa in double (adjacent) words. Data from the memory 6 may be passed by way of a switch 10 and an M-register 14 to a selected one or ones of the temporary storage registers 22, 30, 36, 40 and 56. Registers 22 (8-bits) and 30 (10-bits) are normally used for storing exponents and are associated with an adder 34 whereas registers 36, 40 and 56 (all of 72-bits) are normally used for storing mantissas and are associated with an adder 38. A counter 28 is provided for counting steps in iterative processes such as division. Instruction words, also received by way of switch 10, are retrieved from memory in pairs and passed to temporary storage register 78 for decoding by means 92, 97 and 99. Instructions are described in the Specification for accessing, manipulating (adding or dividing) and storing words representing numbers in any of the floating-point formats referred to above. Division.-Two divide instructions are provided in the first of which a dividend already loaded into registers 30 and 56 is divided by a divisor at an address specified by the address portion of the instruction (Fig. 2, not shown). In the second divide instruction, the operand already in registers 30, 56 is treated as divisor and the operand in memory as dividend. With both instructions the divide operation proper starts after normalization and with the dividend in registers 40, 30 and the divisor in registers 36, 22. If the dividend is not negative and the divisor positive, complementing of the necessary operands is effected. Division of the normalized mantissas is by repeated subtraction in adder 38 followed by shift with the G-counter 28 counting the number of iterations performed. If subtraction is successful, (carry signal SC o = 1) the output of the adder 38 is returned to the N register 40 (shifted left one position) but if subtraction is not successful (SC o = 0) the previous contents of N register 40 are merely shifted left by one position. The quotient is developed in register 56 and is complemented to provide the final result. The exponents are simply subtracted in adder 34 and complemented.