GB1047246A

GB1047246A -

Info

Publication number: GB1047246A
Authority: GB
Priority date: 1963-02-27

Abstract

1,047,246. Computer checking arrangemerits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 5, 1964 [Feb. 27, 1963; June 25, 1963], No. 4816/64. Heading G4A. Parity prediction circuits check the validity of an arithmetic operation on two operands and a carry input signal. In a first embodiment employing a binary parallel carry-predict adder split into groups, a first level carry predictor 5 (Fig. 2, not shown) predicts the group input carry C1 as a function of the previous groups, a second level carry predictor 6 predicts interorder carries as functions of operands A, B and group input carry C1, and these are summed with operands A, B, in a binary adder 7 to give a result in a register 4. Simultaneously with the carry predictions a three level parity predictor 11 predicts first tentative parities PP, gamma, #, alpha at 8, predicts second parities P, G at 9 and at a third level 10 predicts the result parity RP which is entered in the result register 4. The parities are calculated according to the equations: In a second embodiment groups of data are fed into a half-sum circuit 11 (Fig. la, not shown), the results of which are used in group carry look-ahead 15 and bit carry look-ahead 14 circuits and are checked in a half sum checker 16 which comprises a number of exclusive OR elements -which operate on the half sums and data parities to determine the validity of the word and also a number of OR elements to determine the validity of the group. A correct result is obtained even when a group is shifted relative to its parity provided a signal signifying this shift is included in the group validity circuit. In the half-sum circuit functions A, B (G1, G2, G3, G4) and A+B(P1, P2, P3, P4) are simultaneously determined and are subsequently used in the sum parity predictor 18 (Fig. 6, not shown), together with the input group carry. The predicted parity is compared with the parity found from the full sum circuit 12 (Fig. la) and parity generator 19 to register the validity of the result.