FR2893730B1 - Montage a detection des essais de manipulation - Google Patents

Montage a detection des essais de manipulation

Info

Publication number
FR2893730B1
FR2893730B1 FR0610060A FR0610060A FR2893730B1 FR 2893730 B1 FR2893730 B1 FR 2893730B1 FR 0610060 A FR0610060 A FR 0610060A FR 0610060 A FR0610060 A FR 0610060A FR 2893730 B1 FR2893730 B1 FR 2893730B1
Authority
FR
France
Prior art keywords
mounting detection
handling tests
tests
handling
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0610060A
Other languages
English (en)
Other versions
FR2893730A1 (fr
Inventor
Thomas Kunemund
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of FR2893730A1 publication Critical patent/FR2893730A1/fr
Application granted granted Critical
Publication of FR2893730B1 publication Critical patent/FR2893730B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
FR0610060A 2005-11-18 2006-11-17 Montage a detection des essais de manipulation Expired - Fee Related FR2893730B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102005055158A DE102005055158B4 (de) 2005-11-18 2005-11-18 Schaltungsanordnung mit einer Einrichtung zur Erkennung von Manipulationsversuchen und Verfahren zur Erkennung von Manipulationsversuchen bei einer Schaltungsanordnung

Publications (2)

Publication Number Publication Date
FR2893730A1 FR2893730A1 (fr) 2007-05-25
FR2893730B1 true FR2893730B1 (fr) 2010-10-01

Family

ID=37989443

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0610060A Expired - Fee Related FR2893730B1 (fr) 2005-11-18 2006-11-17 Montage a detection des essais de manipulation

Country Status (3)

Country Link
US (1) US7916517B2 (fr)
DE (1) DE102005055158B4 (fr)
FR (1) FR2893730B1 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101299602B1 (ko) * 2007-03-27 2013-08-26 삼성전자주식회사 리버스 엔지니어링을 보호하는 집적회로
US8102725B2 (en) * 2007-09-10 2012-01-24 Nxp B.V. Method for controlling a pre-charge process and a respective integrated circuit
FR2935059B1 (fr) 2008-08-12 2012-05-11 Groupe Des Ecoles De Telecommunications Get Ecole Nationale Superieure Des Telecommunications Enst Procede de detection d'anomalies dans un circuit de cryptographie protege par logique differentielle et circuit mettant en oeuvre un tel procede
DE102010045328A1 (de) * 2010-09-14 2012-03-15 Giesecke & Devrient Gmbh Portabler Datenträger
US9431353B2 (en) * 2014-04-09 2016-08-30 Infineon Technologies Ag Method for manufacturing a digital circuit and digital circuit
US9431398B2 (en) 2014-04-28 2016-08-30 Infineon Technologies Ag Semiconductor chip having a circuit with cross-coupled transistors to thwart reverse engineering
US9337156B2 (en) * 2014-04-09 2016-05-10 Infineon Technologies Ag Method for manufacturing a digital circuit and digital circuit
US9548737B1 (en) 2015-07-17 2017-01-17 Infineon Technologies Ag Method for manufacturing a digital circuit and digital circuit
US9496872B1 (en) * 2015-07-17 2016-11-15 Infineon Technologies Ag Method for manufacturing a digital circuit and digital circuit
JP6690238B2 (ja) * 2015-12-28 2020-04-28 富士通株式会社 電子回路、及び外的作用検出用ラッチ回路
DE102016008756B3 (de) * 2016-07-18 2017-08-31 Frank Schuhmacher DPA-resistentes Dual-Rail-Precharged-Flip-Flop mit Fehlererkennung
DE102017102037A1 (de) 2017-02-02 2018-08-02 Infineon Technologies Ag Physisch unklonbare funktionsschaltung
DE102019123555B4 (de) 2019-09-03 2022-12-01 Infineon Technologies Ag Physisch obfuskierter schaltkreis

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4328583A (en) * 1980-09-08 1982-05-04 Rockwell International Corporation Data bus fault detector
US4342112A (en) * 1980-09-08 1982-07-27 Rockwell International Corporation Error checking circuit
US5483542A (en) * 1993-01-28 1996-01-09 At&T Corp. Byte error rate test arrangement
US6253350B1 (en) * 1998-07-09 2001-06-26 International Business Machines Corporation Method and system for detecting errors within complementary logic circuits
US6225826B1 (en) * 1998-12-23 2001-05-01 Intel Corporation Single ended domino compatible dual function generator circuits
JP2003016785A (ja) * 2001-06-28 2003-01-17 Sharp Corp 半導体記憶装置およびそれを用いた情報機器

Also Published As

Publication number Publication date
US7916517B2 (en) 2011-03-29
US20070171099A1 (en) 2007-07-26
DE102005055158B4 (de) 2008-08-28
DE102005055158A1 (de) 2007-05-24
FR2893730A1 (fr) 2007-05-25

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