FR2852766A1 - Data word packet transferring method for use in cordless communication device, involves emptying memory word by word by running handshake protocol to alternately load two memories with packet and emptying latter memories - Google Patents

Data word packet transferring method for use in cordless communication device, involves emptying memory word by word by running handshake protocol to alternately load two memories with packet and emptying latter memories Download PDF

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Publication number
FR2852766A1
FR2852766A1 FR0303221A FR0303221A FR2852766A1 FR 2852766 A1 FR2852766 A1 FR 2852766A1 FR 0303221 A FR0303221 A FR 0303221A FR 0303221 A FR0303221 A FR 0303221A FR 2852766 A1 FR2852766 A1 FR 2852766A1
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France
Prior art keywords
word
packet
memory
data
data word
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FR0303221A
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French (fr)
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FR2852766B1 (en
Inventor
Ludovic Jeanne
Patrick Lopez
Patrick Fontaine
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Thomson Licensing SAS
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Thomson Licensing SAS
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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W28/00Network traffic or resource management
    • H04W28/02Traffic management, e.g. flow control or congestion control
    • H04W28/10Flow control between communication endpoints
    • H04W28/14Flow control between communication endpoints using intermediate storage

Abstract

The method involves loading data word packets coming from a micro-controller (1) in a FIFO memory (6). The memory is emptied word by word, little by little by running a handshake protocol to alternately load FIFO memories (8A, 8B) with a packet. The latter memories are alternately emptied in a three register memory where a micro-controller (2) recovers the data words. The data word of each data word packet is identified as a beginning of the packet in the memory (6). An independent claim is also included for an application specific integrated circuit serving as a communication interface in cordless communication equipment for a domestic communication network.

Description

The invention relates to a method for transferring word packets from

  data between two microcontrollers synchronized with each other by a protocol

  handshake, as well as a device implementing the method.

  Document US-5404374 discloses a specific application integrated circuit (ASIC) serving as a communication interface for wireless communication equipment in which packets of data words, which may have different lengths, are transferred by burst through two communication layers and in particular through a data link layer and a physical layer.

  A method is proposed for transferring data word packets between two microcontrollers as indicated above with which errors in the transfer of data words can be detected and treated easily.

  To this end, the invention relates to a method for transferring packets of data words between a transmission circuit and a reception circuit synchronized with one another by a handshake protocol, characterized in that it consists in loading the data word packets from the transmitter circuit in a first FIFO memory in which the first data word of each data word packet is identified as the start of the data word packet, to empty the first FIFO word memory by word, as the handshake protocol progresses, to alternately load one of two second FIFO memories with a packet of data words, and to alternately empty the second FIFO memories in a set of three memory registers in which the receiver circuit retrieves the data words, these three memory registers comprising a first memory register intended to receive the first data word in a data word packet, a second memory register for receiving the last data word in the data word packet and a third memory register for receiving the intermediate data words in the data word packet data.

  With the method according to the invention, the data word packets can be transferred by burst. In the case of a transfer fault of a data word packet contained in one of the two second FIFO memories, this badly transferred data word packet can be discarded by a simple switching of the alternating operation of the second memories FIFO.

  Furthermore, by using a specific sequence of sampling data words from the three memory registers, the receiving circuit is forced to follow a particular operation which can be easily monitored to detect a data word transfer error. The receiver and transmitter circuits are for example microcontrollers.

  The invention also relates to a circuit for implementing the method, as well as to a device comprising an implementation circuit. Other characteristics and advantages of the method according to the invention will become apparent on reading the following description of an example of implementation of the method according to the invention illustrated by the drawings.

  FIG. 1 schematically shows the architecture of an integrated circuit 15 serving as a communication interface between two microcontrollers through two communication layers.

  FIG. 2 shows in more detail the architecture of the FIFO memories for the implementation of the method according to the invention.

  In FIG. 1, two microcontrollers 1 and 2 implemented in an application-specific integrated circuit 20 for example, communicate in both directions through two communication layers, in this case a data link layer indicated by DLC and a physical layer indicated by PHY according to the OSI model.

  Blocks 3A and 3B designate the data transfer mechanism from micro-controller 1 to microcontroller 2 and blocks 4A and 4B designate the data transfer mechanism from microcontroller 2 to microcontroller 1.

  The architecture and operation of blocks 3A and 3B are analogous to the architecture and operation of blocks 4A and 4B.

  The communication between the two microcontrollers 1 and 2 through the blocks 3A-3B, 4A-4B is synchronized by a handshake mechanism known per se according to which an RTS signal is sent from the transmitting microcontroller to the micro- receiving controller when the first is ready to transmit D data and an RTR signal is sent from the receiving micro-controller to the transmitting micro35 controller when the first is ready to receive D data, this D data being transferred from the sending micro-controller to the receiving microcontroller during the coincidence of the two signals RTS and RTR.

  Figure 2 shows in more detail the architecture of blocks 3A and 3B.

  To transfer a data word packet comprising a certain number of data words to the microcontroller 2 operating as a receiver in the physical communication layer PHY, the microcontroller 1 operating as a transmitter writes the first word of the word packet data in a first memory register 5A and each subsequent word of the data word packet in a second memory register 5B.

  On each access to one of the memory registers 5A, 5B, the microcontroller 1 sends a write signal W / Ad and the address of the memory register 5A, 5B concerned to a control mechanism 5 responsible for taking samples in turn. the contents of the two registers 5A, 5B. Insofar as the first word of each packet contains information indicative of the length in words of the packet, the control mechanism 5 is able to detect a failure to access the registers 5A and 5B by the microcontroller 1 and in in the event of detection of a failure to access the memory registers 5A, 5B, it sends an error signal E1 to the microcontroller 1 to force the latter to start again sending the packet of data words.

  The control mechanism 5 picks up the data words, one by one, from the registers 5A and 5B in the order indicated above and stores them in a first FIFO memory 6 by associating with the first word of each packet of data words ( each word taken from the memory register 5A) information identifying the start of a packet of data words. This information is symbolized in FIG. 2 by the symbol 1 and can be coded by a bit on a column of the FIFO memory 6.

  In FIG. 2, there is shown in the FIFO memory 6 a set of data words here constituting two packets of data words, the first packet containing three data words indicated by MC2 and the second packet 30 containing four indicated data words by MC3.

  The FIFO memory 6 has a size sufficient to contain several packets of data words, the packets being able to be of different lengths. In this way, the microcontroller 1 can transfer bursts of data word packets into the FIFO memory 6.

  Although this is not shown in FIG. 2, the control mechanism 5 manages the filling of the FIFO memory 6 in relation to the write requests sent by the microcontroller 1 as the protocol for processing progresses. handshake symbolized by the RTS 5 and RTR signals exchanged between the mechanism 5 and a control mechanism 7 on the side of the physical communication layer PHY.

  The control mechanisms 5 and 7 can be implemented for example in the form of state machines.

  When a data word is transferred to the control mechanism 7 with the information indicating the start of the packet, it is stored in one of two second FIFO memories 8A, 8B operating alternately. Each second FIFO memory 8A, 8B has a size equal to the maximum length of a packet of data words. The two FIFO memories 8A, 8B are therefore loaded alternately by the control mechanism 7, the switching of the loading 15 from a second FIFO memory to the other being triggered by the detection in the mechanism, of control 7 of a word flagged as a start of data word packet.

  FIG. 2 also shows in the two FIFO memories 8A, 8B the words MC1 of a packet of data words and the single word MCO 20 of another packet of data words.

  When one of the two FIFO memories 8A, 8B is loaded, the receiver microcontroller 2 comes to read the data words successively in one of the three memory registers 7A, 7B, 7C in the following manner.

  The first word of a data word packet is read from the memory register 7A, the last word of the data word packet is read from the memory register 7C and the intermediate words of the data word packet are read from the memory register 7B.

  On each read access of one of the memory registers 7A, 7B, 7C, the microcontroller 2 sends a read signal R / Ad with the address of the memory register 7A-7C concerned to the control mechanism 7.

  As indicated above, insofar as the first word of each packet of data words is transferred to the control mechanism 7 with the information indicative of a packet start, the mechanism 7 is capable of alternating the loading of the memories FIFO 8A, 8B.

  Furthermore, since the first word stored in each FIFO memory 8A, 8B is the first word in a data word packet and contains information indicative of the length of the packet, it is presented each time by the mechanism 7 in the memory register 7A to the microcontroller 2. 5 The following words of the data word packet are presented in turn in the memory register 7B to the microcontroller and the last word of the data word packet is presented in the register 7C to the microcontroller 2. In the case where the control mechanism 7 detects a lack of access to the memory registers 7A-7C by the microcontroller 2, on the basis of the control of the signal for reading and R / Ad address, it sends an error signal E2 to the microcontroller 2.

  The current badly transferred data word packet can be discarded in the microcontroller 2 while a simple switching of the alternating operation of the second FIFO memories makes it possible to continue the process of transferring the data word packets.

  This mechanism for transferring bursts of variable length data word words can be applied to the transfer of commands between the two microcontrollers, each command being in the form of a data word packet.

Claims (6)

  1 / A method for transferring packets of data words between a transmitter circuit and a receiver circuit (1,2) synchronized with one another by a handshake protocol (RTS, RTR), characterized in that it comprises the steps : loading the data word packets coming from the transmitting circuit (1) into a first FIFO memory (6) in which the first data word of each data word packet is identified as being the start of the data word packet , emptying the first FIFO memory word by word, as the handshake protocol progresses, to alternately load one of two second FIFO memories (8A, 8B) with a packet of data words, for alternately emptying the second FIFO memories into a set of 15 three memory registers in which the receiver circuit (2) retrieves the data words, these three memory registers comprising a first memory register (7A) intended receiving the first data word of a data word packet, a second memory register (7B) intended to receive the last data word of the data word packet and a third memory register (7C) intended to receive the intermediate data words of the data word packet.
  2 / The method according to claim 1, in which the first FIFO memory (6) is loaded from two memory registers comprising a first memory register (5A) intended to receive the first word of a data word packet and a second memory register (5B) intended to receive the other words of the data word packet.
  3 / Integrated circuit for a specific application serving as a communication interface in wireless communication equipment for a home communication network, characterized in that it is designed for implementing the method according to one of claims 1 or 2.
  4 / Communication device characterized in that it comprises a transmitter circuit 35 (1) and a receiver circuit (2) synchronized by a handshake protocol, a first queue memory (6) for writing by the words transmitter circuit of a packet to be transmitted, the memory comprising means for identifying the first word of a packet, a second and third queue memory (8A, 8B), for alternately receiving packets extracted from the first queue memory.
  5 / Device according to claim 4, characterized in that it further comprises two memory locations (5A, 5B) intended respectively to contain the first word and the following words of a data packet to be transferred between the transmitter circuit (1 ) and the first queue memory (6). 10 6 / Device according to one of claims 4 or 5, characterized in that it further comprises three memory locations (7A, 7B, 7C) intended respectively to contain the first word, the intermediate words and the last word of a packet read in respectively one of the second and third queue memories (8A, 8B).
  7 / Device according to one of claims 4 to 6, characterized in that it further comprises two circuits (5, 7) for controlling the handshake protocol, respectively on the transmitter circuit and receiver circuit side. 20
FR0303221A 2003-03-17 2003-03-17 Method for safe transfer of packets of data words between two micro-controllers, circuit and device for implementing the same Expired - Fee Related FR2852766B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR0303221A FR2852766B1 (en) 2003-03-17 2003-03-17 Method for safe transfer of packets of data words between two micro-controllers, circuit and device for implementing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0303221A FR2852766B1 (en) 2003-03-17 2003-03-17 Method for safe transfer of packets of data words between two micro-controllers, circuit and device for implementing the same
PCT/EP2004/050252 WO2004084519A1 (en) 2003-03-17 2004-03-04 Method for the burst transmission of data word packets between two microcontrollers, and circuit and device for implementing same

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FR2852766A1 true FR2852766A1 (en) 2004-09-24
FR2852766B1 FR2852766B1 (en) 2005-07-01

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5151999A (en) * 1986-03-31 1992-09-29 Wang Laboratories, Inc. Serial communications controller for transfer of successive data frames with storage of supplemental data and word counts
US5473755A (en) * 1992-06-01 1995-12-05 Intel Corporation System for controlling data stream by changing fall through FIFO last cell state of first component whenever data read out of second component last latch
US5619544A (en) * 1994-06-03 1997-04-08 Texas Instruments Incorporated Universal asynchronous receive/transmit circuit with flow control
US6163539A (en) * 1998-04-28 2000-12-19 Pmc-Sierra Ltd. Firmware controlled transmit datapath for high-speed packet switches

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5151999A (en) * 1986-03-31 1992-09-29 Wang Laboratories, Inc. Serial communications controller for transfer of successive data frames with storage of supplemental data and word counts
US5473755A (en) * 1992-06-01 1995-12-05 Intel Corporation System for controlling data stream by changing fall through FIFO last cell state of first component whenever data read out of second component last latch
US5619544A (en) * 1994-06-03 1997-04-08 Texas Instruments Incorporated Universal asynchronous receive/transmit circuit with flow control
US6163539A (en) * 1998-04-28 2000-12-19 Pmc-Sierra Ltd. Firmware controlled transmit datapath for high-speed packet switches

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WO2004084519A1 (en) 2004-09-30

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