FR2797700A1 - Chip card reader has memory that can be readily programmed using an artificial chip card connected electrically to a personal computer for control of the programming procedure - Google Patents

Chip card reader has memory that can be readily programmed using an artificial chip card connected electrically to a personal computer for control of the programming procedure Download PDF

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Publication number
FR2797700A1
FR2797700A1 FR9910684A FR9910684A FR2797700A1 FR 2797700 A1 FR2797700 A1 FR 2797700A1 FR 9910684 A FR9910684 A FR 9910684A FR 9910684 A FR9910684 A FR 9910684A FR 2797700 A1 FR2797700 A1 FR 2797700A1
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Prior art keywords
gt
lt
microprocessor
memory
card
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FR9910684A
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French (fr)
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FR2797700B1 (en
Inventor
Ludovic Ruat
Olivier Ferrand
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STMicroelectronics SA
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STMicroelectronics SA
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Classifications

    • GPHYSICS
    • G07CHECKING-DEVICES
    • G07FCOIN-FREED OR LIKE APPARATUS
    • G07F7/00Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/10Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
    • G07F7/1008Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06KRECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06KRECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/0013Methods or arrangements for sensing record carriers, e.g. for reading patterns by galvanic contacts, e.g. card connectors for ISO-7816 compliant smart cards or memory cards, e.g. SD card readers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06KRECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/0013Methods or arrangements for sensing record carriers, e.g. for reading patterns by galvanic contacts, e.g. card connectors for ISO-7816 compliant smart cards or memory cards, e.g. SD card readers
    • G06K7/0056Methods or arrangements for sensing record carriers, e.g. for reading patterns by galvanic contacts, e.g. card connectors for ISO-7816 compliant smart cards or memory cards, e.g. SD card readers housing of the card connector
    • G06K7/006Methods or arrangements for sensing record carriers, e.g. for reading patterns by galvanic contacts, e.g. card connectors for ISO-7816 compliant smart cards or memory cards, e.g. SD card readers housing of the card connector the housing being a portable casing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06KRECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/0013Methods or arrangements for sensing record carriers, e.g. for reading patterns by galvanic contacts, e.g. card connectors for ISO-7816 compliant smart cards or memory cards, e.g. SD card readers
    • G06K7/0086Methods or arrangements for sensing record carriers, e.g. for reading patterns by galvanic contacts, e.g. card connectors for ISO-7816 compliant smart cards or memory cards, e.g. SD card readers the connector comprising a circuit for steering the operations of the card connector
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06QDATA PROCESSING SYSTEMS OR METHODS, SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00Payment architectures, schemes or protocols
    • G06Q20/30Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/355Personalisation of cards for use
    • G06Q20/3552Downloading or loading of personalisation data

Abstract

To program the chip card reader (30) an artificial chip card (40) is inserted into the reader. The chip card contains data for programming the memory and has standard contacts (C1-C8) connected electrically to a PC (50) or similar for controlling the programming process. An Independent claim is made for a chip card reader with a microprocessor and a memory that can be programmed by insertion of an artificial chip card containing the programming data in a memory.

Description

The present invention relates to a chip card reader comprising a microprocessor, an electrically programmable memory and a connector comprising contacts arranged to connect microprocessor ports <B> to contact areas of a chip card. The present invention particularly relates to card readers <B> to </ B> puce called "viewers", of the type illustrated in FIG. 1, including a small-sized box 2, a <B> 3 </ B> display and a slot 4 introducing a <B> <B> 5 <B> card. </ B>

This type of reader <B> 1 </ B> is the subject of various applications and allows for example to display the number of units remaining in a phone card, the amount of money available in a card <B> to </ B> chip type electronic wallet, etc. Due to its small size, the reader <B> 1 </ B> is sometimes in the form of a key ring, as seen on Figure <B> 1. </ B>

As illustrated in FIG. 2, there is generally in such a reader <B> 1 </ B> a <B> board <B> 10 </ B> on which a microprocessor <B is arranged. > 11, </ B> display <B> 3, </ B> chip card slot 12, a <B> 13 </ B> limit switch and a electric battery 14 supplying power to the microprocessor <B> 11. </ B> The connector 12, generally <B> to </ B> friction, comprises metal pads 12-i arranged to coincide with the contact pads 5 -i from a <B> to a <B> 5 </ B> card inserted into the drive. Limit switch <B> 13 </ B> is connected to the DTC1, DTC2, and <B> 11 </ B> ports of the microprocessor and detects the insertion or removing the <B> to </ B> chip <B> 5. </ B>

The microprocessor <B> 11 </ B> is generally of the microcontroller type and incorporates on the same silicon chip, in addition to a central unit <B> 15 </ B> (CPU), various peripheral elements. These include a memory plane <B> 16, a first group <B> 17 </ B>, and a second group <B> 18 </ B> of input / output ports. The first group <B> 17 </ B> designates microprocessor ports dedicated to communication with the cards <B> to </ B> chip, <B>. </ B> are electrically connected to the connector 12. The second group <B> 18 </ B> denotes various other ports of the microprocessor <B> 11, </ B> including the aforementioned DTC1, DTC2 ports. The memory array <B> 16 </ B> usually includes a volatile program memory <B> 16-1 </ B> in which the application program of the reader is loaded, and a RAM <B> 16-2 </ B > RAM type for temporary storage of data while reading a <B> to </ B> chip. The reader application program usually includes the communication parameters with a chip card (card type to be read, communication protocol, data location <B> to </ B> read, <B > ... </ B> and the <B> to </ B> operations performed when a card is inserted.

In practice, program memory <B> 16-1 </ B> can be programmable and electrically erasable EEPROM or FLASH memory, or a ROM type ROM. As is well known to those skilled in the art, the EEPROM memories have the advantage, compared to the ROM memories, of being able to be erased and programmed <B> to </ B> will via ports of the microprocessor, for example ISP-SEL, ISP-DATA, ISP-CK ports shown in FIG. 2. The ISP-SEL port makes it possible to place the microprocessor in the ISP ("In Situ Programming") mode. <B>. </ B> When the microprocessor is in the ISP mode, the ISP-CK port delivers a synchronization clock signal and the ISP-DATA port receives in serial form the programming data of the memory <B> 16-1. </ B>

However, these programming facilities offered by microprocessors <B> to EEPROM memory are not used in low cost readers of the type described above. The prediction of a specific connector to access the ISP ports indeed increases the cost price of the readers and does not make sense. It is preferred to use a microprocessor provided with a conventional ROM that is programmed at the electrical test stage, when the integrated circuits are still present collectively on a silicon wafer. In the event of excess production or last-minute application changes, PCBs that have been assembled unnecessarily are discarded and new cards are manufactured with appropriately programmed microprocessors.

The present invention aims to overcome this disadvantage.

More particularly, the present invention is directed to a chip card reader comprising a programmable and electrically erasable memory and a method for programming or reprogramming this memory without the need for a specific connector.

This object is achieved by a method for loading a program into the memory of a chip card reader comprising a microprocessor and a connector having contacts arranged to connect microprocessor ports to <B>. Contact areas of a chip card, comprising a step of sending to the microprocessor memory programming data via the connector, by inserting into the reader a dummy chip card including standard contact pads connected in part by electrical wires to a control device of the memory programming process . According to one embodiment, at least one signal or command necessary for triggering the programming process of the memory is applied to the microprocessor via a contact pad of the dummy card chosen from the contact pads C4 and <B > C8 </ B> provided by the ISO standard <B> 7816. </ B>

According to one embodiment, at least one signal or command necessary to trigger the memory programming process is applied to the microprocessor via an additional contact pad arranged on the dummy card <B> to </ B>. proximity to the standard contact pads from card <B> to </ B> chip.

According to one embodiment, the method comprises a preliminary step of delivery <B> to </ B> zero of the microprocessor made by means of a system internal to the microprocessor, arranged to deliver a delivery signal <B> to </ B > zero <B> to </ B> the powering up of the microprocessor, and by means of a limit switch arranged to turn on the microprocessor when a card is inserted into the reader.

According to one embodiment, the dummy card comprises an adapter circuit of the signal voltage emitted or sent to the microprocessor, the adapter circuit receiving on the one hand a supply voltage and a potential reference of the microprocessor via the contact pads. standard of the dummy card, and secondly a supply voltage and a potential reference of the control device.

According to one embodiment, the reader comprises a random access memory, an electrically erasable and programmable memory and a read only memory, the method comprises a step of loading a first program into the reader's RAM memory, while wherein the microprocessor is controlled by a program present in the ROM, and a step of loading a second program into the electrically programmable memory, during which the microprocessor is controlled by the first program.

The present invention also relates to a chip card reader comprising a microprocessor, an electrically programmable memory, a connector comprising contacts arranged to connect microprocessor ports to contact pads. from a chip card, and means for loading a program into the programmable memory via the connector and the microprocessor port intermediate normally serving to communicate with a card <B> to </ B> chip.

According to one embodiment, at least one connector contact is electrically connected to an input of the microprocessor provided to receive a signal or a command necessary to trigger a process of loading a program into the memory of the microprocessor. reader.

According to one embodiment, the contact corresponds by its arrangement in the connector <B> to </ B> standard contact area of card <B> to </ B> chip chosen among ranges C4 and <B> C8 </ B > provided by the ISO standard.

According to one embodiment, the contact corresponds, by its arrangement in the connector <B> to a non-standard contact pad arranged on a dummy card <B> near the standard contact pads of the card. <B> to </ B> chip.

These objects, features and advantages of the present invention will be set out in more detail in the following description of the method according to the invention and various embodiments of card readers <B> to </ B> chip according to the invention, made < B> to </ B> non-limiting title refering to <B> to </ B> the ISO standard <B> 7816 </ B> and in relation to the attached figures among which <B>: </ B> < B> - </ B> The figure <B> 1 </ B> previously described represents a <B> to </ B> chip type reader "viewer", <B> - </ B> Figure 2 previously described schematically shows the internal structure of the reader of the figure <B> 1, </ B> <B> - </ B> Figure <B> 3 </ B> schematically represents a first embodiment of a reader of a <B> to </ B> chip according to <B> 1 </ B> invention and illustrates the method according to the invention, <B> - </ B> Figure 4 represents a voltage adapter arranged in a card dummy according to the invention, <B> - </ B> figures <B> SA to 5D </ B > represent signals and commands applied to the reader of the figure <B> 3 </ B> to trigger a programming process, <B> - </ B> the figure <B> 6 </ B> represents the memory plane of the microprocessor of the figure <B> 3 </ B> and illustrates an aspect of the method according to the invention, <B> - </ B> the figure <B> 7 </ B> is a chronogram summarizing the process illustrated by FIG. 6, FIG. 8 schematically represents a second embodiment of a chip card reader according to the invention, and <FIG. FIG. 9 schematically represents a third embodiment of a chip card reader according to the invention.

As illustrated in FIG. 3, the method according to the invention consists in programming or reprogramming a card reader <B> to </ B>. B> chip by means of a card <B> to </ B> dummy chip 40 inserted into the reader <B> 30, </ b> the dummy card 40 being connected by electrical wires 41 <B> to </ B> a control device of the programming process, or programmer <B> 50, </ B> in itself classic.

The dummy card 40 here comprises eight standard contact ranges <B> C1 to </ B> CB provided by the ISO standard <B> 7816, </ B> connected to the electrical wires 41 via a circuit adapter. voltage 42.

The <B> 30 </ B> reader conventionally comprises a microprocessor <B> 31 </ B> and a connector <B> 32 </ B> arranged on a printed circuit board <B> 33. </ B> Microprocessor <B> 31 </ B> includes program memory of the erasable and electrically programmable type and includes an ISP-SEL port for selection of ISP mode (memory programming). The microprocessor <B> 31 </ B> also includes ports P1, P2, P3, <B> P5, P6, P7 </ B> dedicated to communications with cards <B> to </ B> chip. The ports P1-P3, P5-P7 are electrically connected to contacts C1-c3, c5-c7 of the connector 32, for example by means of pins b1-b3, b5-b7 of the <B> 32 </ B> connector soldered to the board <B> to </ B> circuit board <B> 33. The contacts cl-c3, c5-c7 correspond, by their arrangement , to the standard contact pads Cl-C3, C5-C7 of a board <B> to </ B> chip. Still conventionally, the microprocessor <B> 31 </ B> has a reset reset input, ports DTC1, DTC2 connected <B> to </ B> a limit switch 34, and a terminal VDD power supply and a GND ground terminal respectively connected to the anode and cathode of an electric battery <B> 35. </ B>

According to the invention, the ISP-SEL port and the RESET terminal of the microprocessor are connected <B> to </ B> contacts c4 and c8 of the connector <B> 32, </ B> here via pins b4 and <B> b8. </ B> The contacts c4, c8 correspond, by their location, to the standard contact pads C4, <B> C8 </ B> a card <B> to </ B> chip. These ranges are generally not used in communications with chip cards (reserved by ISO 7816-2 to ISO / IEC JTC 1 / SC 17). the invention to access <B> to </ B> distance, through the dummy card 40 and the connector to the ISP-SEL port and <B> to the </ B> the RESET terminal.

On the other hand, when the microprocessor <B> 31 </ B> is in the ISP mode, the ports Pl, P3, <B> P5 </ B> and <B> P7 </ B> are used as ISP ports as described in Table <B> 1 </ B> below.

Figure img00070017

Table <SEP><B> 1 </ B>
<tb><SEP> Port <SEP><SEP> Typical <SEP><SEP> Port <SEP><SEP> Usage <SEP> Port <SEP> Port <SEP><SEP> ISP Port
<tb><B> Iso </ B><SEP> (according to <SEP><B> ISO <SEP> 7816) </ B><SEP> (according to <SEP> the invention)
<tb><b> ci <SEP> (VCC) <SEP> Deliver <SEP><SEP> power <SEP> power <SEP> Deliver <SEP><SEP> voltage <SEP> VDD
<tb><U> electrical <SEP> of a <SEP> card <SEP><B> to </ B><SEP> bullet </ U>
<tb> P2 <SEP><B> C2 <SEP> (RST) <SEP> Delivers <SEP> the <SEP><SEP> signal <SEP> delivery <SEP><B> to </ B><SEP> zero <SEP> of a <SEP><I> no <SEP> used </ I>
<tb> card <SEP><B><U> to </ U></B><U><SEP> bullet </ U>
<tb> P3 <SEP><B> C3 <SEP> (CLK) <SEP><SEP> Emet <SEP><SEP> Clock <SEP> signal from a <SEP><cardSEP><B> to </ B><SEP> Port <SEP> ISP-CK
<tb><U> bullet </ U>
<tb><B> P5 <SEP> C5 <SEP> (GND) </ B><SEP> Reference <SEP> of <SEP> mass <SEP> Mass <SEP><B> ISP </ B>
<tb><B> P6 <SEP> C6 </ B><SEP> (VPP) <SEP> Deliver <SEP><SEP><SEP> voltage <SEP> Programming <SEP><I> No <SEP > used </ i>
<tb> VPP <SEP> of a <SEP><U> card <SEP><B> to </ B><SEP> bullet </ U>
<tb><B> P7 <SEP> C7 <SEP> (1/0) </ B><SEP><SEP> Serial <SEP> for <SEP> Issuing / Receiving <SEP> of <SEP> Port <SEP><B> ISP-DATA </ B>
<tb> data <SEP> with <SEP><U> a <SEP> card <SEP><B> at </ B><SEP> chip </ U> In ISP mode, port P1 delivers VDD voltage provided by the <B> 35 </ B> battery and the <B> P5 </ B> port delivers the GND ground of the microprocessor. The voltage V DD and the GND mass are sent to the circuit 42 for the voltage adaptation of the received signals <B> or transmitted </ B> by the microprocessor <B> 31. </ B> The port P3, used as a ISP-CK port, delivers the CK clock signal allowing the programmer <B> 50 </ B> to synchronize the data it sends to the microprocessor. The port <B> P7, </ B> used as the ISP-DATA port, receives the programming data sent by the programmer <B> 50. </ B>

FIG. 4 represents an exemplary embodiment of the adapter circuit 42. The circuit 42 is interposed on the ISP-CK transmission lines (sending the CK clock signal to the programmer <B> 50), 1 SP-DATA (sending the programming data to the microprocessor), ISP-SEL (sending an ISP mode selection command to the microprocessor), and RESET (sending the reset signal <B> to </ B> zero of the microprocessor) <B >. </ B> The circuit 42 receives on one side the voltage VDD and GND ground of the microprocessor <B> 31 </ B> and on the other hand the supply voltage VDDE and the mass GNDE of the controller < B> 50. </ B> The GND and GNDE masses are connected together. The voltage adaptation is provided in a simple manner by PMOS type transistors Tl T4 whose source is connected to the VDD or VDD voltage via a resistance of high value R1 <B> to </ B> R4. The gate of each transistor Tl <B> to </ B> T4 is connected <B> to a transmission line on the side where the signal is transmitted, while the source of each transistor is connected <B> to </ B> a transmission line from the side the signal is sent.

In practice, the circuit 42 is capable of various other embodiments and may in particular be arranged <B> to </ B> within the programmer <B> 50 </ B> rather than on the dummy card 40. Also, the circuit 42 may not be necessary if the programmer's VDDE voltage <B> 50 </ B> is compatible with the VDD voltage of the microprocessor <B> 31. </ B>

An example of implementation of the method of the invention will now be described in more detail. Figures <B> 5A <B> 5D </ B> illustrate a microprocessor programming sequence <B> 31 </ B> and represent respectively the signals applied to the RESET terminal and the ISP-SEL ports , ISP-DATA (port <B> P7), </ B> as well as the signals sent by the ISP-CK port (port P3).

During a step S1, the programmer <B> 50 </ B> applies a reset signal to the RESET terminal of the microprocessor <B> 31 </ B> (FIG. <B> 5A), </ B > for example a signal <B> to 1. </ B> The RESET signal is then reset <B> to 0 </ B> for the microprocessor to start. During a <B> S2 step, the programmer <B> 50 </ B> applies a predetermined number of pulses to the ISP-SEL port (FIG 5B), conventionally representing a command " ISPSEL "ISP mode activation. The microprocessor recognizes the ISPSEL command and enters the ISP mode. Thus, during a step <B> S3, the microprocessor delivers the clock signal CK on the ISP-CK port (FIG. <B> 5D) </ B> as well as the voltage VDD and the GND mass on the P1 and P5 ports. The <B> 50 </ B> programmer sends the programming data to the ISP-DATA port in synchronization with the CK clock signal, and the microprocessor loads the received data into its memory.

Figure <B> 6 </ B> represents the memory layout <B> 36 </ B> of the microprocessor <B> 31 </ B> and illustrates in relation to the timing diagram of Figure <B> 7 </ B> a preferred embodiment of the method of the invention offering a great flexibility in programming the microprocessor. The memory array <B> 36 </ B> comprises a read-only memory <B> 37 </ B> of ROM type, an electrically erasable and programmable memory <B> 38 </ B> of type EEPROM or <B> FLASH < / B> and RAM <B> 39 </ B>. The read-only memory <B> 37 </ B> includes an active PGRBOOT root program <B> at </ B> each microprocessor start <B> 31. </ B> After the microprocessor zero reset (step S1), the PGRBOOT program detects the ISPSEL command on the ISP-SEL port (step <B> S2) </ B> and switches the microprocessor <B> 31 </ B> to ISP mode (step <B> S3) . </ B>

According to the invention, the program PGRBOOT loads the data received on the ISP-DATA port into the random access memory <B> 39. </ B> A program is thus loaded into the RAM <B> 39 </ B>. PGR1 which is not a program application of the reader but a program of loading, in the EEPROM memory 38, of a program PGR2 application. When the program PGR1 has been loaded into the RAM <B> 39 </ B> (step <B> S3), </ B> the program PGRBOOT executes, during a step S4, a JUMPRAM instruction. This instruction loads into the microprocessor's ordinal counter the address of the RAM <B> 39 </ B> where the first instruction of the program PGR1 is located. During step S4, the program PGR1 thus takes control of the microprocessor. During a <B> S5 step, the PGR1 program delivers the clock signal to the ISP-CK port. The programmer <B> 50 </ B> detects the reappearance of the clock signal CK and sends on the ISP-DATA port the data constituting the application program PGR2, which are loaded into the EEPROM memory <B> 38 </ B> by the PGR1 program. The reader <B> 30 </ B> according to the invention can thus be programmed and reprogrammed will once its manufacture completed.

In practice, the memory plane <B> 36 </ B> can be incorporated on the silicon chip of the microprocessor <B> 31 </ B> (the microprocessor is then called a microcontroller) or be constituted by one or more chips of silicon separate.

It will be apparent to those skilled in the art that the present invention is susceptible to various embodiments, both in software (how data is loaded and ISP mode trigger protocol). As an example of material modifications, the figures <B> 8 </ B> and <B> 9 </ B> illustrate two embodiments of the reader according to the invention and two corresponding variants of the method according to the invention.

In the <B> 30-1 </ B> drive of Figure <B> 8, </ B> the anode of the <B> 35 </ B> power cell is connected to <B> VDD terminal of microprocessor <B> 31 </ B> via limit switch 34 (DTC1, DTC2 are no longer used). A capacitor <B> 60 </ B> is arranged between the GND and VDD terminals of the microprocessor. The microprocessor comprises a conventional system of delivery <B> to </ B> zero the appearance of the supply voltage VDD, here taking the form of a low voltage detector LVD <B> 61 </ B> (" Low Voltage Detector "). The detector <B> 61 </ B> delivers the signal RESET <B> 1 </ B> when the supply voltage appears, and releases the signal RESET when the voltage becomes higher <B> at </ B> a threshold The detector <B> 61 </ B> resets the signal RESET <B> 1 </ B> when the supply voltage decreases and becomes lower <B> than </ B> a threshold V2 lower than the threshold V1.

Thus, when the dummy card 40 is inserted in the reader <B> 30-1, </ B> the limit switch 34 closes, the capacitor <B> 60 </ B> is charged and the voltage VDD rises gradually. When the voltage VDD reaches the threshold Vl, the signal RESET is released by the detector <B> 61 </ B> and the program PGRBOOT is executed. The microprocessor goes into ISP mode if it receives on the ISP-SEL port the ISPSEL command described above. In this embodiment, it is therefore not necessary to remote control the RESET terminal and it is not connected to the connector <B> 32. </ B>

In the <B> 30-2 </ B> drive of Figure 9, the <B> 32 </ B> connector has two additional C9 contacts, corresponding in layout <B> to < / B> additional contact pads <B> C9, C10 </ B> of the dummy card 40. These ranges <B> C9, C10 </ B> are arranged on the dummy card 40 near the standard contact pads < B> Cl to C8. </ B> The contacts c9, clO are respectively connected to the ISP-SEL port and <B> to the RESET terminal of the microprocessor <B> 31 </ B> via pin <B> b9, </ B> blO of the <B> 32 connector. </ B> Thus, the RESET signal and the ISPSEL command are not sent to the microprocessor by the standard ISO ranges C4, <B> C8 </ B> but by the additional ranges <B> C9, C10. </ B>

Various other embodiments of the reader according to the invention may be provided by combining the three embodiments which have just been described. Furthermore, although the reader described above is intended to read ISO cards <B> 7816, </ B> the present invention is transposable <B> to </ B> any other type of reader, including a reader of card answering <B> '</ B> the standard AFNOR.

 Also, although the present invention was originally designed to allow the use of <B> to </ B> EEPROM or <B> FLASH </ B> microprocessors in low cost manufacturing drives, the present invention it is no less applicable <B> to </ B> any type of reader and allows, in general, to avoid the installation of an additional connector.

Claims (1)

  1. <U> CLAIMS </ U> <B> 1. </ B> Method for loading a program (PGR1, PGR2) into the memory <B> (36, 38, 39) </ B> of a reader <B > (30, 30-1, </ b> <B> 30-2) </ B> card <B> to </ B> chip comprising a microprocessor <B> (31) </ B> and a connector <B> (32) </ B> having contacts (cl-c8) arranged to connect ports (Pl, P3, <B> P5, P7) </ B> of the microprocessor <B> to </ B> contact pads (C1-C8) of a board <B> to </ B> chip, characterized in that it comprises a step consisting in sending to the microprocessor programming data of the memory <B> (36, 38, 39) </ B> through the <B> (32) connector, </ B> inserting into the <B> drive (30, 30-1, 30-2) </ B> a dummy chip card (B) containing standard contact pads (C1-C8) connected in whole or in part by electrical wires (41) <B> to </ B> > a <B> (50) </ B> device for controlling the programming process of the memory. Method according to claim 1, wherein at least one signal (RESET) or command (ISPSEL) necessary for triggering the memory programming process <B> (36, 38, 39) </ B> is applied to the microprocessor <B> (31) </ B> through a contact pad of the dummy card (40) selected from the contact pads C4 and <B> C8 </ B> provided by the ISO standard <B> 7816. </ B> <B> 3. </ B> The method according to one of claims <B> 1 </ B> and 2, wherein at least one signal (RESET) or a command (ISPSEL) required to trigger the memory programming process <B> (36, 38, 39) </ B> is applied to the microprocessor <B> (31) </ B> via an additional contact area <B> (C9, C10) </ B> arranged on the dummy card (40) <B> to </ B> proximity of the standard contact pads card <B> to </ B> chip ( Cl-C8). 4. Method according to one of claims <B> 1 3, </ B> comprising a preliminary step of delivery <B> to </ B> zero of the microprocessor realized by means of a system <B> (61) < / B> internal microprocessor, arranged to deliver a reset signal <B> to </ B> zero (RESET) <B> to </ B> powering up the microprocessor, and by means of an end switch stroke device (34) arranged to turn on the microprocessor when a card is inserted into the reader (B) (30-1). </ B> <5> </ B>. Method according to one of the claims <B> 1 to </ B> 4, wherein the dummy card (40) comprises an adapter circuit (42) for the voltage of the signals transmitted or sent to the microprocessor <B> (31), </ B> the adapter circuit receiving on the one hand a supply voltage (VDD) and a potential reference (GND) of the microprocessor via the standard contact pads <B> (C1, C5) </ B> of the dummy card (40 ), and on the other hand a supply voltage (VDDE) e t a potential reference (GNDE) of the control device <B> (50). <B> 6. </ B> Method according to claim 1 <B> 1 to 5. </ B> in which the reader <B> (30, 30-1, 30-2) </ B> comprises a random access memory <B> (39), </ b> a programmable and electrically erasable memory <B> (38) < / B> and a read-only memory <B> (37), </ B> characterized in that it comprises a step (S4) consisting of loading a first program (PGR1) into the RAM of drive, during which the microprocessor is controlled by a program (PGRBOOT) present in the ROM, and a step <B> (S6) </ B> consisting of <B> to </ B> load a second program (PGR2) in the electrically programmable memory <B> (38), </ B> during which the microprocessor is controlled by the first program (PGR1). <B> 7. </ B> <B> (30, 30-1, 30-2) </ B> board to </ B> chip including a <B> microprocessor (31), <B> / B> an electrically programmable memory <B> (38) </ B> and a connector <B> (32) </ B> having contacts (cl-c8) arranged to connect ports (Pl, P3, <B > P5, P7) </ B> of the microprocessor <B> (31) to </ B> the contact pads (C1-C8) of a board <B> to </ B> chip, characterized in that it comprises <B> means (36, 37, 39, PGRBOOT PGR1, RESET, bl -blO, cl-clO, P1, P3, P5, P7, ISP-SEL, 40). ) to load a program (PGR2) into the programmable memory <B> (38) </ B> via the <B> (32) </ B> connector and via ports (P1, P3, <B> P5, P7) </ B> of the microprocessor normally serving <B> to </ B> communicate with a <B> to </ B> chip. <B> 8. </ B> Card reader <B> to </ B> chip according to claim 7, wherein at least one contact (c4, c8, c9, clO) connector B> (32) </ B> is electrically connected <B> to </ B> a microprocessor input (RESET, ISP-SEL) intended to receive a signal (RESET) or a command (ISPSEL) necessary for triggering a process of loading a program (PGR1, PGR2) into the memory <B> (36, 38, 39) </ B> of the reader. <B> 9. </ B> Card reader <B> (30, 30-1) <B> to </ B> chip according to claim 8, wherein said contact (c4, c8) corresponds by its arrangement in the connector <B> (32) to </ B> a standard board contact area <B> to </ B> chip selected among the ranges C4 and <B> C8 </ B> provided by the ISO standard. <B>. </ B> Card reader <B> (30-2) <B> to </ B> chip according to one of claims <B> 8 </ B> and <B> 9, </ B> wherein said contact (c9, clO) corresponds by its arrangement in the connector <B> (32) to </ B> a non-standard contact area <B> (C9, C10) </ B > arranged on a dummy card (40) <B> to </ B> near the standard contact pads (Cl-C8) card <B> to </ B> chip.
FR9910684A 1999-08-18 1999-08-18 Programmable chip card reader Expired - Fee Related FR2797700B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003005285A1 (en) * 2001-07-02 2003-01-16 Tds Todos Data System Ab A card reader and a method for reading of cards

Citations (4)

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Publication number Priority date Publication date Assignee Title
EP0409241A1 (en) * 1989-07-19 1991-01-23 Kabushiki Kaisha Toshiba IC card with additional terminals and method of controlling the IC card
WO1995004328A1 (en) * 1993-07-30 1995-02-09 Intellect Australia Pty. Ltd. Device and method for ic cards
DE29513985U1 (en) * 1995-08-31 1995-11-02 Cards & Devices Chipkartenloes Miniaturized reader for chip cards
US5679945A (en) * 1995-03-31 1997-10-21 Cybermark, L.L.C. Intelligent card reader having emulation features

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0409241A1 (en) * 1989-07-19 1991-01-23 Kabushiki Kaisha Toshiba IC card with additional terminals and method of controlling the IC card
WO1995004328A1 (en) * 1993-07-30 1995-02-09 Intellect Australia Pty. Ltd. Device and method for ic cards
US5679945A (en) * 1995-03-31 1997-10-21 Cybermark, L.L.C. Intelligent card reader having emulation features
DE29513985U1 (en) * 1995-08-31 1995-11-02 Cards & Devices Chipkartenloes Miniaturized reader for chip cards

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003005285A1 (en) * 2001-07-02 2003-01-16 Tds Todos Data System Ab A card reader and a method for reading of cards
US7104457B2 (en) 2001-07-02 2006-09-12 Tds Todos Data System Ab Card reader and a method for reading of cards

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