FR2792113A1 - Production method of integrated circuit involves shallow trench isolation adjacent to active zone of insulated-gate transistor - Google Patents

Abstract

Method comprises formation of set of layers on substrate (1) including insulating layer (20) and stop layer with remaining portions (31), stage of formation of block of insulating material (MI) in trench (7) including etching of set of layers, formation of trench in substrate by etching, filling of trench with insulating material, and finishing stage. Finishing stage includes, prior to the formation of the gate oxide (OXG) on the active zone of transistor, the stages of surface oxide removal reducing the height of the block of insulating material formed in the trench. The etching of the set of layers includes a lateral etching of the stop layer along perimeter of the opening of the trench (7) to a lateral distance (d) chosen with respect to the height reduction in the finishing stage so that the block of insulating material filling the trench does not have a depression with respect to the level of gate oxide, or that the level of localised depression is less than 10 nm in depth. The block of insulating material (MI) does not extend to the active zone, or extends to the active zone to a distance less than 15 nm. The lateral distance (d) of etching can be equal to 10 nm, and not greater than 40 nm. The lateral etching of the stop layer formed of eg. silicon nitride, is carried out after the trench etching and before the filling of trench. A layer of material with remaining portions (40), of different material as eg. tetraethylorthosilicate (TEOS), is deposited on the stop layer, and the etching of the set of layers is anisotropic with use of a resin mask deposited on the upper layer. An opening of the resin mask corresponds to the opening of trench, and the lateral etching is isotropic with use of preliminary etched upper layer as a mask. The upper layer with remaining portions (40) is removed before the filling of trench. The insulating layer with remaining portions (20) is formed of eg. silicon dioxide.

Description

I Method for producing an integrated circuit comprising a trench

  lateral insulation attached to an active area of a

  transistor, and corresponding integrated circuit.

  The invention relates to the manufacture of integrated circuits, and more particularly to the production of lateral isolation trenches attached to an active area of a transistor in order to reduce the parasitic effect of

corner of such a transistor.

  Currently, the production of an insulated gate field effect transistor (MOS transistor) whose active area is attached to a lateral isolation trench (Shallow Trench Isolation in English) leads to the production of a vacuum or local cavity, located at the edge of the active area, between this and the insulating material (oxide) of the trench. This cavity results in the presence of polysilicon (material forming the gate of the transistor) around the rounded corner of the active area, which results in the presence of a parasitic transistor at the corner of the active area. And, this parasitic wedge effect, results in a threshold voltage of the globally produced transistor, inhomogeneous in all the active zone because higher in the center of this one than at the edge. This therefore causes

  an increase in the leakage currents of the global transistor.

  The invention aims to provide a solution to this problem.

  An object of the invention is to minimize or even completely eliminate the parasitic wedge effect resulting from the production of a

  lateral isolation trench attached to an active area of a transistor.

  The invention therefore generally proposes a method of producing an integrated circuit comprising a lateral isolation trench attached to an active area of a transistor. The realization of the trench comprises the formation on the substrate of a stack of layers comprising a layer called stop layer (by in particular its stop function during a subsequent mechanochemical polishing). This barrier layer is for example formed of silicon nitride. The method also includes a phase of forming a block of insulating material (typically consisting of one or more oxides) in the trench, this formation phase comprising an etching of said stack, an etching of the trench and a filling of the trench by material

  insulator (typically made up of one or more oxides).

  The method also includes a finishing phase comprising, prior to the formation of a gate oxide on the active area of the transistor, superficial deoxidation steps reducing the size of the

  block of insulating material formed in the trench.

  According to a general characteristic of the invention, the etching of said stack also includes a lateral etching of the barrier layer relative to the periphery of the opening of said trench on a

lateral engraving distance.

  This distance is chosen taking into account the size of said reduction in size effected in the finishing phase, so as to obtain in said trench, after formation of the gate oxide, a block of insulating material whose profile is devoid of depression relative to the level of the gate oxide, or else present relative to this level, a depression

  located with a depth of less than 10 nanometers (100).

  The surface deoxidation steps forming part of the finishing phase are conventional steps well known to those skilled in the art and whose characteristics are perfectly known and

  predetermined in the complete process for producing the integrated circuit.

  Those skilled in the art will therefore be able to choose the lateral etching distance of the masking layer without difficulty, so as to ultimately obtain the

required profile.

  The minimization of the depth of the local cavity present at the corner of the active area, or even the total elimination of this cavity, therefore makes it possible to minimize or even completely eliminate the parasitic wedge effect. Furthermore, the elimination of any local depression may be accompanied by an overflow of the block of insulating material from the trench above the active area. However, it is preferable, in order to further optimize the performance of the overall transistor, that this block of material insulating from the trench does not extend too much above the active zone. Also, according to a preferred embodiment of the invention, the distance of the lateral engraving is chosen taking into account said reduction in size effected in the finishing phase, so as to obtain in said trench, after formation of the gate oxide, a block of insulating material whose profile does not extend beyond the active area or extends beyond the active area with an overflow distance of less than 15

nanometers (150).

  Even if a person skilled in the art can easily adjust the distance of the lateral engraving so as to obtain the desired effects according to the invention, it has been observed that it was preferable that the distance of said lateral engraving be at least equal to 10 nanometers. Indeed, a lateral etching distance of less than 10 nanometers would not bring any significant improvement as regards the reduction of the parasitic wedge effect, compared to the prior art, and could even lead to obtaining

  local cavity deeper than 10 nanometers.

  Likewise, it has been observed that the distance of said lateral engraving should preferably be less than or equal to 40 nanometers, so as to avoid ultimately obtaining too much overflow.

  important insulating material of the trench on the active area.

  Although it would be possible to carry out simultaneously or almost simultaneously the vertical etching and the lateral etching of the nitride layer (stop layer) by carrying out for example an isotropic etching specific for this nitride layer, or by playing slightly on the etching parameters, it is currently preferable to perform the lateral etching of the barrier layer after the etching of the trench and

  before filling it.

  More specifically, according to an embodiment of the method according to the invention, an upper layer made of a material different from that of the stop layer (for example TEOS oxide) is deposited on the barrier layer. The etching of said stack and of the trench comprises anisotropic etching using a resin mask placed on the upper layer of the stack and the opening of which corresponds to the opening of the trench. And the sides of the previously etched stop layer are etched laterally, isotropically, using said layer

  upper (in TEOS oxide) previously engraved as a mask (hard).

  Furthermore, it is preferable to remove said upper layer, having served as a mask for lateral etching, before filling the trench with the insulating material. Indeed, this makes it possible to avoid a bad local filling characterized by pockets free of insulating material ("voids" in English), depending on the methods of

filling used.

  The invention also relates to an integrated circuit, comprising a lateral isolation trench adjoining an active area

  of a transistor covered with a gate oxide.

  According to a general characteristic of the invention, said trench comprises a block of insulating material whose profile is devoid of depression relative to the level of the gate oxide, or has relative to said level a localized depression whose depth is

less than 10 nanometers.

  According to one embodiment of the invention, the profile of the block of insulating material does not overlap the active area or overlap the area

  active with an overflow distance of less than 15 nanometers.

  Other characteristics and advantages of the invention

  will appear on examination of the detailed description of methods of implementation

  work and realization, in no way limitative, and attached drawings, in which: - Figure 1 very schematically illustrates a portion of an integrated circuit according to the prior art, having a parasitic wedge effect; - Figures 2 to 10 illustrate very schematically different steps of an embodiment of the method according to the invention; and FIG. 11 very schematically illustrates a portion of an integrated circuit according to the invention, having resulted in minimization or even

a removal of the corner effect.

  In FIG. 1, the reference ZA designates the active area of an insulated gate field effect transistor (MOS transistor) covered with an OXG gate oxide disposed under a layer of PLS polysilicon

  intended to form the gate of the transistor.

  The active zone ZA is separated from the rest of the integrated circuit by a

  lateral insulation trench filled with MI insulating material.

  As can be seen in FIG. 1, the profile P of the block of insulating material MI locally exhibits a depression DPR with respect to the level of the gate oxide OXG. Therefore, polysilicon surrounds the rounded corner of the active area ZA thus creating, during the operation of the transistor, a stray corner transistor. The threshold voltage of this corner transistor is lower than the threshold voltage measured in the center of the active area and the leakage current (Ioff) of the overall transistor

is increased.

  The invention aims to minimize or even eliminate such a parasitic wedge effect, by proposing the method according to the invention, an embodiment of which will now be described with more reference

  particularly in Figures 2 to 1 l.

  In FIG. 2, the reference 1 designates a substrate, for example made of P-type silicon, typically having a thickness of the order of 3 microns. A sacrificial oxide layer or buffer layer 2 is formed on the upper surface of the substrate 1, typically by growth of silicon dioxide. The thickness of such a layer, commonly called by a person skilled in the art "padox", is typically of the order of 50

to 200 a.

  Then deposited on the buffer layer 2, a layer 3, which is called here "stop layer" because of its subsequent function which will be discussed in more detail below. This barrier layer is typically obtained by chemical vapor deposition (CVD deposition) and is for example formed from silicon nitride Si3N4. The thickness of such a layer is of the order of 1000 A to 2000 A. Next, an upper layer 4 formed in the example described of ethyl tetraorthosilicate oxide (TEOS) is deposited on the stop layer 3.

  in English) and having for example a thickness of the order of 200.

  As will be seen in more detail below, this upper layer will serve as a mask for lateral etching of the stop layer made of silicon nitride 3. The deposition of this layer 4 is carried out

  conventional way, for example by CVD filing.

  Then, in a manner known per se, a block of resin 5 is deposited which is also locally etched in a manner known per se, so as to define the characteristics of the periphery of the opening of the future trench (the opening 6 of the resin block corresponds to the opening of the trench). We then carry out (Figure 3) a series of anisotropic engravings

  plasma dry in the same etching equipment known per se.

  So etching successively, using the resin mask, the upper layer 4 then the stop layer 3, then the oxide layer 2 and

finally the trench 7.

  Of course, the chemical characteristics of successive engravings are modified in a manner known per se as and when

etched layers.

  The resin is then removed from the stack illustrated in FIG. 3. It therefore consists of two portions 40 of the upper layer 4 locally etched, of two portions 30 of the stop layer 3 locally

  etched and two portions 20 of the oxide layer 2 locally etched.

  We then proceed (FIG. 4) to a lateral etching of the sides of each portion 30 of the barrier layer over a lateral etching distance d. This lateral etching is obtained for example by carrying out an isotropic wet etching in an H3PO4 bath. During this isotropic etching, the two portions 40 of the upper layer 4 previously etched are used as an etching mask. It should be noted here that the material of the upper layer 4 is chosen, so that the selectivity of the etching of the barrier layer is high compared to the

  material of the upper layer 4.

  FIG. 4 therefore gives two portions 31 of barrier layer

  laterally engraved with respect to the periphery of the opening of the trench.

  The lateral engraving distance d is preferably at least

  equal to 100 and at most equal to 400 A, for example equal to 250 A.

  As an indication, the width of the opening of the trench is

  around 0.4 micron for 0.18 micron technology.

  One then proceeds to a cleaning of the walls of the trench as well as to a deoxidation in a hydrofluoric acid bath so as to consume part of the oxide 20 so as, as will be seen in more detail below, improve the rounding of the corners of the active area to further minimize the stray corner effect. This deoxidation step also makes it possible simultaneously, without the addition of another particular step, to remove the hard mask layer 40. It should be noted here that the deoxidation step leads to removal of part of the oxide 20 under the nitride layer 31, as illustrated more particularly in FIG. 5 by the

reference 21.

  We then proceed (FIG. 6) to an oxidation of the walls of the trench, in particular by carrying out thermal growth of silicon dioxide 8. The purpose of this oxidation step is not only to control the surface conditions of the sides of the trench, but also to round the corners of the cavity as explained above. In addition, those skilled in the art will have noticed that the lateral etching of the nitride layer according to the invention allows better exposure of the corners of the active area and therefore improves the rounding of the corners during this step.

1 5 oxidation.

  We then proceed (Figure 7) to fill the trench with an insulating material. More specifically, this insulating material is composed here first of all of silicon dioxide 9 deposited anisotropically by high density plasma in a plasma chamber, in a manner known per se, over a thickness typically of the order of 4000 to 5500 A. This oxide is

  less dense than silicon dioxide obtained by growth.

  Then deposited in an oven, by a conformal deposition carried out in a manner known per se, ethyl tetraorthosilicate (TEOS), referenced, over a thickness typically of the order of 3000 A to 5000 A. After densification annealing, a block of resin 1 1 is formed on the upper surface of the insulating material 10 and an etching of the insulating material is carried out (FIG. 8) using the block of resin as a mask. We then obtain the configuration illustrated very schematically in Figure 8, in which, after etching, the TEOS oxide block comprises

two points 100 and 101.

  It should be noted here that due to the lateral etching of the barrier layer (3, 30), a greater distance is obtained between the two remaining portions 31 of the barrier layer, which leads, due conformal deposition of the oxide 10, to obtain a smaller overall block of oxide, which facilitates the chemical mechanical polishing which is carried out in the next step with stopping on the nitride layer 31 so to obtain the configuration illustrated in FIG. 9. In this FIG. 9, the reference MI designates the block of insulating material present in the trench

after mechanical-chemical polishing.

  Furthermore, the removal of the TEOS layer 40 during the deoxidation before filling with the insulating material of the trench,

  allows homogeneous filling without cavities ("voids").

  After removal of the barrier layer 31 by an etching known per se, the configuration illustrated in FIG. 10 is obtained. Those skilled in the art then notice that the block of insulating material MI covers the corners of the adjacent active areas, which , as we will now see in more detail, will ultimately help to limit, even eliminate, the

  local depression causing the parasitic wedge effect.

  More precisely, after the step of removing the nitride layer, it is usual to carry out deoxidation and oxidation phases that

  we will now describe in more detail.

  From the configuration illustrated in FIG. 10, a first deoxidation is carried out leading to the withdrawal of the oxide layer 21 (padox). Then, an oxidation of the semiconductor block is carried out leading to the formation, in particular on the active areas, of a layer of sacrificial oxide with a thickness typically of 100 A (commonly designated by a person skilled in the art under the denomination

  "Sacox"). This oxidation precedes the various implantations of dopants.

  A second deoxidation is then carried out to remove this sacrificial oxide layer before forming the layer on the active areas.

  gate oxide typically having a thickness of the order of 35 Å.

  We then obtain the configuration illustrated very schematically

in Figure 11.

  In this FIG. 11, the reference OXG designates the gate oxide and the reference MI designates the block of insulating material present in the trench after this finishing phase. The deoxidation steps having taken place during this finishing phase, have consumed part of the insulating block MI illustrated in FIG. 10, then leading to the obtaining on the flanks of the block MI of a profile P. In this figure 11 1 , it is noted that the profile P does not exhibit any depression, that is to say cavity, extending below the level NV of the gate oxide (illustrated in dashed lines in FIG. 11). The insulating material of the emitted block also does not overflow on the active area. Therefore, the deposition of polysilicon forming the grid material will not lead to the production of polysilicon around the rounded corner of the active area, which removes

the parasitic corner effect.

  In general, the lateral etching distance d (FIG. 4) is adjusted taking into account the consumption of oxide in the deoxidation of the padox and the sacox carried out in the finishing phase, to obtain the configuration illustrated in FIG. 11. It is also possible, to tolerate at the end of the finishing phase, that the profile P has a slight depression localized at the corner of the active zone, the depth relative to the level NV of the gate oxide does not exceed 100

 .

  Similarly, it is possible to tolerate at the end of the finishing phase, that the profile P of the block of insulating material MI slightly protrudes over the active area ZA, while preferably not exceeding an overflow distance of 15 nanometers, so as not to damage the others too much

transistor performance.

O

Claims (9)

  1. A method of producing an integrated circuit comprising a lateral isolation trench attached to an active area of a transistor, comprising the formation on the substrate (1) of a stack of layers comprising a barrier layer (3 ), a phase of forming a block of insulating material (MI) in the trench comprising an etching of said stack, an etching of said trench in the substrate, a filling of said trench with an insulating material, and a finishing phase comprising , prior to the formation of a gate oxide (OXG) on the active area of the transistor, superficial deoxidation steps reducing the size of the block of insulating material (MI) formed in the trench, characterized in that the etching of said stacking also includes a lateral etching of the barrier layer (3) relative to the periphery of the opening of said trench (7) over a lateral distance (d) chosen taking into account said reduction in t wing operated in the finishing phase so as to obtain in said trench, after formation of the gate oxide, a block of insulating material (MI) whose profile (e) is free of depression relative to the level of the oxide grid, or presents with respect to this level a localized depression whose   depth is less than 10 nanometers.   2. Method according to claim 1, characterized in that the lateral etching distance (d) is chosen taking into account said reduction in size effected in the finishing phase so as to obtain in said trench, after formation of the oxide grid, a block of insulating material (MI) whose profile does not overlap the active area or overlap the area   active with an overflow distance of less than 15 nanometers.   3. Method according to one of the preceding claims,   characterized in that the lateral distance (d) of said engraving is at less than 10 nanometers.   4. Method according to one of the preceding claims,   characterized in that the lateral distance ((d) of said engraving is   less than or equal to 40 nanometers.   5. Method according to one of the preceding claims,   characterized in that the lateral etching of the barrier layer (3) is carried out after the etching of the trench (7) and before filling of the trench.   6. Method according to one of the preceding claims,   characterized by the fact that an upper layer (4) made of a material different from that of the stop layer is deposited on the barrier layer (3), in that the etching of said stack and of the trench comprises anisotropic etching using a resin mask (5) placed on the upper layer of the stack and whose opening (6) corresponds to the opening of the trench, and by the fact that the sides of the barrier layer previously etched, isotropically using   said upper layer previously etched (40) as a mask.   7. Method according to claim 6, characterized in that   removes said upper layer (40) before filling the trench.   8. Integrated circuit, comprising a lateral isolation trench attached to an active area of a transistor covered with a gate oxide, characterized in that said trench comprises a block of insulating material (MI) whose profile (P ) is devoid of depression relative to the level of the gate oxide (OXG), or exhibits relative to this level (NV) a localized depression whose depth is less than 10 nanometers.   9. Circuit according to claim 8, characterized in that the profile (P) of the block of insulating material (MI) does not extend over the active area or overflows into the active area by an overflow distance less than 15 nanometers.