FR2788866A1 - Method of online decompression of a computer program - Google Patents

Abstract

The instructions are addressed via pointers (P). Instructions are stored (16,19) in order of frequency of appearance. During decompression pointers are extracted from memory using addresses generated by the program counter (14), and used to address instruction extraction tables. A number (U) of low order bits of addresses supplied by the program counter are used to extract pointers.

Description

The present invention relates to a method for decompressing a

  presenting computer program

in compressed form.

  More particularly, the invention relates to a method of this type by which the decompression is carried out online, as the program proceeds.

  In the present description, the term "computer"

  means any type of processor capable of executing a

  computer program, including microprocessors.

  Furthermore, throughout the description, we

  will use the word "pointer" to denote a group of

  bits "pointing" to an instruction to execute.

  The use of pointers makes it possible to store in a memory only different instructions, even if these instructions are used several times by the program. The set of instructions thus occupies less space in memory; that's why we talk about

"compressed" program.

  Figure 1 of the accompanying drawings shows one of the most common methods of pressure relief in the art. This method implements a memory 1 with a width of M bits which is addressed by a program counter 2 forming part of a processor 3. The memory 1 contains pointers P with a width of M bits which serve as addresses for a memory or instruction table 4 with a width of N bits. The pointers of M bits are shorter than the instructions of N bits (M <N). The memory, or table, 4 contains all the instructions necessary for the operation of the

processor 3.

  This method effectively makes it possible to reduce the size of the memory 4, which contains only different instructions, but it has the disadvantage of requiring pointers of the same size M for all the program steps (or instructions), than the instruction either very frequently or very rarely performed. However, it often happens that certain instructions are used much more often than others in a

given program.

  It would therefore be more interesting to have short pointers for very frequent instructions and longer for rare instructions, so

  improve compression performance.

  In another known method illustrated in FIG. 2, the memory 1 has a width of N + 1 bits and contains both "rare" instructions Ir, with a width of N bits, and pointers P each having a width N / 2 bits and arranged in blocks B of the memory. The most significant bit of the memory word is used here to designate whether it is an Ir instruction or a block B of pointers P. The pointers P are used as addresses of the instruction table 4 containing the "frequent" instructions If the number of which can be at most equal to the maximum value 2N / 2 that a pointer P can take. The outputs of memory 1 and of table 4 are connected to a multiplexer 5 through which the instructions pass to processor 3 according to the value of the most significant bit of the address

applied to memory 1.

  Another way to arrange pointers in memory is to use Huffman coding, well known to specialists. In this case, the instructions are arranged according to the hierarchy of their frequency of appearance in the program to be executed. For example, as shown in FIG. 3, a 5-bit pointer coded by a one-bit operating code equal to 1 is used for the 16 most frequent instructions, a 7-bit pointer with two bits (01) of operating code for the 32 less frequent instructions, a 10-bit pointer with three bits (001) of operating code for 128 even less frequent instructions and finally a 13-bit pointer with four bits (0001)

  of operating code for 512 rare instructions.

  For such a case, the memory can be arranged according to the example shown in FIG. 4 which assumes a width of the memory 1 of 22 bits plus 2 coding bits. According to the hierarchical rank of the pointers, these are here arranged in blocks totaling 22 bits coded respectively by the codes 01, 10 and 11 for pointers of 11, 7 and 5 bits respectively, while very rare instructions Itr can be memorized in full (also called "native instructions") and

coded 00.

  FIG. 5 represents a known method of decompression which can make use of the examples which have just been described. The memory 1 is here connected to a decompressor 6 which can download instructions into an auxiliary cache memory 7 containing uncompressed instructions which are used by the processor 3. The program counter 2 determines whether the instruction must come from the cache memory 7 or if instructions must be extracted from memory 1 (connections 8 and 9 respectively). As a memory word (or block of pointers) comprises a variable number of pointers, the determination of the address of this block of pointers where there is a given pointer addressed by the program counter is not immediate. The addresses must, for this purpose, be converted into an address translation table 10 in order to obtain the block of pointers which will make it possible to search for the instructions necessary at the corresponding stage of the course of the program. The instructions designated by the pointers are loaded into the cache memory 7 so that they can be executed by

the processor.

  The decompression systems of the prior art which have just been described all have drawbacks. For example, if a decompression according to FIG. 2 is used, two pointers designating two consecutive instructions of the program must always be contiguous and stored at adjacent addresses in the memory for the corresponding instructions to be correctly

applied to the processor.

  To be able to make connections (or "jumps"), the address provided by the program counter requires a memory with native instructions, this

  which requires an address translation table.

  In addition, the program counter should not progress if a word in the memory has more than one pointer. In this way, to implement such a

  process, the processor must be specially designed.

  Finally, a final drawback lies in the fact that address translation requires a lot of time and requires additional memory, which in part loses the benefit of the savings made by

compression of the program.

  The object of the invention is to provide a method for decompressing a compressed program, this method having to be free from the drawbacks of the prior art. It therefore relates to a method of decompressing a compressed program intended to be executed in a processor, the compressed program consisting of at least a first series of frequently used instructions and stored in a first table, a second series of instructions less frequently used and stored in a second table and pointers having a bit length shorter than that of the instructions and being stored in successive blocks in a memory of pointers, the method consisting in selectively extracting said pointers from said memory at the using addresses generated by means of a program counter, and using these pointers selectively for the addressing of said tables and the extraction of said instructions as and when said program proceeds, characterized in that said blocks of pointers each contain the same number S = 2 pointers and in that the U bits d the lowest weight of each address supplied by said program counter are used for the successive extraction of said pointers

  the block of pointers in which they are stored.

  It follows from these characteristics that the U least significant bits can be used to identify in each block the pointer which will call the instruction used by the processor during the next program step and this, this program step

implies a connection or not.

  According to other advantageous characteristics of the invention: - the number of least significant bits of said address is applied to a multiplexer which is loaded successively with the blocks contained in said memory and the pointers of a block are selected at l using said least significant bits; a shift register is loaded successively with the content of the blocks of said pointer memory and said shift register is advanced using said number of least significant bits, in order to apply said pointers as addresses to at least one of said first and second tables; - predetermined value pointers are used as addresses of a table so as to extract therefrom said less frequent instructions and said instructions are applied, the

if applicable, said processor.

  - said pointers of predetermined value are used as addresses of a third table containing secondary pointers, used to address said second table, said less frequent instructions being thus extracted therefrom; - Said pointers contain a Huffman code and said tables containing said instructions are selectively addressed by said pointers as a function of at least one of the most significant bits of said pointers representing said Huffman code; - during a connection, said number of least significant bits of the content of said program counter is used to designate in a block of said memory the pointer to which the connection must be made; - to designate the first pointer to be used during a connection, the pointers present in said shift register are caused to progress as the program proceeds, the number of progressions is counted and this number is compared with the value represented by said low weight bits of the content of said program counter; - certain pointers in at least some of said blocks contain an NOP code and an NOP instruction is applied to said processor, when a pointer

  thus coded is extracted from said memory.

  Other features and benefits of

  the invention will appear during the description which

  will follow, given solely by way of example and made with reference to the appended drawings in which: - Figures 1 to 5 show several solutions known from the prior art for producing a system for decompressing a compressed program; - Figure 6 is a schematic representation of a system for decompressing a compressed program for a processor implementing the method according to the invention; - Figure 7 is a variant of the system shown in Figure 6; and - Figure 8 shows a schematic representation of a second embodiment of the invention. We will now refer to FIG. 6 which represents a system for decompressing a computer program allowing the execution of a first mode of

implementation of the invention.

  A memory 11 of which each memory word comprises M bits contains the work program in compressed form of a processor 12 shown at the bottom of the figure. This processor 12 uses instructions from a

width of N bits.

  The words of the memory 11 are X in number and each form a block 13 of S pointers P each having T bits. The width of a block is therefore M = TxS bits. S is an integer power of two, this power being designated by U. Consequently, the number S of pointers

per block is equal to 2u.

  In a nonlimiting example of the invention illustrated in FIG. 6, these numbers can have the

  following values: M = 96; N = 22; S = 16; T = 6; U = 4.

  The memory 11 is addressed by a program counter 14 whose U least significant bits are not used to configure each address of

this memory 11.

  The output of memory 11 is connected to a multiplexer 15 which, in order to address a given pointer from each block 13, uses the U least significant bits which are applied to it each time by the

program counter 14.

  The output of the multiplexer 15 is connected to a table 16 of frequent instructions If in which the instructions which are used most frequently during the course of the work program are recorded. The output of the multiplexer 15 is also connected to a decoder 17 which decodes on 3 bits for example, the highest values that a pointer can take. Considering the example encrypted above, the decoder 17 can decode pointers having the values 56 to 63, the values 0 to 55 being reserved

-T - TT

  as addresses from table 16, which in this case can therefore

  house a maximum of 55 most frequent If statements.

  The values 56 to 63 are decoded as follows: Bit code

56,000

57 001

58,010

59,011

60 100

61 101

62 110

63,111

  The corresponding bits decoded by the decoder 17 serve as an address part of a second table 18 in which secondary pointers Pi are stored, for example having a length V, V possibly being equal to 11, for example. The address intended for this table 18 of pointers Pi is composed of S - U bits coming from the program counter 14, more as the least significant bits, the respective three decoded bits coming

decoder 17.

  The address thus completed is used to designate pointers Pl, these being applied to a third table 19 containing instructions Imf used less frequently than the instructions If during the course

of the work program.

  Thus, the table 18 is addressed by the S - U most significant bits of the program counter 14 and by the U-1 bits leaving the decoder 17, ie with S-1 bits in total. Table 18 therefore has a size of 2.S - 1 words of 11 bits, that is to say half as many words as the pointers of six

memory bits 11.

  --if 'The outputs of tables 16 and 19 are applied in

parallel to processor 12.

  We will now describe the operation of the decompression system of Figure 6 taking as an example the values specified above. The sixteen-bit program counter 14 addresses the memory 11 by selecting one of the blocks 13 using its twelve most significant bits and one of the pointers of this block using the least four bits

significant.

Two cases can then occur.

  If the selected pointer has a value between 0 and, it directly addresses table 16 which contains the fifty-six instructions most used by the

processor 12.

  However, if the pointer has a value between 56 and

  63 is that it is an Imf instruction that is little used.

  In the example, the block illustrated in the memory has seven of these pointers, coded from 56 to 62. A block of pointers can contain a maximum of eight of these pointers

(coded from 56 to 63).

  It is now assumed that the program counter 14 and the multiplexer 15 select the second pointer of block 13, which here has the value 56. This value is decoded by the decoder 17 which supplies the three bits the

  less significant (here 000) at table 18.

  Table 18 comprises, for each block of sixteen six-bit pointers addressed by the twelve most significant bits of the program counter 14, a block of maximum eight pointers, of eleven bits each, addressed by the same address formed by the twelve most significant bits from program counter 14. The first of these pointers in each block of eight actually corresponds to code 56, the second to code 57 etc., the last corresponding to code 63. In the example discussed here, only seven six-bit pointers (memory 11) coded from 56 to 62 are used. The pointers of table 18 are then used to address the table 19 containing 2048 Imf instructions with which can

work processor 12.

  A simple calculation makes it possible to highlight the reduction in memory space that can thus be achieved. Previously (Figure 1), 64k instructions of 22 bits each were needed, or 1,441,792 bits. The system of figure 6 requires Memory 11: 64k x 6 = 393 216 bits Table 16: 56 x 22 = 1 232 bits Table 18: 32k x 11 = 360 448 bits Table 19: 2k x 22 = 45 056 bits Total 799 952 bits a reduction of about 45% compared to the system

according to figure 1.

  FIG. 7 represents a variant of the decompression system of FIG. 6. In this case, a memory 11A addressed by a program counter 14A comprises blocks 13A each made up of sixteen eight-bit pointers. Among these pointers, those with the highest four values 252 to 255 are intended to address the table 18A, while the other pointers having a value up to 251 are used to address the table 16A which contains the most frequent If statements

sent to processor 12A.

  Table 18A then directly contains blocks of four less frequent instructions Imf for this same processor. In this case, the memory 11A contains: Memory 11A: 64k x 8 = 524 288 bits Table 16A: 250 x 22 = 5500 bits Table 18A: 16k x 22 = 360 448 bits Total 890 236 bits or a reduction of 40%, approximately . The system of FIG. 8 comprises a memory 11 associated with means for enabling the addressing of any pointer P in any block 13 in the event that the work program prescribes connection to such a pointer. In this case, the connection address from the processor 12 is applied to the program counter 14, the U bits of which in this case will be used to designate the pointer P to which the connection must be made. The most significant bits of the content of the program counter 14 are also used in this case to designate the block 13 in which the pointer P to be reached is located. The output of memory 11 is connected to a

shift register 20.

  This system also includes a decoder 21 of the part U of the connection address controlling the progress of the pointers of the block 13 concerned in the shift register 20. This decoder 21 is therefore connected for this purpose to the register 20. It is also connected to a counter 22 intended to record the number of shifts taking place in the register 20. The part U of the connection address is also applied to one of the inputs of a comparator 23 which compares the position of the counter 22 with the value of the U part of the address. When the comparator 23 finds equality between its two inputs, the shift in the register 20 ceases and the pointer P is

  extract from the shift register 20.

  Each pointer P contained in the blocks 13 of the program memory 11 here comprises a Huffman code making it possible to selectively address a plurality of instruction tables (four tables 24 to 27 are provided in the example shown) under the command d a decoder 28. This decodes a predetermined number of most significant bits of each pointer P to designate which of the tables 24 to 27 will have to provide the following instruction of the

work program.

  The instructions in tables 24 to 27 are presented with a decreasing frequency of appearance in the program and are designated by pointers P of

increasing bit length.

  Thus, for example, the frequent instructions If of the table 24 can be designated by sixteen pointers of five bits each, four of which serve as the address of the table

  24 which will then include sixteen frequent If instructions.

  The fifth bit of the pointer designates the table 24. In this case, the decoder 28 shifts each time by five bits the

shift register 20.

  Similarly, if the code detected by the decoder 28 is "01", it is the table 25 which is designated. This comprises 32 less frequent Imf instructions, the pointers P then having a size of seven bits, which the shift register 20 is shifted at each program step. Tables 26 and 27 can contain even less frequent Iemf instructions and rare Ir instructions 128 and 256 respectively, respectively. The corresponding pointers then have a length of ten and thirteen bits, which the decoder must shift the register 20 at each corresponding program step. Of course, the code used to designate the table to be selected from tables 24 to 27 can be I TV different from that described. For example, according to a variant, it is possible to choose to fill certain blocks 13 of the program memory with instructions Ir directly usable by the processor 12 using for this a code "1" and to fill other blocks 13 with pointers P coded as indicated above to designate the frequent If instructions, less frequent

  Imf and even less frequent Iemf.

  This way of coding makes it possible, for example with blocks 13 with a width of 92 bits, to have, per block, four rare instructions Ir of 22 bits and eight instructions of 11 bits as less frequent Imf instructions. The objective of coding thus consists in filling

  at best the space available in each block.

  We have seen previously that the management according to the invention of the program counter 14 provides that each block 13 of the pointer memory 11 always leads to the execution of the same number of instructions. However, it would be interesting from the point of view of obtaining the best possible compression ratio, to be able to have a certain freedom in the choice of the number

  instructions to execute by block 13.

  To remedy these two apparently contradictory requirements, it is advantageous according to the invention, to sometimes use pointers P which do not lead to the execution of an instruction in the processor 12 but which contain a particular code called NOP (acronym

  meaning "No OPeration" in English).

  To insert such an instruction, which does not cause an active operation in the processor 12, the pointer code detected by the decoder 28 is, in this case, a control signal sent to a multiplexer 29 which, according to this signal , sends the instruction NOP to the I IT-processor 12 instead of the instructions from tables 24 to 27. It should be noted that, although this is not shown, such an arrangement can also be

  provided in the cases of FIGS. 6 and 7.

  According to another variant, it is possible to insert between the tables 16 and 19 of FIG. 6 or the tables 24 to 27, on the one hand, and the processor 12, on the other hand, a cache memory containing a set of uncompressed instructions with which the processor 12 works very frequently, which makes it possible, in certain cases, to avoid

  go through the decompression process.

Claims (9)

  1. A method of decompressing a compressed program intended to be executed in a processor (12; 12A), the compressed program consisting of at least a first series of instructions (If) frequently used and stored in a first table ( 16; 16A; 24), a second series of instructions (Imf; Iemf; Ir) less frequently used and stored in a second table and pointers (P) having a bit length shorter than that of the instructions and being stored in blocks successive (13: 13A) in a pointer memory (11; 11A), the method consisting in selectively extracting said pointers (P) from said memory (11; 11A) using addresses generated by means of a program counter (14; 14A), and to selectively use these pointers for addressing said tables and extracting said instructions as and when said program proceeds, characterized in that said blocks (13; 13A) of pointers (P) each contain the same number S = 2u pointers and in that the U least significant bits of each address supplied by said program counter (14; 14A) are used for the successive extraction of said pointers (P) from the block of pointers (13; 13A) in which they are stored.   2. Method according to claim 1, characterized in that it consists in applying the number of least significant bits (U) of said address to a multiplexer (15; A), in loading this multiplexer successively with the blocks (13 ; 13A) contained in said memory (11; 11A) and in selecting the pointers of a block using said least significant bits.   3. Method according to claim 1, characterized in that it consists in loading a shift register (20) successively with the content of the blocks (13) of said pointer memory (11) and in advancing said shift register ( 20) using said number of bits (U) of low weight, to apply said pointers (P) as addresses to at least one of said first and second tables (24 to 27).   4. Method according to any one of   claims 1 to 2, characterized in that pointers   (P) of predetermined value are used as addresses of a table (18A) so as to extract therefrom said less frequent instructions (Imf) and to apply said instructions, if necessary, to said processor. 5. Method according to claim 4, characterized in that said pointers of predetermined value are used as addresses of a third table (18) containing secondary pointers (Pl), used to address said second table (19) and thereby extract therefrom said less frequent instructions (Imf); 6. Method according to claim 3, characterized in that said pointers (P) contain a Huffman code and in that said tables (24 to 27) containing said instructions (If, Imf, Iemf; Ir) are selectively addressed by said pointers as a function of at least one of the most significant bits of said pointers   representing said Huffman code.   7. Method according to any one of   previous claims, characterized in that, when   of a branch, said number of least significant bits (U) of the content of said program counter (14) is used to designate in a block (13) of said memory (11) the pointer to which the branch is to be carried out . 8. Method according to claim 7, when it depends on claim 3, characterized in that, to designate the first pointer to be used during a connection, the pointers (P) present in said shift register (15) are brought to progress as the said program proceeds, in that the number of progressions is counted (22) and in that this number is compared (23) to the value represented by said low-weight bits (U) of the content of said counter program (14).   9. Method according to any one of   claims 1 to 8, characterized in that certain   pointers in at least some of said blocks contain an NOP code and in that an NOP instruction is applied to said processor (12), when a pointer so encoded is extract from said memory (11). -r-T-