FR2775142A1 - High frequency functioning state machine - Google Patents

Abstract

There is a second register and combination logic circuit, allowing future commands to be memorised during an active clock cycle period. A slave circuit is not needed.

Description

State machines for integrated circuit operating at
high frequency.

 The invention relates to state machines for integrated circuits operating at high frequency, and more generally to integrated circuits comprising state machines.

 State machines, conventionally designated by "sequencers", are generally used in digital circuits to produce control sequences, conditional or not, for any type of logic circuit used in a circuit using sequential logic, such as for example a microprocessor, a counter, a memory and more generally complex sequential circuits.

 Sequencers include at least one combinatorial circuit in which are coded logic equations combining input variables and state variables, so as to produce future state variables, representative of the future state in which the state machine, in correspondence with variations of the logical states of the variables present on inputs of said machine. The state variables are stored in a register at each period of a timing clock.

 Those skilled in the art know such state machines, in particular those of "MOORE" or "MEALAY", which are shown in FIGS. 1 and 2.

 The state machine of MOORE 1, shown diagrammatically in FIG. 1, comprises a first combinational circuit CA, the data outputs of which are connected to the data inputs of a storage register RA. The storage register RA consists, for example, of a series of D type flip-flops and is updated by a clock signal HCk.

 The data outputs of the register RA are then connected to the data inputs of a second combinational circuit CE. Said first and second combinational circuits CA and Cg respectively have a maximum propagation time TCA and TCB.

 The first combinational circuit CA produces logic variables of future state EF from at least one logic input signal I and at least one logic variable of current state EC which is located at the output of the storage register RA . The second combinational circuit produces output variables S1, corresponding to the output variables of state machine 1, as a function of the logic variables of current state. Thus, the output variables S1 of the state machine of MOORE are a function of the logic variables of current state of said state machine 1.

The output variables S1 are used to control a logic circuit 2, for example an arithmetic and logic unit ALU which will be designated hereinafter "ALU". As shown in Figure 1, the ALU is located between registers R2 of logic circuit 2. The time required for the ALU to perform a logic operation is TALUS
The maximum operating frequency FMAX of the device in FIG. 1 is calculated by considering a maximum possible time interval between two active edges of the clock clock HCk. Thus, in the example of FIG. 1, TCA is the time which defines a maximum time of the change of state generated by the first combinational circuit CA, which can authorize an operating frequency equal to fl = l / TCA. Furthermore, once the change of state has taken place, the time necessary to obtain the result at the output of the ALU is equal to TCB + TALuB corresponding to the cumulative propagation time required for the second combinational circuit CE and for propagation time of the ALU after receipt of the command from the second combinational circuit Cg, which authorizes an operating frequency equal to f2 = l / (TCB + TALU). This frequency f2, in general much less important than the frequency f1, becomes the maximum frequency FMAX of use of the circuit.

In relation to FIG. 2, the state machine of
MEALAY 3 includes a first combinational circuit CC, the data outputs of which are connected to the data inputs of a storage register RC. This is, for example, made up of a series of D type flip-flops and updated by a clock signal HCk.

 The data outputs of the RC register are then connected to the data inputs of a second combinational circuit CD. The said first and second combinational circuits CC and CD have respectively a propagation time TCC and TCD.

 The first combinational circuit CC produces logical future state variables EF representative of the future state of the machine, from at least one logic input signal I and logic current state variables EC located at the output of the RC register. The second combinational circuit produces output variables S3 corresponding to the output variables of the state machine 3, as a function of the logic variables of current state EC and of the logic input signal I. Thus, the output variables S3 of the MEALAY state machine is a function of the logic variables of current state EC and of the input logic variables I of said state machine 3.

 The output variables S3 are used to control a logic circuit 4, for example a memory 4 having an access time TMEM.

The maximum operating frequency FMAX of the device in FIG. 3 is calculated by considering a maximum possible time interval between two active edges of the clock clock HCK. Thus, in the example of FIG. 1, TCC is the time which defines a maximum state change time, generated by the first combinational circuit CC, which can authorize an operating frequency equal to fl = l / TCC. Furthermore, once the change of state is established, the time required to output the variables stored in the memory is TCD + TMEM, corresponding to the cumulative time of propagation of the second combinational circuit CD and of access time of the memory, which authorizes an operating frequency equal to 2 = 1 / (TCD + TMEM)
This frequency f2, in general much less important than the frequency f1, defines the maximum frequency FMAX.

In addition, the design of integrated circuits is based on relatively advanced description languages, such as the VHDL language (Very Hard
Description Language) known to those skilled in the art. The designers of integrated circuits are content to give logic equations of the state machine to computers which then compile the said equations to produce a circuit diagram of combinatorial logic.

In the case of complex equations, the combinatorial circuit obtained is also complex. The result obtained by compilation is not necessarily satisfactory with regard to the propagation times with the state machines of MOORE and the state machines of
MEALAY, when the state machines must manage a large number of states.

 The object of the invention is to propose a circuit comprising at least one state machine, the architecture of which makes it possible to obtain combinational circuits with reduced propagation times and not transferred to the propagation time of a controlled circuit.

 The subject of the invention is an integrated circuit comprising at least one state machine which comprises a first register for memorizing a state of the state machine and supplying current state variables on outputs, the first register having in addition data inputs to be stored and a clock input for receiving a clock signal; a first combinational logic circuit having first and second inputs and outputs, the first inputs being connected to the outputs of the first register to receive the current state variables, the second inputs being connected to input terminals to receive variables input and outputs being connected to the data inputs of the first register to provide future state variables to be stored in the first register during a next active edge of the clock signal; a second register for storing and supplying control signals to outputs, the second register further having data inputs to be stored and a clock input for receiving the clock signal; a second combinational logic circuit having outputs connected to the inputs of the second register to supply future control signals which will be stored in the second register during a next active edge of the clock signal.

 In a first embodiment, the second combinational circuit has inputs that are connected to the outputs of the first combinational circuit to receive the future state variable.

 In a second embodiment, the second combinational circuit has first and second inputs, the first inputs being connected to the outputs of the first register to receive the current state variable, and the second inputs of the second combinational circuit being connected to the terminals d 'input to receive the input variable. In a variant, the state machine further comprises a third register for partially storing a state of said state machine and supplying on an output control signals which correspond to state variables, the third register comprising at in addition to data inputs connected to the outputs of the first combinational circuit, and having a clock input for receiving the clock signal.

The invention will be better understood and other features and advantages will appear on reading the description which follows, the description making reference to the appended drawings among which:
FIG. 1 schematically represents a state machine of MOORE,
FIG. 2 schematically represents a state machine of MEALAY,
FIG. 3 schematically represents the first embodiment of a state machine according to the invention,
FIG. 4 schematically represents the second embodiment of a state machine according to the invention,
- Figure 5 shows schematically a variant of the second embodiment.

 We will not return to Figures 1 and 2, their descriptions having been made previously.

 As shown in FIG. 3, a state machine 5 comprises a first combinational logic circuit C1 having first and second data inputs and a data output.

 The first combinatorial logic circuit C1, designated in a simplified manner by "first combinatorial circuit", is a circuit in which are coded logic equations combining input variables and current state variables EC received respectively on first and second inputs, to produce future state variables EF corresponding to a future state in which the state machine 5 will be found.

The first combinational circuit C1 requests a first propagation time TC1 to supply the variables of future state.

The state machine 5 also includes a first register R1, for example consisting of flip-flops of type D, having a data input, a clock input, and an output. The first register is used to store variables and to supply, on its output, the current state variables EC. The data entry of the first register
R1 is connected to the output of the first combinational circuit C1. The clock input of the first register
R1 receives a clock signal HCk so that the said register stores the future state variables EF during each active edge of the clock signal HCk.

The first inputs of the first combinational circuit C1 are connected to the outputs of the first register R1 to receive the current state variables
EC. The second inputs of the first combinatorial circuit
C1 are connected to input terminals to receive the input variables I. The outputs of the first combinational circuit C1 are connected to the data inputs of the first register R1 to supply it with the future state variables EF.

 It should be noted that, during each active edge of the clock signal HCk, the current state variables EC are updated in the first register R1, the future state variables EF then being stored therein to become new variables d current state EC.

 In addition, the state machine has a second combinational circuit C2 and a second register R2. The second combinatorial circuit C2 has inputs connected to the outputs of the first combinatorial circuit C1 and has outputs to provide a future control variable.

 The second register R2 has data inputs, a clock input and outputs. The second register R2 is used to store variables and to supply, on its outputs, control variables Sg.

The data inputs of the second register R2 are connected to the outputs of the second combinational circuit
C2. The clock input of the register R2 receives the clock signal HCk. The future control variables are stored in the second register R2 during each active edge of the clock signal HCk and then become the control variables Sg. The second combinatorial circuit C2, making it possible to decode the future state variables EF, needs a second propagation time TC2.

 The control variable Ss makes it possible to control another circuit using sequential logic, such as for example a memory 8 having an access time TMEM8.

The maximum frequency of use of the circuit using the state machine 5 is calculated by considering a time interval between two active edges of the clock signal HCk. Thanks to the arrangement of FIG. 3, only the access time TMEM8 of the memory 8 is to be taken into account to determine the maximum operating frequency of the memory 8, the frequency being equal to fi = i / TMEM8. Furthermore, the time required to obtain the control variable Sg at the output of the second combinational circuit C2 is equal to TCl + TC2, corresponding to the sum of the propagation time of the first combinational circuit C1 and the propagation time of the second combinational circuit C2, which can authorize a frequency f2 = l / (TCl + TC2). Thus, in cases where the access time TMEM8 is relatively long compared to the first propagation time TC1, it is certain that we have TC1 + TC2 <TMEM8 + TC2 The frequency FMAX = min (1 / TMEM8 1 / (TC1 + TC2)) is in any case less than the frequency possible with the circuits of the prior art. Moreover,
If TMEM8> TC1 + TC2 then the state machine does not intervene to determine the frequency FMAX of use of the circuit.

 As shown in FIG. 4, a state machine 6 comprises a first combinational logic circuit C3 having first and second data inputs and a data output.

 The first combinatorial logic circuit C3, designated in a simplified manner by "first combinatorial circuit", is a circuit in which are coded logic equations combining input variables and current state variables EC received respectively on first and second inputs, to produce future state variables EF corresponding to a future state in which the state machine will be 6.

The state machine 6 also comprises a first register R3, for example consisting of flip-flops of type D, having a data input, a clock input, and an output. The first register is used to store variables and to supply, on its output, the current state variables EC. The data entry of the first register
R3 is connected to the output of the first combinational circuit C3. The clock input of the first register
R3 receiving a clock signal HCk so that the said register stores the future state variables EF during each active edge of the clock signal HCk.

The first inputs of the first combinational circuit C3 are connected to the outputs of the first register R3 to receive the current state variables
EC. The second inputs of the first combinatorial circuit
C3 are connected to input terminals to receive the input variables I. The outputs of the first combinational circuit C3 are connected to the data inputs of the first register R3 to supply it with the future state variables EF.

 It should be noted that, at each active edge of the clock signal HCkl, the current state variables EC are updated in the first register R3, the future state variables EF then being stored therein to become new variables of current state EC.

In addition, the state machine has a second combinational circuit C4 and a second register R4. The second combinative circuit C4 has first and second inputs, and outputs to provide a future control variable, the first and second inputs of the combinative circuit C4 being connected respectively to the input terminals to receive the input variables I and to the first register outputs
C3 to receive the current EC state variables.

 The second register R4 has data inputs, a clock input and outputs. The second register R4 is used to store and supply, on its outputs, control variables S6. The data inputs of the second register R4 are connected to the outputs of the second combinational circuit C4. The clock input of register R4 receives the clock signal HCk.

The future control variables are stored in the second register R4 during each active edge of the clock signal HCk and then become the control variables S6.

 The control variable S6 makes it possible to control another circuit using sequential logic, such as for example a memory 9 having an access time TMEM9.

 The first and second combinational circuits C3 and C4 need first and second propagation times TC3 and TC4 respectively.

 As the second combinatorial circuit C4 performs a decoding of the state variables in parallel with the first combinatorial circuit C3, the maximum frequency of use is either 1 / Tc3, or 1 / Tc4, or either l / TMEM9. This state machine 6 has the same advantages as the state machine 5 of FIG. 3. In addition, it is easier to make the maximum frequency of the circuit independent of the state machine 6 because it is certain that the propagation times TC3 and TC4 are smaller than the sum of these times, ie TC3 + TC4.

 FIG. 5 represents a state machine 7 which is an improvement on the state machine 6 of FIG. 4.

The state machine 7 also comprises a third register R7 having data inputs, a clock input, and outputs, the third register R7 making it possible to store a state variable EF. The data input of the first register R7 is connected to the output of the first combinational circuit Cg. The clock input of the first register R7 receives a clock signal HCk so that said register stores the future state variables EF during each active edge of the clock signal HCk. The outputs of the third register
R7 provide s7 control signals which correspond to some of the current state variables.

 A slave circuit 10 receives the control signals S6 and S7.

 The operation and advantages of the state machine 7 are the same as the state machine 6.

However in certain cases, the decoupling carried out with the third register R7 has the effect of reducing the size of the integrated circuit, this reduction being due to the suppression of the duplication of functional elements of the first and second combinational circuits caused by a duplication of equation in these two circuits, for the circuit of figure 5.

Claims (4)

 1. Integrated circuit comprising at least one state machine (5, 6, 7) which comprises  - a first register (R1, R3) for memorizing a state of the state machine (5, 6, 7) and supplying current state variables (EC) to outputs, the first register having furthermore data to be stored and a clock input for receiving a clock signal (HCk),  - a first combinational logic circuit (C1) having first and second inputs and outputs, the first inputs being connected to the outputs of the first register (R1, R3) to receive the current state variables (EC), the second inputs being connected to input terminals to receive input variables (I) and the outputs being connected to the data inputs of the first register (R1, R3) to provide future state variables (EF) to be stored in the first register on the next active edge of the clock signal,  characterized in that the state machine (5, 6, 7) further comprises  - a second register (R2, R4) for storing and supplying control signals (S5, S6) to outputs, the second register (R2, R4) further having data inputs to be memorized and a clock input for receive clock signal (HCk) l  - a second combinational logic circuit (C2, C4) having outputs connected to the inputs of the second register (R2, R4) to provide future control signals which will be stored in the second register (R2, R4) during a next active edge of the clock signal (HCk) .  2. Integrated circuit according to claim 1, characterized in that the second combinational circuit (C2) has inputs which are connected to the outputs of the first combinational circuit (C1) to receive the future state variable (EF).  3. Integrated circuit according to claim 1, characterized in that the second combinational circuit (C4) has first and second inputs, the first inputs being connected to the outputs of the first register (R3) to receive the current state variable (EC ), and the second inputs of the second combinational circuit (C4) being connected to the input terminals to receive the input variable (I).  4. Integrated circuit according to claim 3, characterized in that the state machine (7) further comprises a third register (R7) for partially storing a state of said state machine (7) and providing on an output control signals (S7) which correspond to state variables, the third register (R7) further comprising data inputs connected to the outputs of the first combinational circuit (C3), and having a clock input for receiving the clock signal (HCk).