FR2685585A1 - Electronic circuit for processing a digital value of a parameter - Google Patents

Abstract

The circuit (16) comprises decoding means (45) for producing incrementation and decrementation pulses on the basis of displacement signals (A, B) which are indicative of the displacement of a movable element, means (32) for counting and for storing the digital value (V), and display control means (80, 81) for producing display signals which are representative of a value related to the digital value stored in the counting and storage means (32). The counting and storage means (32) are arranged to receive a digital value presented at a data input/output port (33) during reception of a write control signal (WR), to modify the digital value as a function of the incrementation and decrementation pulses coming from the decoding means (45), and to address the digital value to the data input/output port (33) upon reception of a read control signal (RD). Use especially in digital potentiometers.

Description

 The present invention relates to an electronic circuit for processing a digital value of a parameter.

 In various applications, such as digital potentiometers, the numerical value of a parameter is modified during the displacement of a movable member, and a display representative of the numerical value thus modified is produced in real time. For this purpose, a displacement signal decoding circuit and a display control circuit connected to an outdoor unit are usually used, where the digital value of the parameter is stored. Such a configuration implies a centralization at the level of the external unit of the treatments applied to the numerical value. When a certain number of numerical values of parameters are thus treated simultaneously, such centralization can encumber the processing capacity of the outdoor unit. In addition, it involves a large number of connections because any movement of a movable member must be able to be detected at any time to correctly change the numerical value of the corresponding parameter.

 The object of the present invention is to propose a processing circuit for locally providing functions for storing, modifying, displaying control, reading and writing a numerical value of a parameter.

 The invention thus proposes an electronic circuit for processing a digital value of a parameter, characterized in that it comprises a data input / output port, a write control terminal, a control terminal for reading, a display signal output port, at least two displacement signal input terminals indicative of the displacement of a movable member, decoding means connected to the displacement signal input terminals to produce increment and decrement pulses on the basis of the displacement signals, digital value counting and storing means connected to the data input / output port, the write control terminal, the read command and the decoding means, and display control means connected to the counting and storage means and the display signal output port for producing display signals representative of a related value to the digital value stored in the counting and storage means, and in that the counting and storage means are arranged to receive a digital value presented to the input / output port of data when receiving a signal write command to the write control terminal, change the digital value according to the increment and decrement pulses from the decoding means, and address the digital value to the input / output port of data when receiving a read command signal at the read command terminal.

Other features and advantages of the present invention will appear in the following description of an exemplary embodiment, read in conjunction with the appended drawings, in which:
- Figure 1 is an axial sectional view of a potentiometer that may include a circuit according to the invention;
FIGS. 2 to 4 are perspective views of elements of the potentiometer shown in FIG. 1, the view of FIG. 3 having partial detachment;
- Figure 5 is an expanded view of a film attached to the movable member shown in Figure 3;
FIG. 6 is an overall diagram of an electronic circuit according to the invention;
FIG. 7 is a more detailed diagram of the circuit of FIG. 6;
FIG. 8 is a circuit diagram of part of the circuit of FIG. 7;
FIG. 9 is an electrical diagram of the mounting of the display diodes of the potentiometer; and
- Figure 10 is a diagram illustrating the connection of several circuits according to the invention to a computer.

 A digital potentiometer, such as that illustrated in FIGS. 1 to 4, is used to adjust the digital value V of a parameter. The potentiometer can for example be part of a mixer. In this case, the parameter may be an amplification gain relative to an audio track.

 The potentiometer illustrated in FIGS. 1 to 4 comprises a body 2, a movable member 3 and an electronic part 4.

 The body 2, metal alloy, consists of a tubular portion 5 and a base 6 (Figures 1 and 2). The base 6 is located at the base of the tubular portion 5 and around it. It comprises four holes 7 for receiving screws 8 for fixing the potentiometer on a support.

 The movable member 3 (Figures 1 and 3) has a generally tubular shape whose inner diameter is slightly greater than the outer diameter of the tubular portion 5 of the body 2. The movable member 3 is mounted around the tubular portion 5 of the body 2 and can rotate relative thereto. For mounting, it is possible for example to provide a ring 10 engaged in two annular grooves vis-à-vis, namely a groove 11 located outside the tubular portion 5 of the body 2 and a groove 12 located at the inside the movable member 3.

No mechanical stop is provided to limit the movement of the movable member 3. The latter therefore has an infinite freedom of rotation relative to the body 2.

 The electronic part 4 (FIGS. 1 and 4) comprises a printed circuit board 15 supporting an integrated circuit 16, and a block 17 on which fifteen light-emitting display diodes 18 are mounted. The block 17 is made of insulating resin molded to the end of the wafer 15. In the example shown in Figure 4, the display diodes 18 are housed in fifteen cavities provided near the periphery of the block 17 and distributed at regular intervals on an arc C of about 2700.

 The block 17 protects the display diodes 18 and their connections to the integrated circuit 16. The block 17 closes the front end of the tubular portion 5 of the body 2 opposite the base 6. It is secured to the body 2, by example by gluing. As a variant, the display diodes 18 could be mounted on a hybrid circuit covered with a plexiglass filter ensuring the good diffusion of the light emitted by the diodes 18 and protecting the diodes 18 and their connections to the integrated circuit 16.

 The printed circuit board 15 extends inside the tubular portion 5 of the body 2. It protrudes from the body 2 on the side of the base 6. On the protruding portion of the wafer 15 is a socket 19 allowing, by means of a cable 20, to connect the potentiometer to an external system. The surface of the printed circuit board 15 carries the integrated circuit 16, a light source emitting diode 22, two light-receiving diodes 23 and resistors and conductive tracks for the connection of the integrated circuit 16 to the socket 19, 18 for the connection of the potentiometer to the external system, the socket 19 and the cable 20 could for example be replaced by a second printed circuit board extending transversely to the axis of the tubular portion 5, mechanically connected to the wafer 15 and carrying, on its side opposite the wafer 15, a set of connecting pins. In this case, the base 6 of the body 2 will have the shape of a skirt surrounding this second printed circuit board.

 The transmitting and receiving diodes 22, 23 are part of encoding means further comprising a screen-printed film 24 (FIGS. 3 and 5) glued to the inside face of the movable member 3. If the movable member 3 is made of transparent material the film 24 can also be fixed on the outer face of the movable member 3. The film 24 comprises two periodic patterns 26 each constituted by an alternating succession of light reflecting zones 25 and non-reflecting zones. The reflective zones 25 may for example be in the form of bars serigraphed on a non-reflective film. The reflective and non-reflective zones are elongated along the axis of the movable member 3 and have the same width perpendicular to this axis. The two patterns 26 are slightly offset along the axis of the movable member 3.

They have the same periodicity and are shifted by a quarter period relative to each other perpendicular to the axis of the movable member 3.

 The three diodes 22, 23 are aligned along the axis of the tubular portion 5 of the body 2, the emitting diode being located in the middle of the two receiving diodes 23 (Figure 4). The emitting diode 22 radiates through an opening 27 formed in the tubular portion of the body 2 (Figure 2). The opening 27 has an elongated shape parallel to the axis of the tubular portion 5. The axial position of the movable member 3 is such that the two periodic patterns 26 of the film 24 are illuminated by the light from the emitting diode 22 and through the aperture 27. The two receiver diodes 23 are arranged to receive light passing through the aperture 27 after reflection on the reflective areas 25 of the periodic patterns 26.When a reflecting zone 25 of a periodic pattern 26 is located opposite a receiving diode 23, it receives the light from the emitting diode 22 and reflected by this zone 25. When the user rotates the movable member 3 relative to the body 2, the periodic patterns 26 run past the aperture 27 and the emitter diode 22, and selectively reflect the light emitted to the receiver diodes 23 through the aperture 27. The receiver diodes 23 then produce two signals. binary displacement A, B of the same period. These two displacement signals A, B are in phase quadrature relative to each other because of the shift of a quarter period between the two periodic patterns 26. The period of the displacement signals is indicative of the speed displacement of the movable member 3 and the sign of the quadrature phase shift is indicative of the direction of movement.

FIG. 6 represents a block diagram of the electrical means included in the potentiometer. The integrated circuit 16 comprises two displacement signal input terminals 30 respectively connected to the positive terminals of the receiving diodes 23 to receive the displacement signals A, B. The potential of the mass
GND and a positive potential UCC are supplied to the integrated circuit 16 via the socket 19 and are used to activate the emitter diode 22 and bias the receiver diodes 23.

 The integrated circuit 16 comprises counting and storage means 32, in which the numerical value V of the parameter, coded on N = 8 bits, is stored.

The counting and storage means 32 are connected to a data input / output port 33 of the circuit 16 via an 8-conductor line making it possible to transmit the digital value coded on 8 bits. The counting and storage means 32 are further connected to a write control terminal 34, a read control terminal 35, and a reset control terminal 36.

 In the example shown in FIG. 7, the counting and storage means 32 comprise an 8-bit synchronous counter 38, coupled to a tri-state buffer 39. The input of the buffer 39 receives the 8 bits stored in the counter 38. The output of the buffer 39 is connected to the data input / output port 33. The buffer 39 is further connected to the read control terminal 35 receiving an inverted read command signal -RD.

In the absence of a read control signal (RD = 0, -RD = 1), the buffer 39 is disconnected. When it receives the read command signal RD (-RD = 0), the buffer 39 sends the value V stored on 8 bits in the counter 38 to the data input / output port 33.

 The counter 38 is connected to the write control terminal 34 receiving an inverted write control signal -WR, and to the data input / output port 33.

When a write control signal WR is received at the write control terminal 34 (-WR = 0), the counter 38 takes the 8-bit coded digital value present at the data input / output port 33 The counter 38 is further connected to the reset control terminal 36. When a reset control signal CLR (CLR = 1) is received at the reset control terminal 36, the counter 38 resets the value stored digital V.

 The counter 38 also includes an incrementing input u and a decrement input d for modifying the stored digital value V. The value V stored in the counter 38 is increased by one unit when a logic level pulse 0 is received at the incrementing input u while the other input d is at logic level 1. The digital value V stored in the counter 38 is decreased by one unit when a logic level pulse 0 is received at the input of decrement b while the other input u is at logic level 1. The other cases of logic signals presented at the inputs u, d do not modify the stored value V.

 Minimum value detection means 40 are connected to the counting and storage means 32 and to the input of a logic gate 41. In the example shown in FIG. 7, the minimum value detection means 40 are a 8-input OR gate respectively connected to the 8 binary registers of the counter 38, and the logic gate 41 is a NAND gate whose input is connected to the output of the OR gate 40 and whose output is connected to the decrement input b of the counter 38. The OR gate 40 delivers a logic level signal 1 except when the value V stored in the counter 38 is zero, zero constituting the minimum value that can be stored. Thus, when the stored value V is equal to zero, the output of the NAND gate 41 is blocked at logic level 1, and the decrement input d of the counter 38 can not therefore receive a logic level pulse 0, which prevents the stored value from falling below below the minimum value.

 Maximum value detection means 42 are connected to the counting and storage means 32 and to the input of a logic gate 43. In the example of FIG. 7, the maximum value detection means 42 are a gate NO AND 8 inputs respectively connected to the 8 bit registers of the counter 38, and the logic gate 43 is a NAND gate whose input is connected to the output of the NAND gate 42. The NAND gate 42 delivers a level signal logic 1 except when the value V stored in the counter 38 is equal to 255, 255 = 28-1 constituting the maximum value that can be stored. Thus, when the stored value is equal to 255, the output of the NAND gate 43 is blocked at logic level 1, and the incrementing input u of the counter 38 can not therefore receive a logic level pulse 0, which prevents the stored value from rising above the maximum value.

 The integrated circuit 16 further comprises decoding means 45 which are connected to the displacement signal input terminals 30 and to an input terminal 44 of the circuit 16 receiving clock pulses CLK. At each rising or falling edge of one of the displacement signals A, B, the decoding means 45 produce an incrementation pulse or a decrement pulse of duration equal to that of a clock pulse CLK. The incrementing pulses are addressed to the incrementation inputs u and decrementation d of the counter 38 through the NAND gates 43 and 41, respectively.

The logic level incrementing pulses 1 are addressed to the second input of the gate
NO AND 43. This then transmits to the incrementation input u of the counter 38 a logic level incrementing pulse 0, unless the output of the NAND gate 42 is at logic level 0, it is that is, unless the stored value is equal to the maximum value 255.

Logic level decrement pulses 1 are addressed to the second input of the gate
NO AND 41. This then transmits to the decrement input d of the counter 38 a logic level decrement pulse 0, unless the output of the OR gate 40 is at the logic level 0, that is, say unless the stored value is equal to the minimum value 0.

In the example shown in FIG. 7, the decoding means 45 comprise four edge detection cells 46 to 49, and comparison means comprising eight NAND comparison gates 50 to 57 and two NAND gates for determining direction. 58, 59. The edge detection cells 46 to 49 detect the rising and falling edges of each of the displacement signals A, B and produce corresponding edge detection pulses. The comparison means compare each edge detection pulse corresponding to one of the displacement signals A,
B, and produce an incrementation or decrementation pulse depending on the result of the comparison.

 The edge detection cell 46 is shown in FIG. 8. It comprises two D flip-flops 61, 62, each having an inverted reset input -R1, -R2 connected to the input terminal 30 of the displacement signal A. first flip-flop D 61 receives clock pulses CLK at its clock input CLK 1. The inverted output -Q1 of the first flip-flop D 61 is connected to the clock input CLK2 of the second flip-flop D 62 and to an input of an AND gate 63. The inverted output of the second flip-flop D 62 is connected to the other input of the AND gate 63. The output of the AND gate 63 is connected to the control input d1 of the first D flip-flop 61.

The control input d2 of the second flip-flop D 62 is raised to the positive potential UCC. The output Q1 of the first flip-flop D 61 provides the output signal AU of the edge detection cell 46.

When the displacement signal A is at logic level 0, the two flip-flops D 61, 62 are reset (-R1 = -R2 = 0) at each clock pulse and the output signal AU is at logic level 0. Both inverted outputs -Q1, -Q2 are at level 1 and the AND gate 61 applies a level 1 to the control input d1 of the first D flip-flop 61. When the displacement signal A changes from level 0 to level 1 (rising edge ), the flip-flops D 61, 62 are no longer reset and the first edge of the clock signal
CLK makes the output Q1 conform to the control input d1, so that the output signal AU goes to level 1.

Simultaneously, the inverted output -Q1 goes to level 0, which also changes state the second flip-flop D 62 and the AND gate 63 which then applies a level 0 to the control input dl of the first flip-flop D 61. At the second edge of the clock signal CLK, the first flip-flop
D resets its output Q1 and the signal AU according to its control input d1. But the second flip-flop D 62 does not change state because its control input d2 remains at level 1 imposed by the positive potential UCC. Consequently, the inverted output -Q2 remains at level 0, as well as the output of the AND gate 63 applied to the control input d1 of the first D flip-flop 61.

 In summary, the edge detection cell 46 produces a logic level AU output signal 0, except when a rising edge of the displacement signal A is produced which causes a logic level 1 edge detection pulse in the output signal AU, whose width is equal to that of a clock pulse CLK.

 The other three front detection cells 47, 48, 49 are identical to the cell 46 described with reference to FIG. 8. The input of the cell 47 is connected to the input terminal 30 of the displacement signal B, so that it produces a logic level 1 edge detection pulse upon the appearance of a rising edge of the displacement signal B. The input of the cell 48 is connected to the input terminal 30 of the signal of A displacement via an inverter 65, so that it produces a logic level 1 edge detection pulse at the appearance of a falling edge of the displacement signal A.The input of the cell 49 is connected to the input terminal 30 of the displacement signal B via an inverter 66, so that it produces a logic level 1 edge detection pulse when a front appears. descending from the movement signal B.

 By comparing any edge detection pulse relative to one of the displacement signals A, B to the other displacement signal, it is possible to determine the direction of movement of the movable member 3 and to control a corresponding incrementation or decrementation of the stored numeric value.

Eight situations are possible. Four of these situations translate a negative direction of movement: rising edge of B when A = 1, rising edge of A when B = 0, falling edge of B when A = O, and falling edge of A when B = 1. These four situations are detected by the doors respectively
NO AND COMPARISON 50 to 53 whose outputs are connected to the input of the NAND-determining negative-direction gate 58 whose output produces the logic-level decrement pulses addressed to the input of the NAND gate 41.

The other four situations translate a direction of positive displacement: falling edge of A when
B = 0, falling edge of B when A = 1, rising edge of B when A = 0, and rising edge of A when B = 1.

These four other situations are detected respectively by the comparison NAND gates 54 to 57 whose outputs are connected to the entrance of the door.
NO AND positive direction determination 59 whose output produces the logic level incrementing pulses 1, addressed to the input of the NAND gate 43.

Each cell 46 to 49 detecting edges of one of the displacement signals A, B has its output connected to a comparison NAND gate further receiving the other displacement signal at its input, and to a NAND gate for comparison. further receiving the other inverted displacement signal at its input. Of these two doors
NO and comparison, one is connected to the NEU gate of negative direction determination 58 and the other is connected to the positive direction NAND gate 59.

 When the two displacement signals A, B are at constant logic levels, the four cells 46 to 49 have a level 0 output. Therefore, the eight comparison NAND gates 50 to 57 have a level 1 output and the two NAND direction gates 58, 59 have a level 0 output.

A rising or falling edge of the signal A or B causes a level 1 pulse at the output of one of the cells 46 to 49. Only one of the eight comparison NAND gates 50 to 57 then delivers a logic level pulse 0 and this results in a decrementing or incrementing pulse at the output of the corresponding NAND direction determining gate 58 or 59.

 The decoding means 45 described above are particularly advantageous because they produce a decrementation or incrementation pulse for each of the rising or falling edges of each of the phase quadrature displacement signals A, B. For the same signal period in phase quadrature A, B, the sensitivity of the response is thus increased by a factor of 4 with respect to a conventional decoder which delivers only one incrementation or decrementation pulse per period.

 The high sensitivity of the decoding means 45 makes it possible to limit the number of serigraphed bars 25 of the periodic patterns 26 situated on the movable member 3.

This facilitates the realization of periodic patterns 26, especially when the movable member 3 has a relatively small size.

The integrated circuit 16 comprises a table bis latch 70 whose output is connected to an output terminal 71 of the circuit 16 producing a two-state output signal BUSY. The latch 70 includes two doors NO
And 72, 73 (Figure 7). The NAND gate 72 has two control inputs connected to the output of the NAND gates 41 and 43 and receiving the decrement and decrement pulses of logic level 0. A third input of the NAND gate 72 is connected to the output of the NAND gate. the door
NO AND 73. The NAND gate 73 has three control inputs connected to the write control terminal 34, the read control terminal 35, and the reset control terminal 36 through a remote control. inverter 74. A fourth input of the NAND gate 73 is connected to the output of the NAND gate 72.The output signal
BUSY is provided by the output of the NAND gate 72. This BUSY signal takes logical state 1 after receiving an increment or decrement pulse, and logic state 0 after a write command (- WR = 0), read (-RD = 0) or reset (-CLR = 0).

Therefore, BUSY = 1 indicates that the numeric value
V stored in the counter 38 has been modified by moving the movable member 3 since the last command write, read or reset.

The integrated circuit 16 further comprises display control means 80, 81 mounted between the counting and storage means 32 and a display signal output port 82, 83 (Fig. 6). These display control means comprise means 80 connected to the bit registers of the counter 38 for determining a value W coded on M = 4 bits (sl-s4) as a function of the numerical value V coded on N = 8 bits in the counter 38, and shaping means 81 receiving the value
W coded on 4 bits and producing display signals xl-x4 and yl-y4 representative of this value W for displaying the value W on the 2M-1 = 15 display diodes 18.

The means 80 determining the value W comprise (FIG. 7) an adder 85 on M = 4 bits, an input on M bits (b1-b4) receiving the M = 4 most significant bits of the counter 38 and the other input on
M bits (a1-a4) a M1 = 3 most significant bits (a2-a4) connected to the ground and the least significant bit (a1) connected to the output of an AND gate 86.

 An input of the AND gate 86 is connected to the output of a NAND gate 87 having M = 4 inputs connected to the M = 4 most significant bit registers of the counter 38. The other input of the AND gate 86 is connected to the output of a NAND gate 88. The NAND gate 88 has an input connected to the bit register of the counter 38 having the rank weight M + 1 = 5 via an inverter 89, and another connected input at the output of a NAND gate 90. The NAND gate 90 has M = 4 inputs respectively connected to the M = 4 most significant bit registers of the counter 38 via M = 4 inverters 91.

Thus, the value W coded on 4 bits sl-s4 at the output of the adder 85 is given by:
W = 1 when 0 5 V <24
W = k, with 1 <k <15, when
16 k - 8 s V <16 k + 8
W = 15 when 232 # V <256
N and M can of course make values other than N = 8 and M = 4, provided that N 2 M in the general case, means similar to the means 80 described above will give ::
W = 1 when 0 s V <2N-M + 2N-M-1
W = k, with 1 <k <2M-1, when
k2N-M, 2N-M-1s V <k2N-M + 2N-M-1
W = 2M-1 when 2N ~ 2N-M ~ 2N-M-1g V <2N
The shaping means 81 comprise two multiplexers 92, 93. The multiplexer 92 has two inputs receiving the two most significant bits s3, s4 of the value.
W. It produces four two-state yl-y4 signals, namely a disconnected state and a GND ground state. The multiplexer 93 has two inputs receiving the two low-order bits s1, s2 of the value W. It produces four xl-x4 two-state signals, namely a state connected to the ground GND and a state connected to the positive potential UCC. The multiplexers 92, 93 each have a control input connected to an input terminal 94 of the circuit receiving an inverted inhibition signal -INH. The reception of an inhibition signal INH (-INH = 0) by the multiplexers 92, 93 blocks their outputs xi-x4, yl-y4 to prevent the display on the diodes 18.

 The electrical assembly 95 of the 2M-1 = 15 display diodes 18 is shown in FIG. 9. It is a matrix arrangement 95 in which the signals x1-x4 correspond to the abscissae and the signals y1-y4 correspond to the ordered. The positive input of each diode 18 is connected either to the ground or to the potential UCC as a function of one of the signals xi-x4. The negative input of each diode 18 is either disconnected or connected to ground through a current limiting resistor 96 as a function of one of the signals y1-y4.

Each value W is represented, at the output of the formatting means 81, by a xl-x4 abscissa signal and by an yl-y4 ordinate signal. The diode 18 relating to a value W is lit when the corresponding abscissa x1-x4 is connected to the positive potential UCC and the corresponding ordinate y1-y4 is connected to ground.

There is no diode 18 at the intersection of abscissa xl and ordinate yl, which would correspond to
W = 0. Indeed, it has been planned to display the value W on an odd number 2M-1 = 15 of diodes 18, so that a central point represented by the diode 18 corresponding to W = 2M- i = 8. With the arrangement of the display diodes 18 shown in FIG. 4, the diodes 18 corresponding to the increasing values of W can be placed successively along the circular arc C, in the clockwise direction of a shows. For the display of a value W, it is possible either to light only the diode corresponding to the value W, or to turn on all the diodes corresponding to the values lower than or equal to W.

 The integrated circuit 16 described above performs both functions of storage, modification consecutive to the displacement of the movable member 3, writing, reading and display of a digital value V of a parameter. The writing of a numerical value in the counting and storage means 32 is independent of the displacement of the movable member 3. The embodiment of the circuit 16 in integrated form advantageously allows it to have a reduced size (typically 6 mm 2) . It can then be housed inside the tubular portion 5 of the body 2 of the potentiometer, which typically has an inside diameter of the order of 6 mm.

 In the application of the invention to a mixer, a number of potentiometers are connected to a computer via their jacks 19. Figure 10 illustrates the connection of the integrated circuits 16 of several digital potentiometers to a calculator outside 100.

The data input / output ports 33 of the circuits 16 are connected to the computer 100 via a data bus 101. The write control 34 and read 35 input terminals are connected to the computer via a control bus 102. associated with an address selector provided in the computer 100. The input terminals 44, 36, 94 of the circuits 16 respectively receiving the clock pulses CLK, the reset control signal CLR, and the inverted inhibition signal
INH are connected to the computer 100 by common parallel lines 103, 104, 105. Thus a reset command (CLR = 1) resets all the digital values stored in the various circuits 16 connected to the computer 100, and a deletion command display (-INH = 0) inhibits the display on all the potentiometers connected to the computer 100.

 The output terminals 71 of the BUSY signals are connected to the computer 100 by a line 106. This line 106 may be a bus associated with an address selector provided in the computer 100, to identify each circuit 16 transmitting BUSY signals indicative of the displacement. of a movable member 3. The line 106 may also be a common parallel line. In the latter case, the two states of the signal BUSY must be converted so that the state consecutive to the displacement of the movable member is a state disconnected in three-state logic, which makes it possible to detect at the level of the computer 100 that the one of the associated circuits 16 sends a BUSY signal.

 The computer 100 is equipped with software providing other treatments using the digital values set using the potentiometers. The reception of BUSY signals allows it to manage the priorities between the two independent ways of modifying the digital values stored in the circuits 16.

For example, it is possible to give priority to changes by moving the movable member 3 relative to the write commands via the data bus 101. For this purpose, the transmission of the write control signal WR is prevented when the corresponding BUSY signal is present, the BUSY signal having to be modified first by issuing a read control signal
RD which informs the computer 100 on the latest modifications entered manually by the user.

 Although the invention has been described with reference to a particular embodiment, it will be understood that various variants can be made to this example without departing from the scope of the invention.

Claims (14)

 An electronic circuit (16) for processing a digital value (V) of a parameter, characterized in that it comprises a data input / output port (33), a write control terminal (34), a read control terminal (35), a display signal output port (82, 83), at least two input signals (30) of displacement signals (A, B) indicative of the moving a movable member (3), decoding means (45) connected to the displacement signal input terminals (30) to produce incrementation and decrement pulses on the basis of the displacement signals (A, B), digital value counting and storage means (32) connected to the data input / output port (33), the write control terminal (34), the read command (35) and the decoding means (45), and display control means (80, 81) connected to the counting and storing means (32) and the signal output port of display (82, 83) for producing display signals representative of a value (W) related to the digital value (V) stored in the counting and storage means (32), and in that the counting means and storage (32) are arranged to receive a digital value presented at the data input / output port (33) upon receipt of a write control signal (WR) at the write control terminal (34), changing the numerical value (V) according to the incrementation and decrement pulses from the decoding means (45), and addressing the numerical value (V) to the data input / output port (33) when receiving a read command signal (RD) at the read control terminal (35).  2. Circuit according to claim 1, characterized in that the decoding means (45) are arranged to process displacement signals (A, B) in the form of two binary signals in quadrature phase.  3. Circuit according to claim 2, characterized in that the decoding means (45) comprise edge detection means (46 to 49) for detecting the rising and falling edges of each of the displacement signals (A, B). and generating corresponding edge detection pulses, and comparing means (50 to 59) for comparing each edge detection pulse corresponding to one of the displacement signals (A, B) to the value of the other one of the displacement signals and to produce an incrementing or decrementing pulse depending on the result of the comparison.  4. Circuit according to claim 3, characterized in that the edge detection means comprise, for each of the displacement signals (A; B), two edge detection cells (46,48; 47,49) connected to the input terminal (30) of said displacement signal (A; B), one (46; 47) of these two cells generating an edge detection pulse upon the occurrence of a rising edge of said displacement signal (A; B), the other (48; 49) of these two cells producing an edge detection pulse when the occurrence of a falling edge of said displacement signal (A; B).  5. Circuit according to claim 4, characterized in that the two edge detection cells (46, 48, 47, 49) relating to a displacement signal (A; B) are identical, one (48; ) of these two cells being connected to the input terminal (30) of said displacement signal (A; B) via an inverter (65; 66).  6. Circuit according to one of claims 4 or 5, characterized in that the comparison means comprise eight comparison logic gates (50 to 57) and two logical sense-determining gates (58, 59), in that for each of the quadrature phase shift signals (A; B), the output of each of the two corresponding edge detection cells (46,48; 47,49) is connected to the input of two of the logic gates of comparison (50 to 57), one of these two comparison logic gates further receiving the other displacement signal at its input, the other of these two comparison logic gates further receiving the other inverted displacement signal at its input, so that one of these two logic gates produces pulses indicative of a displacement of the movable member (3) in a positive direction and that the other of these logic gates produces pulses indicative of a displacement of the movable member (3) in a negative direction f, in that the outputs of the four comparison logic gates (54 to 57) producing pulses indicative of a displacement of the movable member (3) in a positive direction are connected to the input of one of the logic gates direction determining means (59) whose output produces said incrementing pulses, and in that the outputs of the four comparison logic gates (50 to 53) producing pulses indicative of a displacement of the movable member (3) in a negative direction are connected to the input of the other logic sense gate (58) whose output produces said decrement pulses.  7. Circuit according to one of claims 1 to 6, characterized in that it comprises minimum value detection means (40) connected to the counting and storage means (32) and to the input of a logic gate (41) having another input receiving the decrement pulses and an output connected to the counting and storage means (32), this logic gate (41) transmitting the decrement pulses to the counting and storage means (32) except when the minimum value detecting means (40) produces a signal indicating that the stored digital value (V) is equal to a minimum value.  8. Circuit according to one of claims 1 to 7, characterized in that it comprises maximum value detection means (42) connected to the counting and storage means (32) and to the input of a logic gate (43) having another input receiving the incrementing pulses and an output connected to the counting and storage means (32), this logic gate (43) transmitting the incrementation pulses to the counting and storage means ( 32) except when the maximum value detecting means (42) produces a signal indicating that the stored digital value (V) is equal to a maximum value.  9. Circuit according to one of claims 1 to 8, characterized in that it comprises a bistable flip-flop (70) whose output is connected to a terminal (71) of the circuit producing an output signal (BUSY) to two states, namely a state controlled by first control inputs of the flip-flop (70) receiving the incrementation and decrement pulses, and a state controlled by second control inputs of the flip-flop (70) connected to the control terminals writing and reading (34, 35).  10. Circuit according to claim 9, characterized in that it comprises a reset control terminal (36) connected to the counting and storage means (32) and to one of said second control inputs of the flip-flop (70). ).  11. Circuit according to one of claims 1 to 10, characterized in that the display control means comprises means (80) for determining a value (W) coded on M bits according to the stored digital value ( V) encoded on N bits in the counting and storage means (32), M and N denoting integers with M 5 N, and formatting means (81) connected to said means (80) for determining a value M bit encoded and the display signal output port (82, 83) for shaping display signals (x1-x4, y1-y4) representative of said M-bit encoded value (W).  Circuit according to Claim 11, characterized in that the said means (80) for determining a value coded on M bits are arranged so that:  W = 1 when 0 s V <2N-M + 2N M-1;  W = k, with 1 <k <2M-1 when  k2N-M-2N-M-1S V <k2N-M + 2N-M-1; and  W = 2M - 1 when 2N-2N-M-2N-M-1 S V <2N  V designating said stored digital value coded on N bits, and W said value coded on M bits.  13. Circuit according to one of claims 11 or 12, wherein N = 8 and M = 4.  14. Circuit according to one of claims 1 to 13, characterized in that it is embodied as a single integrated circuit (16).