FR2605131A1 - Frame scanning digital display system - Google Patents

Abstract

A frame scanning graphic display system in which all the points can be addressed according to two operating modes. In the first mode, data are extracted from a revision memory M0 to M3, serialised, modified and applied to a display device at a first frequency. In the second mode, the data are extracted from the revision memory, serialised and partially modified at the said first frequency and are then further modified and transferred to the display device at an even sub-harmonic, for example a half, of the first frequency. The additional modification comprises the chaining of successive groups of display data bits. Consequently, when the frame scanning device operates at a constant scanning speed, the first mode provides high definition for the image elements but a relatively low colour definition display and the second mode provides a display with an even sub-multiple, for example half, of the definition of the image elements but with a considerably higher colour definition.

Description

The present invention relates to digital display systems and more particularly to systems which use a raster scanning display device.

Digital display systems for use with computing systems are well known in the prior art. In many graphics systems equipped with. raster scanning devices, the system is used in which all points are addressable or bitmap. In this system, the data is arranged in a revision memory so that when it is read as output for display, successive groups of data leaving the memory directly relate to successive image elements on the display. One of the oldest descriptions of such a system can be found in an article titled "Computer Graphics In
Color "by Peter B. Denes published in the journal" Bell Laboratories Record "by
May 1976, pages 139 to 146. Many common microcomputer systems use the system in which all points are addressable to generate graphical displays. An example is the IBM Personal Computer when it includes a color graphics adapter card (CGA) or an enhanced graphics adapter card (EGA).

Most known systems can be switched to give different display definitions including different numbers of image elements per total image analysis frame, different numbers of display lines and different numbers of colors available per element. picture. However, none of these prior art systems has used a switchable arrangement between a first mode in which data is extracted from a revision memory at a given frequency and transmitted to the display at the same frequency and a second mode in which the data is extracted from the memory at this same frequency but transmitted to the delay device at a frequency which is an even divider, for example half, of the extraction frequency. A digital display system produced according to the teachings of the present invention comprises a revision memory for storing digital data defining display image elements and means for connecting data read in the revision memory into groups of image element signals for display. The system includes switching means for switching from a first to a second mode. In the first mode, the data is read from memory, amended and applied to the display device at a first frequency. In the second mode, the data is read from the memory and initially converted to said first frequency, but is finally converted and applied to the display device at an nth sub harmonic (for example half) of said first frequency. mode, successive groups of data derived from memory are combined to form the display control signals.

Figure 1 is a schematic representation of a digital display adapter for connecting a central processing unit to a frame scanning display device.

Figure 2 is a detailed diagram of the doors and a combination circuit used in the system of Figure 1.

FIG. 3 is a schematic representation of a selector circuit used in the system of FIG. 1.

FIG. 4 represents the data content of the shift registers used in the system of FIG. 1 in an operating mode thereof.

Figure 1 is a schematic representation of a digital display system implementing the teachings of the present invention. The system has input lines that are connected to a central processing unit (not shown) and output lines that are connected to a CRT display device (not shown). The system includes a revision memory composed of four planes 10-13 for the respective storage of the data representing the different color components of the signals to be displayed. Thus, for example, the plane MO (10) stores components of red, the plane M1 (11) of the components of green, the plane M2 (12) of the components of blue and the plane M3 (13) of the components of intensity . The data is stored in the revision memory in the configuration of all addressable points (APA). In this configuration, bytes of data are arranged in the planes at the locations corresponding to the positions of the image elements on the cathode ray tube display. Thus, for example, at the start of a cathode ray tube (CRT) scan, four selected bytes are read simultaneously from identical locations in each of the planes of the revision memory, one byte per plan. These bytes are normally used to define the color and / or intensity of the first eight image elements of the display. Then the bytes at an address immediately following the address read initially, are read to define the color and / or the intensity of the next eight image elements of the display. This process continues until all image elements have been defined and displayed. Depending on the definition of the display and the capacity of the revision memory, the data for a display frame can either fill the revision memory, or be stored in a part of the addressable locations in this one. In the first case, the initial address for a display frame is the first address of each plane of the revision memory. In the second case, the initial address for a display frame can be chosen at an address selected in the revision memory. By changing this initial address from frame to frame, sequence and animation functions can be ensured. The sequential revision memory addresses for reading the display data from this memory are generated by a cathode ray tube control system (CRTC) 14 and applied to the revision memory by the 20 address lines 15. CRTC 14 can be of the MC6845 type manufactured by MOTOROLA Inc. and can be controlled in a known manner by input signals on lines not shown and comprising clock and control lines, from the central unit treatment. To simplify the explanation, the direct connections between the revision memory and the central processing unit have not been shown. These connections would obviously include the connections of the data bus and the address bus to the address lines 15 through a multiplexing system. These connections allow the central processing unit to access the revision memory to insert and update data to be displayed.

The present invention relates to an arrangement for using the data contained in the revision memory to provide different display resolution signals, both as a function of the number of image elements in a display frame and of the number of colors available for each image element. For example, three switchable resolutions will be described, the first two allowing a display of 640 x 200 image elements with 16 or 64 colors per element, respectively, and the third allowing a display of 320 x 200 image elements with 256 colors per element.

First of all, the operation of the system is switched by means of the mode signals on the lines 16 coming from a register 38 which receives and retains mode control signals coming from the central processing unit, in mode at 640 x 200 image elements and 16 colors. In this mode, the selection circuit 17 has no effect on the signals which pass through it. Consequently, for each access to the revision memory, a group of four bytes of data, one byte from each plane of the revision memory, is fed without change to the shift registers 21 to 24. The shift registers 21 to 24 are synchronized together by chronology signals on a line 25 originating from the CRTC system 14 to serialize the received bytes. The serial outputs of the shift registers are synchronized through synchronization gates 26 to 29 to provide 4-bit inputs parallel to a pallet register system 31. This register system comprises sixteen registers which can be loaded from the unit central processing unit (through data and control lines not shown) and selected by the 4-bit inputs. Each register stores 6 bits. The 6-bit outputs are applied to a 6-bit door 32 and are synchronized from this door by clock signals on line 25, to another 6-bit door 33. The outputs of the two doors 32 and 33 are applied through lines 34 and 39, respectively, to a combination circuit 35. The combination circuit also receives 4-bit color selection signals from a register 36 through lines 40.

These color selection signals are applied to the register 36 from the central processing unit by the input lines 37. The combination circuit is controlled by mode signals from the mode register by lines 16. FIG. 2 is a schematic representation of an embodiment of the combination circuit 35. This figure shows the gates 32, 33 and the register 36 of FIG. 1 with their respective outputs at six, six and four lines 34, 39 and 40. These lines are selectively connected to the eight-bit gates 45, 46 and 47 whose eight-bit outputs are applied by lines 41, 42 and 43 to a common output 44. A selection circuit 48 responds to the mode input signals from the register 38 (Figure 1) by lines 16 to selectively provide an output on one of its three output lines 51, 52 or 53, which thus conditions one of the doors 45, 46 or 47. When the door 45 is conditioned, four bits from gate 32 and four b its from gate 33 are transferred to output lines 44. When gate 46 is conditioned, six bits from gate 33 and two bits from register 36 are applied to egress lines 44. When gate 47 is conditioned, four bits of gate 33 and four bits of register 36 are applied to the output lines 44. These different outputs correspond to the three operating modes of the system of FIG. 1 as defined by the mode signals applied to register 38. Referring to again in FIG. 1, it can be seen that the output of the combination circuit 35 on the lines 44 is applied to a door 54. This door is synchronized either at the clock frequency of the signals on the clock line 25 coming from the system CRTC 14, halfway through this frequency.

This half frequency is developed by a locking circuit 55 which is synchronized by the clock line 25 and has its output -Q reconnected to its input D. The free input of the locking circuit 55 is connected to a conditioning line d display (DISPEN) which will be described later.

A selection circuit 56 determines whether the full-frequency or half-frequency clock cadence signals are applied to the gate 54 in response to mode signals from the mode register 38. As will be seen more clearly later , the half frequency chronology is used with the output of gate 45 (Figure 2), that is to say with color outputs comprising four bits of each of the registers 32 and 33 and the entire frequency chronology is used with the other operating modes of the system.

The eight-bit signals passing through gate 54 are used to control a color look-up table (CLUT) 58. This includes 256 18-bit registers that can be selected by the eight-bit input signals.

Of the eighteen bits of the registers, six control a red digital / analog circuit 59, six others control a green digital / analog circuit 60 and the last six control a blue digital / analog circuit 61 which respectively deliver red analog output signals, green and blue to control a CRT display.

As indicated above, we will now consider the operation of the system in 640 x 200 image elements and 16 colors mode. This mode corresponds to the selection of register 47 (Figure 2) to deliver outputs to the CLUT table 58 at the entire clock frequency, i.e. the CRTC clock output is directed without change to the gate d clock 54.

In this mode, the color selection register 36 provides 4 bits of the CLUT address signals, these remaining constant for given periods in order to define different ranges of colors to be displayed during each of these peridoes. The remaining 4 bits of the CLUT address come from register 33 and are therefore determined by the contents of the plans of the revision memory and the pallet system. The clock frequency of CRTC 14 corresponds to the frequency of the revision of the picture elements on the cathode ray tube so that each line of picture elements on this tube is displayed in turn. This mode with four variable bits for each image element, allows sixteen different display colors.

In another mode in operation when the gate 46 of FIG. 2 is selected and again using the entire frequency chronology, 640 x 200 image elements are again displayed. In this mode, however, there are only two fixed bits of the color selection register 36 and gate 46 receives all six color bits from gate 33. Consequently, in this mode, with six variable bits for each image element, sixty-four different colors can be displayed.

In the system described so far, the revision memory, the parallel / serial shift registers 21 to 24, the palette system 31, the color search table 58 and the digital / analog conversion circuits 59 to 61 make all part of known digital display systems.

The display system of the present invention differs mainly from those known in the prior art by the combination of the two doors 32 and 33 of FIG. 1, of the door 45 of FIG. 2 and of the door 54 of FIG. 1 which controls the clock frequency which is selected for the chosen mode. In the present embodiment, all of these elements come into play to produce a display of 320 x 200 image elements each with a choice of two hundred and fifty colors.

In the present embodiment, the mode with 320 × 200 image elements is the third mode that can be selected. In this mode, it is the door 45 (FIG. 2) in the combination circuit which is selected and the half clock frequency coming from the flip-flop 55 which is selected by the selector 56 to control the door 54.

In operation in the third mode, the data is read from the revision memory, passed into the parallel / serial shift registers 21 to 24 and the gates 26 to 29 at the entire clock frequency. The gate outputs address the pallet register system 31 which applies its six-bit outputs to the gates 32 from where they pass to the gates 33 at the entire clock frequency. Four bits from each of these gates form the eight-bit output from gate 45 (Figure 2) which is applied by lines 44 to gate 54. This gate now operates at a frequency equal to half the clock frequency circuits up to this point. Consequently, this gate is crossed by each alternating group of eight bits coming from gate 45 and going to table CLUT 58 or, in other words, the output current of the 6 bits coming from the system at palette 31, four bits of each even numbered output and four bits of each odd numbered output, are combined to form each table entry
CLUT. Since there are at least eight variable bits and no fixed bit of register 36 is used, each group of bits addresses any one of the 256 registers of table CLUT 58. Consequently, each image element displayed can have any of the 256 colors. If the display is scanned at the same frequency as previously, dividing the address frequency of the CLUT table from gate 54 by two means that only half of the number of image elements is formed. Thus, the cathode ray tube will now display 320 x 200 image elements but each element will be selected from 256 colors.

In the description above, the functions and the structure of the selection circuit 17 of FIG. 1 were omitted for the purpose of simplification. This circuit is a highly desirable, although not essential, part of the display system. It is effective in the low definition mode of image elements described as the third mode above. Given the storage requirements of the revision memory, it is clear that without modification of the system, each pel element displayed will be divided from the two corresponding bits originating from each of the revision memory plans 10 to 13, in other words, in each plane, each stored byte includes a quarter of the data for each image element of four image elements. Previously and in the first and second modes of the present system, each byte stored in a plane contained one bit of each of the eight groups of image element data. Consequently, to modify the data for a single pel element, it is necessary to use bit manipulation techniques. However, these techniques become complex when pairs of bits have to be manipulated.

The selection system 17 allows the revision memory to contain bytes in each plane, each byte containing two sets of four bits of image element data. In the first and second modes, the selection circuit transfers the data from the revision memory without change, and this element data. images are stored as before, each byte in a plane containing eight bits each representing a bit of different image element data. In the third mode, the data is stored in the form of bytes each containing two groups of four bits of image element data. These bytes are read from corresponding locations in consecutive planes. For example, if the first location to be read as output for display is 0, the first byte is read from location 0 in plane 0, the next from location 0 in plane 1 followed by location O in plane 2, etc. So that both CPU and CRTC access the revision memory, the two lower order address bits now define the selected plane , thus causing the whole plans to chatter.

FIG. 3 represents an embodiment of the selection system 17 of FIG. 1. At the top of FIG. 3, four memory data registers 62 to 65 are shown connected to receive data from the memory planes MO to M3, respectively. The data registers are connected through sets of doors 66 to 69 or 70 to 73, to the shift registers 21 to 24. Signals on a mode line 51 (see Figure 2) which are generated for the mode of display 320 x 200, with 256 colors, are connected to doors 66 to 69. Signals which are generated for the other modes (that is to say those generated on lines 52 and 53 of FIG. 2), are used to condition the doors 70 to 73. In the high definition modes of image elements, that is to say the modes with 640 x 200 display elements, the signals of the registers 62 to 65 are transferred through the doors 70 to 73 to shift registers 21 to 24 without modification. In low definition mode of the display elements, each gate 66 to 69 transits two bits from each of the registers 62 to 65 to each of the shift registers 21 to 24. In other words, each shift register receives four groups of two bits , each group being from a different memory plan.

Figure 4 shows the bit transfer arrangement. This figure shows the four shift registers 21 to 24 with the output lines in series to the right of each register. In each register stage of FIG. 4, the data content is referenced n / m, n representing the memory plane and m representing the location of the bits of a byte read in this plane.

It will be recalled that in display mode 320 × 200, the color of each image element is defined by eight bits comprising two consecutive groups of four bits each coming from the shift registers. By examining the bit configuration of FIG. 4, we see that the first two groups of four bits read in the shift registers, include a complete byte of data from the revision memory plan 0. This byte is followed by bytes memory plans 1, 2 and then 3. Thus, the revision memory plans can be chained with each byte in a plane representing the data for a complete image element. As indicated above, the planes can then have bytes of consecutive image elements in sequence, which means that they are read from planes 0 to 3 and then return to plane 0.

In the preceding description of FIG. 1, it was indicated that the entry
DISPEN at scale 55 on line 57 would be explained later. The purpose of this input is to ensure in 320 x 200 picture element mode that the correct signals are applied from gates 32 and 33 through the combination circuit 35 to the CLUT table 58. The DISPEN signal is a signal generated by CRTC 14 to indicate the moment when the display must be conditioned. In other words, it defines the part of each scan line of the display that is modulated by the image element data. In order to ensure that the correct pairs of four bit groups are used, the DISPEN signal keeps the flip-flop unconditioned until the start of the display part of a scan line. Then the flip-flop is switched to generate a signal transfer through the selection unit 56 to door 54 at the second whole frequency clock cycle, that is to say when data has been transferred through door 32 to door 33.

Thus, the first picture element of the scanned line is defined by the first two groups of four-bit data.

In summary, a digital display system has been presented for controlling a frame scanning display device. The image element data is retained in a display memory in a form which can be addressed at any point in which the arrangement of the data in memory corresponds to the positions of the pel elements on the display device. Although the frame rate remains the same, data flow to the display can be set to the first frequency or to half that frequency.

With the first frequency, a high resolution display of the image elements and a limited number of colors is obtained. With the half frequency, the resolution of the image elements is reduced by half but by using pairs of groups of successive color signals for each image element, the resolution of the color is improved significantly. For efficient use of revision memories in high-resolution image mode, the known system for reading byte bytes from multiple memory planes is used, each byte containing bits relating to a color component of the pel elements. In low resolution image mode, each byte in the revision memory corresponds to a single image element and the memory planes are chained. A selection circuit between the memory and parallel / serial converters connected to the memory planes, is switched to ensure appropriate data paths between the memory and the converters.

Although particular values have been used to define the various operating modes of the system, it is obvious that other values could be used, for example 640 x 200 image elements, 4 colors and 320 x 200 image elements, 16 colors, provided that the number of image elements in one mode is twice the number of elements in a second mode. For both modes, the speed of the display scan can be the same. In addition, by modifying the system by increasing the number of doors between the paddle damper and the combination circuit, it is possible to use modes in which the picture elements can vary by more than double. For example, with three of these gates, operating modes at a first frequency at half this frequency and at a quarter of this frequency can be used with bit definitions of corresponding picture elements.

Although the present invention has been more particularly described with reference to a preferred embodiment thereof, it is obvious to those skilled in the art that various other modifications of forms and details can be made without departing from it. of the scope and spirit of the present invention.

Claims (7)

1. A digital display system for controlling a device  raster scanning display, characterized in that said system  understands  a) a revision memory for storing element data  images in locations corresponding to locations  associated image elements on said display device,  b) means for reading groups of data of image elements  consecutive in said revision memory to a first  clock frequency,  c) means for converting said groups of data into groups  image element control signals for the device  display, and  d) switching means for switching said means so  to carry out a conversion between a first mode in which each  said data group is converted to a group of data signals  individual picture element command issued to the device  display at said first clock frequency, and a second  mode in which 2n groups of successifts data (where n is a  positive whole number) are combined to generate a group of  individual picture element control signals issued to the  display device at one nth sub harmonic of said  clock frequency. 2. A digital display system according to claim 1 wherein n  is equal to 1 and said conversion means include first  transfer means which are connected to receive groups of  image element data, second transfer means which are  connected to receive the output of said first transfer means,  said first and second transfer means being synchronized with  said first clock frequency, and combining means which  are connected to the outputs of said first and second means of  transfer to transmit only the output of said second means of  transfer in said first mode and to combine the outputs described  first and second transfer means in said second mode. 3. A digital display system according to claim 2 comprising  third transfer means which are connected to receive the  outputs of said combining means, said third means of  transfer being synchronized to said first clock frequency in  said first mode and at half of said first clock frequency  in said second mode. 4. A display system according to claim 3 comprising a display system  color search table which is connected to receive the  outputs of said third transfer means to generate groups  of digital control signals for said display device. 5. A display system according to claim 3 comprising a display system  pallet registers which receive groups of data of image elements  consecutive derived from said revision memory and which generates  response to these, said groups of image element data for  said first transfer means. 6. A display system according to claim 5 wherein said  revision memory includes several color plans and including  in addition, as many parallel / series converters as there are  colors, each of these converters being designed to receive  bytes of data from memory and having serial output  connected to said pallet register system, so that said  pallet register system receives groups of data whose  bit widths correspond in number to converters  parallel / series. 7. A display system according to claim 6 wherein the memory  of revision includes four color planes, and further comprising a  selection system connected between the revision memory and the  parallel / series converters, said selection system being  connected to said switching means for switching the system in a  first mode in which each each byte of data read in a  revision memory plan is sent to the converter  parallel / serial associated with the plane, and in a second mode in which pairs of bits of each byte read in a memory plane, are directed to associated pairs of locations in the parallel / serial converters, so that each converter parallel / serial receives two bits from each plane of the revision memory.