FR2502984A1 - Electrostatic precipitator system HV controller - represses voltage converter in response to loading exceeding predetermined limit during corresp. time interval - Google Patents

Abstract

The precipitator system includes a voltage controller which produces from an alternating power source a variable output. This variable output drives a high voltage converter which applies a high voltage to a precipitator. This variable output is controlled by a control signal from a command subsystem. Preferably, the command subsystem is operative to repress the drive to the high voltage converter in response to its loading exceeding a predetermined limit during a corresponding limit interval. After this limit interval, the command subsystem is operative to rapidly restore productive drive to the high voltage converter, preferably by the next half cycle of the power source that has a polarity opposite to that existing at the beginning of the limit interval. In this fashion stabilized operation is quickly achieved. Also included, preferably, is a conductive element that is coupled to the high voltage converter.

Description

 The invention relates to electrostatic dusting.

 In many operations, the resulting gas which is discharged is purified by an electrostatic precipitator which employs a high voltage to ionize and deflect materials in the form of particles. The value of this high voltage influences the efficiency of the fact that an insufficient tension produces only a weak purification while an excessive tension causes a breakdown or an arcing which is unproductive. It is not desirable to regulate the high voltage so that it remains at a fixed value. On the contrary, it is desirable to increase the high voltage as much as the composition of the discharged gas allows, without causing an arcing. In a known electrostatic dust collector, the high voltage transients which are produced during the detection are detected. strike and they are used in a feedback loop. The high voltage is thus adjusted so as to establish a desired arc striking frequency. Such a system, which requires occasional arc strikes to function properly, dissipates considerable energy during these arc strikes.

 Since the composition of the exhaust gas which is presented to a dust collector can vary over time, the voltage employed by a dust collector must also be varied over time to ensure operation with good efficiency. However, varying this high output voltage in this way can mask other variations in high voltage which are a precursor to arcing. Because of this difficulty in distinguishing between routine fluctuations and fluctuations indicating an impending arc strike, known systems are designed to react to the violent fluctuations which are produced by a real arc strike.

 The invention avoids the problems indicated above by controlling the level of attack of a high voltage converter. The measurement is carried out with a conductive element which is coupled to the high voltage converter. An imminent arc ignition is detected by comparing the present value of the voltage across the conductive element with a basic signal which is a function of at least one previous value of the voltage across the conductive element. Using such a technique, the dust collector is able to adjust the value of the high voltage before arcing occurs.

 In a preferred embodiment, the measurement indicated above is carried out periodically, in order to eliminate the periodic effects produced by an alternating supply current.

 It is also possible to fix the instant at which a measurement is made so that it corresponds to the instant at which the dye variations are most representative of the imminence of an arc strike. For example, arcing has a high probability of occurring within a predetermined interval after a voltage controller has been set or, for alternating current, at predetermined phase angles.

 In addition, embodiments using the principles of the invention can repeatedly increment a control signal which controls the drive level of a high voltage converter. This process can be reversed if the high voltage begins to decrease at the start of a reverse corona effect.

 According to an exemplary embodiment showing the characteristics and advantages of the invention, an electrostatic dust collector system comprises a high voltage device. The dust collector system includes a voltage control device for producing from a primary energy source a variable output voltage which varies under the effect of a control signal. The high voltage device includes a high voltage converter which is driven by the voltage control device to produce a variable high voltage. There is also a conductive element which is connected to the high voltage converter. This element conducts under the effect of variations in the level with which the high-voltage converter is attacked to produce a high voltage. The high-voltage device also comprises a control element which reacts to the voltage across the terminals of the conductive element. producing the control signal. This control element includes a memory element. The memory element produces a basic signal which is a function of at least one previous value of the voltage across the conductive element. The control element produces the control signal with a value which has a predetermined relationship with respect to the basic signal and with respect to the present value of the voltage across the conductive element. Thus, the dust collector system reacts to parameters that indicate the imminence of a high-voltage arc strike.

 Another aspect of the invention relates to a method for varying the high output voltage which is produced by a high voltage converter associated with an electrostatic dust collector. The converter is attacked by a voltage control device.

This control device produces an output voltage which varies under the effect of a control signal. A conductive element is connected to the converter and the conduction of this element corresponds to the level with which the converter is attacked to produce a high voltage. The method includes the operation of initially measuring the voltage across the conductive element.

Another operation consists in advancing the control signal in a direction which increases the drive level of the high voltage converter. The method also includes the operation which consists in remeasuring the voltage across the conductive element after a predetermined interval after the initial measurement of this voltage. Another operation of the method consists in varying the control signal in a direction which decreases the output voltage of the control device under the effect of a predetermined variation in the value of the voltage across the terminals of the conductive element, on the predetermined interval.

The invention will be better understood on reading the following description of an embodiment and with reference to the accompanying drawings in which
Figure 1 is a block diagram of a dust collector system comprising a high voltage device designed and produced in accordance with the principles of the invention
Figure 2 is a diagram of a separator and absolute value generator circuit which is used in the dust collector system of Figure i
Figure 3 is a diagram of part of a tension control device which is used in the dust collector system of Figure i
Figure 4 is a block diagram of a triggered control element which is used in the dust collector system of Figure ;;
Figure 5 is a block diagram of a microcomputer which is used in the dust collector system of Figure i
Figure 6 is a block diagram of control elements for an operator and display elements associated with the dust collector system of Figure 1
FIG. 7 is a block diagram showing the deactivation device and the interface between the voltage control device and the control means which are employed in the dust collector system of FIG.
FIG. 8 is a sequence diagram relating to signals which appear in FIGS. 1 to 7; and
FIG. 9 is a flow diagram of the operation of the system of FIGS. 1 to 7.

 In FIG. 1, the sub-assembly 10 represents a voltage control device which is connected between an input line P2 and an output line P4. The subassembly 10 comprises a pair of thyristors Q1 and Q2 which are connected in parallel with opposite polarities between the lines P2 and P4, so as to be able to circulate an alternating current. By triggering thyristors Q1 and Q2 so that they lead to a desired phase angle, it is possible to control the conduction in these thyristors in a well known manner. Although a thyristor control device is shown here, it is clearly seen that other control devices employing elements such as a saturable reactance can be used instead.

 A high-voltage converter is represented in the form of a transformer-rectifier assembly T1, 18. A conductive element is represented in the form of an air inductor, 16, which is connected in a series circuit with the control device. 10 and the primary winding 14 of the high voltage transformer T1, between the input terminals 12 which receive the primary energy. The high-voltage converter is constituted by the transformer T1 and by a full-wave bridge 18, comprising the diodes CR1, CR2, CR3 and CR4. The diode anode CR1 and the cathode of the diode CR2 are connected to one terminal of the secondary winding, and the other terminal of this winding is connected to the cathode of the diode CR3 and the anode of the diode CR4 The cathodes of diodes CR1 and CR4 are shunted to earth by respective resistors R4 and R6. The anodes of the diodes CR2 and CR3 are connected to the connection point of current peak limiting inductors L2 and L4. The transformer T1 has a high transformation ratio and therefore makes the negative point DC voltage of high value appear at the connection point of the inductors L2 and L4.

 Although the conductive element 16 is shown here in the form of an air inductor, it is seen that other embodiments could use a resistive element. Because it is inductive, element 16 has the advantage of reacting to transient phenomena which indicate an imminent arcing. However, it is also possible to obtain good sensitivity to transients by using a resistor connected in series, the voltage drop of which is differentiated. Although the element 16 is shown connected in series with the primary winding T1, it can be connected to other suitable locations such that it conducts as a function of the level of attack of the transformer T1 and of the diodes CR1, CR2 , CR3 and CR4.We can for example connect a voltage divider between ground and the connection point between the diodes CR2 and CR3 to detect the level with which the high voltage converter is attacked.

 The non-common terminals of the inductors L2 and L4 are connected separately to respective high-voltage electrodes 22 and 24 of dust collectors 26 and 28. The dust collectors 26 and 28 are constructed in a well-known manner and they are arranged in the gas path exhaust from a processing machine or facility. Sufficiently high electric fields in the dust collectors 26 and 28 ionize and deflect the particles in the exhaust gases, which purifies these gases.

 The element 16 is connected in parallel to the primary winding 30 of the transformer T2 and the secondary winding 32 of this transformer is connected between earth and the input of a separator and absolute value generator circuit ABS1. The absolute value separator and generator circuit ABS1 (the details of which are given below) produces a unipolar signal whose value is proportional to the absolute value of its input signal.

An intensity transformer T3 which is in inductive coupling with the line connecting the input 12 and the element 16, supplies a signal proportional to the primary current of the transformer T1. The intensity transformer
T3 is coupled to a separator and absolute value generator circuit ABS2 by means of an isolation transformer T4. The ABS2 separator and absolute value generator circuit has a structure identical to the ABS1 separator circuit. The primary windings of transformers T1 and T5 are connected in parallel. The secondary winding of the transformer T5 attacks the input of a separator and absolute value generator circuit ABS3 whose structure is identical to that of the separator circuit ABS1.

It can be seen that the separator circuits ABS2 and ABS3 are attacked by voltages which are respectively proportional to the primary current and to the primary voltage of the high voltage transformer T1. The secondary current of the transformer T1 flows in one or other of the resistors R4 and R6, this current alternating between the two resistors during successive half-cycles. This secondary current signal is transmitted by non-inverting separating amplifiers 34 and 36 which are connected separately to the terminals of the respective resistors R4 and R6 which are not connected to ground.

A high voltage sensing element is shown here as a pair of dividers, although a Hall effect device or other device may be used instead. One of these voltage dividers, comprising the resistors R8 and R10 connected in series, is connected between the high voltage electrode 22 and the ground. Similarly, a divider comprising the resistors R12 and R14 connected in series is connected between the high voltage electrode 24 and the ground. The connection point between resistors R8 and R10 is connected to the input of an inverting separator amplifier 38 in order to attack it with a voltage proportional to the supply potential of the dust collector 26. Similarly, a separating amplifier inverter 40, which is connected to the connection point between the resistors
R12 and R14, is attacked by a voltage proportional to the supply potential of the dust collector 28.

 In many applications, it is convenient to place the apparatus of FIG. 1 that has just been described near the dust collectors 26 and 28. This equipment is frequently housed on the roof, next to one or more exhaust chimneys smoke. Because the rest of the equipment can be placed in a convenient location for an operator, this separation is indicated by a dashed RF separation line.

 The outputs of the separator circuits ABS2, ABS3, 34, 36, 38 and 40 are associated with the respective inputs IN2, IN3, IN4, IN5, IN6 and IN7 of a subsystem 42. The output of the separator circuit ABS1 is connected to a signal conditioning circuit 43 whose output is connected to the input IN1 of the subsystem 42. The circuit 43 is preferably a low-pass filter, but in certain embodiments, an integrator may be used instead.

Although applying seven different input signals in this way to subsystem 42 provides reasonably detailed information on the operation of the dust collectors, other embodiments may use a different number of inputs. The subsystem 42 is part of control means which comprise a triggered control element (described below) which is attacked by the Inti input. The control means considered here also include a microcomputer C0M, the circuit details of which are described below. The coupling between the subsystem 42 and the microcomputer C0M is represented in the form of a large arrow, to suggest the existence of several data transmission lines and the flow of information in a determined direction. COM microcomputer repeatedly samples the inputs IN1-IN7 so that these inputs are effectively multiplexed in the COM microcomputer. The microcomputer C0M also transmits a control signal to a subsystem 44. The subsystem 44 (which will be described later in more detail) is designed so as to convert the control signal produced by the microcomputer COM into a pair of time definition signals which are transmitted to the control device 10 by lines 46 in order to control its conduction angle. The subsystem 44 obviously establishes an appropriate interface between the control device 10 and the control means 42. As a result, the structure of the subsystem 44 would be notably different if, instead of using thyristors, the control device 10 employed a saturable reactance or another device.

An operator can enter information into the microcomputer COM, by actuating switches in a control member CNL (described below). The microcomputer COM can present information to an operator by means of a display device DISP (described below).

 The COM microcomputer, which ensures the overall control and synchronization of the system, can take various forms. It is preferable that this C0M microcomputer is constructed using a commercial microprocessor, as described below. However, many other structures will be readily apparent to those skilled in the art. In fact, in some embodiments, analog circuits can be used. For example, charge storage capacitors, which can be selected, can be charged to potentials representing the signals on the inputs IN1-IN7 at various times. These stored charges can be selectively transmitted to a combination network to produce a control signal.

 The COM microcomputer establishes the rate and the sequence according to which each of the inputs IN1-IN7 transmits its respective signal to the COM microcomputer. In this embodiment, this rate is normally equal to twice the frequency of the sector, but it is subject to a significant increase under predetermined conditions. It can be seen that other rates can be used to adapt to the characteristics of a particular tension control device and a dust collector.

 To facilitate understanding of the apparatus of FIG. 1, its operation will be briefly described under the conditions in which an arc strike is imminent, in which this strike has occurred and in which an inverse crown effect is present.

 It will be assumed that the device of FIG. 1 has been energized for a short time and that it produces a relatively low voltage on the electrodes 22 and 24.

The microcomputer COM addresses the inputs IN6 and IN7 and it receives data from these inputs, at each half-cycle of the mains voltage applied to the input 12. This data, including the voltage on the electrodes 22 and 24, are received after expiration of approximately 75% of the duration of a half-cycle. These time characteristics allow the microcomputer COM to determine relatively well the current conditions which exist during each half-cycle and to adjust the control signal on line 46 before the next half-cycle. For a moment, the control signal is periodically advanced to each demicycle to increase the voltage on the electrodes 22 and 24. In certain embodiments, the step of progression of the control signal of line 46 can be reduced when the voltages of the electrodes 22 and 24 approach their nominal values. It is assumed in this example that sufficient voltage produces a condition such that an arc strike is imminent. It is now assumed that during the following half-cycle, the corona effect in the dust collectors 26 and 28 expand and form protrusions or "fingers". This expansion is the precursor to arcing and produces a characteristic increase in the current of the dust collector. This increase in the current of the dust collector produces an increased voltage drop across the terminals of the element 16. Because the current disturbance which is produced by this expansion of the corona effect emanations contains important high frequency components, l inductance 16 is particularly sensitive to it. In addition, since the dilation of the corona effect scents has a high probability of occurring in the last part of a half-cycle of the energy applied to the input 12, the fact that the microcomputer COM performs its measurement during this period makes it particularly sensitive to this phenomenon.

 When the COM microcomputer receives a measurement originating from the input IN1 after approximately 75% of the current half-cycle has elapsed, it compares this latter measurement with a threshold fixed in advance (for example 2 V). In the flow diagram of FIG. 9, this sequence is represented by several stages. In step 200, the system waits for a phase indication signal appearing on terminal 72 (which will be described in more detail later) indicating the flow of 75% of the half-cycle. In step 202, the system records the signal which comes from the input IN1 and in step 204 it performs the comparison with the threshold. If the threshold is exceeded, the control signal is decremented in step 206 by a factor of approximately 1%. This decrement is chosen so that it suits the characteristics and the response time of the dust collector which is controlled.

 After this operation (or if it is assumed that step 206 has been skipped due to the fact that the threshold has not been exceeded in step 204), the previous value of the signal of input IN1 is subtracted from the most recently measured value for this signal, which is indicated by step 208. In step 210, the difference obtained is compared with a limit fixed in advance (for example 10%). If the limit is exceeded, the control signal is decremented while otherwise it is incremented. These reduction and increase operations are indicated respectively by steps 212 and 214. The value of the decrement is chosen so as to suit the characteristics and the response time of the dust collector. The value of the increment of step 214 is lower than that of the decrement of step 206. This relationship ensures that in the event that a decrease takes place, its effect is not canceled out by the increase which is performed in step 214.

 The result of the previous operations is that if element 16 (figure 1) indicates that an arc strike is imminent, the control signal (line 46 of figure 1) is decreased, while it is increased otherwise. Thus, the high voltage which is applied to the dust collectors 26 and 28 is found at a relatively large value, just below the point at which arcing occurs. In this embodiment, the control signal is varied by a fixed amount, but in other embodiments, the value of the variation can be obtained from a table or formula, or from other parameters measured.

 It will be noted from reading the above that the COM microcomputer (FIG. 1) is capable of reacting quickly to the imminence of an arc strike and that it immediately attempts to reduce the conduction angle of the device command 10, before 11 arcing occurs.

In this embodiment, the control device 10 employs thyristors which cannot stop driving before the end of a half-cycle of the energy applied to the input 12. Therefore, it is not the C0M microcomputer must react before this time. However, other embodiments can employ fast switching elements or saturable reactance, in which case the controller can be immediately turned off to avoid arcing.

 We have just described the operation in the case where arcing is avoided. We will now describe the reaction of the system in the case where a strong disturbance nevertheless produces an arc.

 It will be assumed that in the middle of a half-cycle of the energy applied to the input 12 (Figure 1), an arcing begins in the dust collector 26. As a result, the voltage on the electrode at high tension 22 drops abruptly. The relatively low voltage which thus appears on the input IN6 is detected after a short time by the microcomputer COM. The most recent value of the signal of the input 1N6 is compared with the value which appeared half a cycle plus everything, and if it exceeds a predetermined limit (for example 25%), the microcomputer C0M reacts to this condition by bringing the control signal present on line 46 to a minimum value. This characteristic is also represented in the flow diagram of FIG. 9, which shows that immediately after the operation corresponding to step 212 or 214 envisaged previously, the most recent high voltage values obtained from the inputs IN6 and IN7 are stored in memory.

The corresponding high voltage values recorded during the previous half cycle are subtracted from these recent values. If the two differences are greater than or equal to zero, there is no further adjustment of the control signal and the subroutine passes to a new cycle, as described below. If either of these differences is negative, which indicates a drop in high voltage, the system performs a comparison with a pre-set arc strike limit to determine whether an arc strike. arch has taken place. If the limit has been exceeded, operation proceeds as follows, as indicated by steps 220, 222, 224 and 226 of the flow chart (Figure 9).

 The control signal is reset to try to deactivate the control device 10 (Figure 1). However, as mentioned previously, if the thyristors of the control device 10 are already conductive, they continue to drive at least until the end of the half-cycle of the energy which is applied to the input 12. From fact that it appears that an arcing has started, the microcomputer COM begins to request data coming from the inputs IN6 and IN7 at a relatively high rate. This high rate is important because the control device 10 must remain off as long as the arc persists.

In addition, because the voltage required to strike an arc is significantly greater than the voltage required to maintain it, the arc does not go out until the electrode voltage has not significantly decreased. Therefore, the voltages on the inputs IN6 and IN7 are controlled in "real time" until they fall below an extinction value which ensures the extinction of the arc.

 The time required to extinguish an arc may vary with each appearance of that arc. Although the voltage on the electrodes 22 and 24 normally decreases in the last half of each half cycle of the alternating energy applied to the input 12, this decrease may be insufficient. In addition, the capacity of the dust collectors 26 and 28 can be large enough for the voltage reduction to be very gradual. For these reasons, the microcomputer COM deactivates the control device 10 as long as the voltage on the electrode 22 or 24 remains excessive. Once this voltage is no longer excessive, the control signal is restored, but to a significantly lower value (corresponding for example to a reduction of 25%) than that which existed in the half-cycle in which the initiation of The arc has taken place, thus avoiding the probability of repeated arc strikes.

 If it is assumed that the high voltages fall below an extinction value a short time after the start of a next half-cycle of the energy applied to the input 12, the operation corresponding to step 228 (Figure 9) takes place. This operation consists in the transmission of the restored control signal, followed by a return to the beginning of the sequence of operations, which is indicated by step 234. The control signal having been restored, one of the thyristors of the control device 10 (FIG. 1) again leads to an instant (phase angle) which is determined by the control signal.

 The preceding sequence of operations which has just been described in relation to FIG. 9 constitutes a program cycle of the microcomputer. Consequently, the microcomputer waits for the next appearance of a phasing signal, appearing after the expiration of 75% of the current half-cycle of the energy applied to the input 12, as indicated by l 'step 200.

 The above sequence constituted a feeding cycle in which an arcing occurred and in which step 222 (FIG. 9) was executed in place of step 230. We will now assume that the arcing did not take place and instead an inverse crown effect occurred during the last 25% of the considered half-cycle of the energy applied to input 12. The reverse crown effect is characterized by operation at a relatively high voltage in a region in which a dust collector has a negative impedance (negative slope of the voltage-current characteristic). Operation in such a region is poor and should be avoided.

 Therefore, once the COM microcomputer (FIG. 1) has determined that the decrement of the high voltage measurement corresponding to the inputs IN6 and IN7 does not indicate an arcing, the operation which is indicated by step 230 (Figure 9) begins. This operation consists in determining whether this moderate decrease in the high voltage exceeds a threshold (for example 5%) which would indicate a reverse corona effect. If this crown effect limit is exceeded, the control signal is decremented by a predetermined value (for example 1%), which is indicated by step 230. This decrement is greater than the increment which can between product by the operation associated with step 214. Although the variation which has just been described for the signal corresponds to a fixed decrement, other embodiments may employ a table, a formula or the value of the measurements corresponding to the IN1-INS inputs to determine the variation of the control signal during the existence of a reverse crown effect.

 With the previous procedure, the voltages on the electrodes 22 and 24 are gradually increased until the reverse corona effect occurs. When the reverse corona effect occurs, the system decreases the conduction angle of the control device 10. In this way, the voltage of the electrodes is maintained in the vicinity of a peak value which corresponds to a relatively high efficiency. It can be seen that if there was no reverse crown effect and if the voltage-current characteristics of the dust collectors 26 and 28 were monotonic, the dust collector voltage would increase until an arcing was imminent.

We will now consider FIG. 2 which is a schematic representation of a circuit representative of the separator and generator circuits of absolute value
ABS1, ABS2 or ABS3 in Figure 1. Two operational amplifiers 48 and 50 are shown connected in parallel. A diode CR5 and the series combination of a resistor R20 and a diode CR6 are connected in parallel between the output and the inverting input of the amplifier 48. The cathode of the diode CR5 and the anode of the diode CR6 are connected to the output of amplifier 48, while the non-inverting input of this amplifier is connected to ground. Due to the presence of a resistor R22 connected between input P5 and the inverting input of amplifier 48, this amplifier supplies on output P6 corresponding to the connection point of resistor R20 and diode CR6 a clipped output signal which is positive, unipolar and inverted.

 The amplifier 50 applies to the output P6 a clipped and not inverted representation of the input signal present on the terminal P5. A CR7 diode and the series combination of a CR8 diode and a R24 resistor are connected in parallel between the inverting input and the output of the amplifier 50. The cathode of the CR7 diode and the anode of the diode CR8 are connected to the output of amplifier 50, while the non-inverting input of this amplifier is connected to terminal P5. The connection point of the resistor R24 and the diode CR8 is connected to the output terminal P6 which is shunted to ground by a resistor R26.

 The configuration indicated above transfers the positive and negative input signals by respective amplifiers 50 and 48 having a gain equal to unity. Since only the amplifier 48 performs an inversion, the output signal present on the terminal P6 is the absolute value of the input signal of the terminal P5. We see that this function can be fulfilled by other configurations, such as a conventional full-wave bridge.

 We will now consider Figure 3 in which we see a partial schematic representation of the control device 10 of Figure 1. The thyristors Q1 and Q2 are connected in anti-parallel configuration with their anodes and their cathodes connected between the input P2 which receives primary energy and output P4.

Corresponding designations of the terminals are shown in FIG. 1. A resistor R28 and a secondary winding 52 of a transformer T8 are connected in parallel between the trigger and the cathode of the thyristor Q1. A resistor R30 and a secondary winding 54 of a transformer T9 are connected in parallel between the trigger and the cathode of the thyristor Q2. One terminal of each primary winding 56 and 58 is respectively connected to the control terminals P10 and P12, while the other two terminals of the primary windings are connected together to a source of positive potential. Transformers T8 and T9 are connected with a phase such that a temporary grounding of terminal P10 or P12 respectively initiates thyristor Q1 or Q2. Terminal P12 can be used to trigger the circulation of a positive current (from terminal P2 towards terminal P4), while terminal P10 triggers the circulation of a negative current. Once thyristors Q1 and Q2 are primed, they continue to drive until the voltage between the anode and the cathode drops to almost zero volts. Control devices conforming to FIG. 3 are commercially available and, in practical embodiments, they have a greater complexity than that shown in this partial diagram.

We will now consider FIG. 4 in which we see a triggered control element which is represented here in the form of an analog to digital converter AD which attacks a network of output flip-flops
L1, although other configurations are possible. If, for example, an analog system is used instead of a digital system, the device shown here can be replaced by a well-known sample-and-hold circuit. The AD converter is a commercial integrated circuit which converts an analog signal present on the INP input into 8-bit data in parallel. These 8 bits are transmitted to the flip-flop network L1 by the eight lines represented. The operation of the converter AD is triggered by the application of a pulse to a start input SC. The conversion rate is defined by an external clock source REF, operating at 1.0 MHz, which is connected to the CL clock input of converter
AD. The completion of the conversion is signaled by the appearance of a positive pulse on the terminal EC of the converter AD. Starting pulses are supplied by a divider 61 whose input and output are connected separately and respectively to the terminals CL and SC of the converter AD. By being connected in this way, the divider 61 can periodically initiate the conversion with a repetition rate which is related to the speed of the AD converter, such as for example 18 kHz. The L1 flip-flop network consists of a pair of commercial integrated circuits which record the data produced by the AD converter in eight internal flip-flops. The data is recorded by the application of a clock pulse rising on the CL input of the scale network
L1, provided that its DI disabling input terminal receives a low signal (zero volts). The data contained in the flip-flop network L1 is applied to a bus line DA, provided that the output invalidation terminal DO is in the low state. A signal in the high state (+5 V) on the restore input R of the flip-flop network L1 forces all the internal flip-flops of this network to a low state, independently of its other inputs. The output EC of the converter AD is connected to the restoration inputs R of a pair of flip-flops of type "D", FF1 and FF2, the data inputs D of which are connected to a common signal source in the high state. The Q outputs of the flip-flops
FF1 and FF2 are connected separately and respectively to the restoration input R and to the clock input CL of the flip-flop network L1. The clock inputs C of the flip-flops FF1 and FF2 are connected separately and respectively to the terminals SEL1 and FCL. The SELI terminal is attacked by the microcomputer COM (FIG. 1) and it is also connected to the input DO of the network of flip-flops L1 as well as to the input of an inverter 62 whose output is connected to the input d 'a separator circuit 64 and at the input DI of the network of flip-flops L1. The output of the separator circuit 64, that is to say the terminal 66, is connected in common to the outputs of the corresponding separator circuits in other converters. Similarly, the outputs of the REF source and of the divider 61 as well as the clock signal terminal
FCL are connected in common to the corresponding inputs of other analog-digital converters. These other converters are used to process the signals present on the inputs IN2-IN7 (figure 1). The FCL terminal receives a synchronization signal which is used by a microprocessor (envisaged below) which is part of the microcomputer COM (FIG. 1).

 A clock signal from the microcomputer COM is applied to the terminal SEL1 to cause the flip-flop network L1 to connect its flip-flops to the bus lines DA. When this triggering does not take place, the signal present on the terminal SEL1 is in the high state and the device of FIG. 4 converts the signal present on the input INP of the converter AD, by proceeding as follows.

 The generation of a pulse by the divider 61 triggers the operation of the converter AD which produces after approximately 42, us 8-bit data in parallel, representing the voltage on its input INP.

After this conversion, the output EC of the converter AD emits a pulse towards the restoration inputs R of the flip-flops FF1 and FF2, and under the effect of this pulse the outputs Q of these flip-flops apply signals in a low state to the inputs R and CL of the L1 flip-flop network.

The following synchronization pulse appearing on the terminal FCL raises the level of the output Q of the flip-flop FF2 and triggers the clock input CL of the network of flip-flops L1. Because the terminal SEL1 is in the high state, which gives rise to an inverted signal in the low state on the input invalidation terminal DI, the flip-flops of the network of flip-flops L1 receive and record the data at 8 bits that come from the AD converter. At this time, the system is in a state to accept another start pulse from the divider 61 and it repeats all of the previous operating sequences.

It will now be assumed that a trigger signal is applied to the terminal SEL1, which causes a low signal to appear on the input C of the flip-flop FFt and on the input DO of the network of flip-flops L1, and a signal inverted high on the DI input of the scale network
L1. Under the effect of these signals, the flip-flop network L1 connects its internal flip-flops to the bus line DA as long as the terminal SEL1 remains in the low state. This state thus causes the transmission of data on the DA lines. It will be noted that because the input DI of the network of flip-flops Lt is in the high state, this network does not react to its clock input CL. There is thus no attempt to modify the data once the transmission has started. When the terminal SEL1 returns to a high state, it triggers the clock input of the flip-flop FF1. Under the effect of this triggering, the output Q of the flip-flop FF1 applies a signal in the high state to the restoration input R of the network of flip-flops L1, which switches its flip-flops to a low state.

As we will see, this low state indicates that the time that has passed is insufficient for the AD converter to be able to update the data contained in the Lt flip-flop network. When the AD converter has completed another conversion cycle , its EC output applies a pulse to the restoration inputs R of the flip-flops rFl and
FF2. Under the effect of this pulse, the flip-flops apply signals in the low state to the inputs R and CL of the flip-flop network Lt. Under these conditions, the flip-flop network L1 is capable of receiving the updated data coming from the converter AD under the effect of the following synchronization pulse applied to the terminal
FCL. This update is repeated as described above as long as terminal SEL1 remains high.

 The input signal which is applied to the terminal INP of the converter AD comes from the terminal INIS which corresponds to the input identified in a similar manner in FIG. 1. Input filtering means are represented here in the form of a low-pass filter which includes a resistor R31 and a capacitor C1, the connection point of which is connected to the input INP of the converter AD; the other terminal of the capacitor C1 is connected to ground and the other terminal of the resistor R31 is connected to the output of the splitter amplifier 68 whose input is connected to the terminal INi '. The sequential diagram 8B in FIG. 8 shows waveforms representative of the signal on the terminal IN11 The voltage fluctuations corresponding to the terminals of the high-voltage transformer T1 (FIG. 1) and of the dust collector 26 (FIG. 1) are represented respectively on the sequential diagrams 8A and 8C of FIG. 8. It can be seen on diagram 8B (FIG. 8) that the signal of the input INl / is in the form of a ramp signal with occasional high frequency pulses appearing during this ramp variation. These pulses correspond to the imminence of the appearance of an arc strike.

 The circuit which is located between the terminals In'and INP constitutes an input filter which is designed so as to improve the sensitivity of the system to the imminence of an arcing. Although this circuit is preferably a low-pass filter, it can take several other forms.

It can for example be constituted by integration means or by a bandpass filter or other processing circuits. The particular circuit that is used depends on the desired sensitivity and the expected waveforms. The above-mentioned integration means can employ a well-known integrator comprising an operational amplifier with a capacitive feedback.

 We will now consider FIG. 5 in which the microcomputer COM of FIG. 1 is represented in the form of a more detailed block diagram.

Although the microcomputer is shown here as a pair of PRCI and PRC2 microprocessors, analog circuits can be used instead, as previously mentioned. PRC1 processors and
PRC2 are connected by common ADR and DA bus lines.

ADR lines are multi-bit lines on which the processors PRC1 and PRC2 transmit coded address information. These addresses select a particular position in a memory MEM, under the effect of which this memory transmits on the data lines with several bits DA the information which is recorded at the designated address. The PRC1 and PRC2 processors and the MEM memory are commercial integrated circuits.

 Terminals 66, 72 and FCL are connected to the two processors PRC1 and PRC2. The terminal FCL, described previously in relation to FIG. 4, supplies a synchronization clock signal coming from a source (not shown) which makes the processors PRC1 and PRC2 carry out their various internal operations sequentially.

Terminal 72 receives a detection signal at the expiration of a period of 75% of a half-cycle of the energy applied to input 12 (Figure 1). The circuit intended to produce such a signal is described below. Terminal 66, described above in relation to FIG. 4, supplies an acknowledgment signal which confirms that an analog-digital converter has been triggered by the processor PRC1 or PRC2.

A sequencing device is shown here in the form of an MX decoder. The MX decoder triggers each individual analog-digital converter once during each half-cycle of the energy applied to input 12 (Figure 1), under normal operating conditions. The MX decoder reacts to the address codes applied to it by the address lines
ADR. The signals present on these lines represent different converters among the numerous analog-digital converters contained in the subsystem 42 (FIG. 1). One of these converters is the AD converter of FIG. 4. The MX decoder has a trigger line for each of the analog-digital converters that it can trigger. Consequently, the SELN lines (FIG. 5) are at least at number of seven in order to trigger the seven converters which are associated with the seven inputs IN1-IN7 (figure 1). One of these trigger lines is represented by the terminal
SEL1 in FIG. 4. The decoder MX also includes a line for each of the input and output devices which will be described later.

 The measured values which are received by the processors PRC1 and PRC2 are recorded in a memory device which is represented here by the memory MEM which comprises eight integrated circuits of read-only memory and twenty-four integrated circuits of random access memory connected in the usual manner. Of course, there are many other memory devices available today. These memory devices also store the computer program which essentially resides in non-volatile read only memory integrated circuits. The program is designed to perform the functions described above in relation to the COM microprocessor (Figure 1) and the flowchart in Figure 9. Generally, the program produces a periodic triggering of the analog-digital converters of the subsystem 42 (figure 1) in order to measure the state of the dust collectors. As described above, the values and variations of these parameters are compared with certain references stored in memory to determine whether the control device 10 (figure 1 ) must be set. In this way, the program sets the dust collector voltage to the highest level which does not produce an arcing or reverse crown effect which are unnecessary. The particular program instructions which are necessary to obtain the functions described above in connection with Figure 1 will be apparent to those skilled in the art. In addition, the user can modify the sequence of program instructions in various ways. For example, all measurements can be made sequentially before executing any logic program instructions. Alternatively, measurements can be made immediately before they are needed for a particular calculation or particular logic decision. In addition, the previously described reaction to an impending arc strike or reverse corona effects can be contained in two separate routines which can be executed in any order. In addition, during certain time intervals, the data can be taken at such a high rate and the logical decision can be taken so immediately, that the program can be considered to operate in a so-called "real time" mode. We have previously described such an operating interval in real time in the case of an interval during which an arc has occurred.

 Due to the relative ease with which the programming can be modified, it is expected that an operator can introduce such modifications from time to time.

For example, an operator can change certain operating references when it is expected that the dust collector will have to treat an exhaust gas with an unusual level of contamination, or when the ambient temperature or humidity is unusual.

It will also be noted that the block diagram in FIG. 5 is simplified but that the additional structural details are conventional and well known to those skilled in the art. In addition, it is expected that the PRC1 and
PRC2 have sufficient capacity to control the operation of conventional accessories such as rocking hammers.

 We will now consider FIG. 6 in which the peripheral input and output devices which are associated with the processors PRCi and PRC2 (FIG. 5) are represented in a simplified synoptic form.

It will be noted that most of the embodiments comprising such peripherals will be more complex, FIG. 6 having only the aim of illustrating their operating principles.

Two seven-segment display devices 76 and 77 are attacked by an interface circuit 78. The circuit 78 includes flip-flops which record the coded information coming from the data lines DA, under the effect of a signal. trigger input applied to the line
SEL3. After recording, decoding and driving circuits forming part of the circuit 78 attack the digital display devices 76 and 77 so as to present to the operator the information which is produced by the processors PRC1 and PRC2 (FIG. 5) . The lines SEL3 and SEL4 are part of the lines SELN (FIG. 5) and the lines DA are the bus lines described above.

Similarly, the operator can enter information by means of manual switches SW1 and
SW2. These switches position flip-flops in circuit 79 and these flip-flops can apply their data to lines DA under the effect of a trigger signal on line SEL4. The switches SW1 and SW2 can be part of a larger keyboard intended to transmit alphanumeric information by the lines DA. The particular configuration of the integrated circuits contained in the sub-assemblies 78 and 79 is so conventional that a person skilled in the art does not need additional details to understand the structure of the device in FIG. 6.

We will now consider FIG. 7 which represents certain details of the circuits contained in the subsystem 44 (FIG. 1). DA data lines are connected to the data inputs of the scale network
L4 whose data outputs are connected to the data inputs of the L6 flip-flop network. The data outputs of the L6 flip-flop network are connected to the prepositioning inputs of a counter in decreasing direction with prepositioning 80. The L4 and L6 flip-flop networks are similar to the flip-flop networks described above (for example the L1 flip-flop network of FIG. 4) and their clock inputs CL are respectively connected to the terminals SELS and 120. The input invalidation terminal DI of the flip-flop network L6 is attacked by an inverter 82 whose input is connected to the terminal SELS The SELS terminal is connected to one of the SELN lines (Figure 5). Terminal 120 (FIG. 7) is driven by a local phase-locked loop which includes a shaping circuit 84, a phase comparator PC, an oscillator controlled by voltage VCO and a divider DIV. The shaping circuit 84 consists of a comparator which produces a square signal at the same frequency as the mains energy which is applied to the input 12. The voltage controlled oscillator
VCO, which produces a signal at a nominal frequency of 122.88 kHz, attacks the divider DIV which produces five output signals whose frequencies are linked to the frequency of
n the VCO oscillator by division rank 2. In particular, for the nominal input frequency of 12288 kHz, output signals having frequencies of 30720, 480, 240, 120 and 60 Hz are respectively applied to terminals 30720, 48C, 240, 120 and 60. The signal at the nominal frequency of 9 Hz present on terminal -60 is subjected to a phase comparison in the PC comparator with the output signal from the shaping circuit 84 , which is synchronous with the sector frequency. The comparator PC applies a voltage to the control input of the VCO oscillator which locks the phase of this oscillator with that of the mains energy applied to the input 12, in a conventional manner. the phase locked loop considered above are made from integrated circuits which are produced commercially for such use. The previously described signal from terminal 72 (here and in FIG. 5) is produced during each half-cycle of the energy applied to input 12.

This signal is produced after 75% of each half cycle.

For this purpose, the two inverting inputs of the AND gate 85 are connected separately to terminals 120 and 240 and its non-inverting input is connected to terminal 480.

 The signal present on the UO terminal is transmitted to the trigger input of a monostable multivibrator 86 which produces a pulse having a duration of approximately 65 ps.

The output of the monostable multivibrator 86 is connected to the inverted clock input C of a flip-flop of type "D",
FF4, whose terminals D, S and Q are respectively connected to earth, to the output of the inverter 82 and to an input of a NOR gate 88. The other input of the gate
NOR-88 is connected to the output of the monostable multivibrator 86 and to an input of an OR gate 90, the other input of which is connected to the output of the NOR gate 92. The output of the NOR gate 88 is connected to the R restoration inputs of the L4 and L6 flip-flop networks.

A deactivation device is represented here by the NAND gate 92. The NOR gate 92, the eight inputs of which are connected to the data lines between the flip-flop networks L4 and L6, produces an output signal at the 'high when all of these data lines are low. As will become apparent, this configuration detects a deactivation signal which finally deactivates the voltage control device 10 (FIG. 1). The exit from the door
OR 90 (FIG. 7) attacks the counter preposition validation input in decreasing direction 80, the clock input CL of which is attacked by the AND gate 94. The terminal 30720 mentioned previously is connected to a non-inverting input of the AND gate 94 and the inverting input of this gate is connected to the CO transfer output of the counter 80.

 The transfer output CO of the counter 80 is connected to an input of an AND gate 104 the other input of which is connected to the output of a limit device 106. The device 106 is attacked by the signals present on the terminals 120 and 30720 so as to provide a positive direction pulse whose duty cycle can be adjusted manually. The trailing edge of this pulse is synchronized by terminal 120. The structure of device 106 is similar to that associated with counter 80.

The input D of a flip-flop FF5 is connected to a positive voltage source and its input C is connected to the output of the AND gate 104. The restoration input R of the flip-flop FF5 is connected to the output of a OR gate 108 whose inputs are separately connected to the terminal
SYSRS and at the exit from OR gate 90. The SYSRS terminal receives a priority action signal which is produced manually. As will become clear, the application of a high signal on the SYSRS terminal prevents the operation of the control device 10 (FIG. 1).

 A resistor R32 is connected between the base of a transistor Q4 of NPN type and the output of an AND gate 110. A resistor R34 is connected between the base of a transistor Q6 and the output of a NOR gate 112 The outputs Q and Q of the flip-flop FF5 are connected separately and respectively to an input of doors 110 and 112. The two other inputs of these doors are connected in common to terminal 60. The terminals P1O and P12 (figure 3) are connected separately and respectively to the collectors of transistors Q6 and Q4 whose emitters are connected to ground.

 To facilitate understanding of the device in FIG. 7, its operation will be briefly described. As an aid, the sequential diagrams 8A, 8B and 8C of FIG. 8 show the signals which appear respectively on the inputs IN3, In'and IN6 (FIG. 1), while the sequential diagrams 8D and 8E show the signals present on lines 60 and 2 (Figure 7).

 It will first be assumed that data (a control signal) is transmitted at the time considered.

Data transmission is indicated by a negative direction pulse on the SELS terminal which is connected to one of the SELN lines (Figure 5). This negative direction trigger pulse present on the terminal SELS is reversed by the inverter 82 which attacks the positioning input S of the flip-flop FF4, which causes the output Q of this flip-flop to go high. This output signal in the high state is transmitted to the NOR gate 88, which means that this door applies a signal in the low state on the restoration lines R of the flip-flop networks L4 and L6. The trailing edge of the negative direction pulse present on the terminal SELS triggers the clock input CL of the network of flip-flops L4, whereby this network records the data present on the lines DA.

 Terminal 120, whose signal is locked in phase on the sector energy applied to terminal 12, produces a positive direction transition at the end of each half-cycle of the energy applied to input terminal 12.

Therefore, the terminal 120 attacks the clock input CL of the flip-flop network L6 and causes this network to output the data coming from the flip-flop network.
L4, at the end of each half-cycle of the energy applied to the input 12. The signal present on the terminal 120 also attacks the monostable multivibrator 86 which applies via the OR gate 90 a positive pulse on the input for prepositioning PE of the counter in decreasing direction 80. This preposition the counter 80 and also transfers a positive pulse to the restoration line R of the flip-flop FF5, via the OR gate 108. Consequently, the flip-flop FF5 applies a low signal to an input of the door AND 110 and a high input signal to an input of the door
NOR OR 112. As a result, the gates 110 and 112 apply signals at zero volts to the respective bases of the transistors Q4 and Q6, which blocks these transistors. Because the collectors of these transistors control the voltage control device 10 (Figures 1 and 3), and the fact that this occurred at the end of half a cycle of the energy applied to the input 12 (Figures 1 and 7), the thyristors of the control device 10 are brought to the non-conductive state. Consequently, no energy is transferred at this time by the control device 10, from the energy input 12. We will describe the counting operation of the counter 80, to allow to understand the effect of the prepositioning of this counter.

 The prepositioning inputs of the counter 80 are represented in the form of inverted or supplemented inputs. Consequently, the binary complement of the digital output signal of the L6 flip-flop network, ie 255 minus this digital output signal, is applied to the counter 80. Provided that the binary number supplied by the L6 flip-flop network is not zero ( prepositioning to the maximum), the CO carry-out output of the counter 80 goes to the low state, which allows the AND gate 94 to transmit to the clock input terminal CL of the counter 80 the signal at 30.72 kHz present on terminal 30720. Once the outputs of the monostable multivibrator 86 and of the OR gate 90 are returned to zero, the AND gate 94 causes the counter 80 to be compiled in the reverse direction from the complemented prepositioning input value, at a rate of 30.72 kHz. If for example the network of flip-flops L6 transmits a number equal to 100, the counter 80 is prepositioned at 155 and it counts in decreasing direction until zero in approximately 6 ms. As will become clear, the number provided by the L6 flip-flop network is proportional to the conduction angle of the control device 10 (FIG. 1). When the counter 80 reaches zero, it produces a high signal on the CO carry-out output which, when applied to the AND gate 94, prevents the application of subsequent clock pulses to the counter 80.

The high signal from the output
CO of the counter 80 is transferred by the AND gate 104 to the clock input C of the flip-flop FF5, assuming for the moment that the device 106 also applies a high signal to the AND gate 104. causes a high signal to also be applied to the input
D of the bascuel FF5, the states of its outputs Q and Q are reversed. At this time, one, but only one, of gates 110 and 112 produces a high signal. If the input energy is in a positive half-cycle, terminal 60 applies a positive signal to the AND gate 110 which causes the conduction of transistor Q4. As a result, thyristor Q2 (Figure 3) becomes conductive. On the other hand, for a negative half-cycle, the NOR gate 112 would cause the conduction of the transistor Q6 (FIG. 7) and of the thyristor Qi (FIG. 3).

 At the end of the current half-cycle, the FFS rocker is restored again in the manner described above. This returns the circuit to its original state in which it is ready to repeat another power cycle.

 We will now assume that instead of normal continuous operation, an arcing occurs and continues throughout the next half cycle. Under the effect of this condition, a zero binary signal is introduced into the flip-flop networks L4 and L6 a short time before the start of another half-cycle. Therefore, all the inputs of NOR gate 92 are in the low state, which produces a signal in the high state at the output of this door.

Irrespective of the fact that the counter 80 may be counting, the output signal at the high state of the door 92 is transmitted by the door 90 to preposition the counter 80 to its maximum value. In addition, since it is now assumed that the arc persists for a full half-cycle, the high state output signal from NOR gate 92 also persists. As a result, the CO output of the counter 80 remains low for the duration of this demicycle. Normal operation begins again when a non-zero signal is transmitted from the DA data lines.

 Similarly, an operator can apply a high signal to the SYSRS terminal to transmit this signal through gate 108 to the restore input R of the flip-flop FF5. Because the flip-flop FF5 is forced into a restoration state, the transistors Q4 and Q6 cannot drive and the control device 10 (FIG. 1) is therefore again deactivated.

 It will also be noted that during a manually adjustable interval which begins at the start of each demicycle of the energy applied to the input 12, the device 106 applies a signal in a low state to an input of the AND gate 104. It can be seen that the device 106 fixes the earliest moment at which the flip-flop FF5 can be triggered. The device 106 therefore fixes the maximum conduction angle for the control device 10 (FIG. 1).

 As previously mentioned, the apparatus described in relation to the previous nine figures can be constructed in other ways using a different combination of digital and analog circuits. It is further seen that various other microprocessor programs can be used in accordance with the above principles. In addition, the sensitivity of the system can be adjusted to the parameters measured so as to adapt to the particular dust collector that is controlled. It is further contemplated that other embodiments will use circuit components having different tolerances and characteristics, so as to achieve the desired precision, power, speed, etc. Thus, the foregoing description leaves room for modifications, changes and substitutions, and in some cases certain features of the invention can be employed without using other features. Many modifications can therefore be made to the device and to the method described and shown, without departing from the scope of the invention.

Claims (17)

 1. High voltage device belonging to an electrostatic dust collector system comprising a voltage control device (10) intended to produce from a primary voltage source (12) a variable output voltage which varies under the effect of a control signal, characterized in that it comprises: a high voltage converter (T1, 18) which is driven by the voltage control device so as to produce from this latter a variable high voltage; a conductive element (16) which is connected to the high voltage converter and which conducts according to variations in the level with which the high voltage converter is driven to produce a high voltage; and control means (COM, 42, 43, 44) which react to the voltage across the conductive element by producing the control signal, these control means comprising a memory element (MEM) for producing a signal basic which is a function of at least an earlier value of the voltage across the conductive element, these control means producing the control signal with a level which has a predetermined relationship with respect to the basic signal and the value has voltage across the conductive element, whereby the dust collector system responds to parameters that indicate that impending high-voltage arcing is imminent.  2. High voltage device according to claim 1, characterized in that the control means (COM, 42, 43, 44) comprise a triggered control element (AD, L1, FF1, FF2) which is intended to produce so recurrent triggered signals which represent the level of the voltage across the conductive element at recurring times.  3. High voltage device according to claim 2, characterized in that the control means (COM, 42, 43, 44) react to a change between two successive triggered signals and in that the first of these two successive signals is recorded in the memory element (MEM).  4. High voltage device according to claim 1, characterized in that the conductive element (16) is essentially inductive and in that the control means (COM, 42, 43, 44) vary the control signal in a direction which decreases the variable output voltage of the voltage control device (10) under the effect of an increase greater than a predetermined increment in the voltage level across the conductive element.  5. High voltage device according to claim 2, characterized in that the high voltage converter (T1, 18) comprises a high voltage transformer (T1) and in that the conductive element consists of an inductor operating in linear regime which is connected in series with this transformer.  6. High voltage device according to claim 1, characterized in that the control means (COM, 42, 43, 44) comprise integration means (43) which are connected to the conductive element so as to produce a signal which represents the integral with respect to the time of the voltage across the conductive element.  7. High voltage device according to claim 1, characterized in that the control means (COM, 42, 43, 44) comprise the input filtering means (R31, C1) which are connected to the conductive element of so as to let through the frequency components included in a predetermined spectrum.  8. High voltage device according to any one of claims 1 to 7, characterized in that it further comprises high voltage detection means (R8, R1O, 38; R12, R14, 40) which are intended for transmitting to the control means a signal which represents the level of the voltage produced by the high-voltage converter (T1, 18), these control means progressively advancing the control signal under the effect of a simultaneous increase in the level of the voltage produced by the high voltage converter.  9. High voltage device according to claim 8, characterized in that the control means (COM, 42, 43, 44) reverse the direction of variation of the control signal under the effect of a predetermined decrement in the level of the voltage produced by the high-voltage converter (T1, 18).  10. High voltage device according to claim 8, characterized in that it further comprises an deactivation element (92) which reacts to a given value of the control signal by deactivating the voltage control device ( 10), this given value appearing when the level of the voltage produced by the high-voltage converter decreases by an amount which corresponds to an arcing.  11. High voltage device according to claim 2, characterized in that the primary energy source is an alternative source and in that the control means (COM, 42, 43, 44) comprise a sequencing device (MX) which is intended to trigger the control element (AD, L1, FF1, FF2) at a rate which is proportional to the frequency of the primary energy source.  12. High voltage device according to claim 11, characterized in that the sequencing device (MX) triggers the control element (AD, L1, FF1, FF2) in the last half of each half-cycle of the energy source.  13. Method for varying the high output voltage produced by a high voltage converter (T1, 18) associated with an electrostatic dust collector (26, 28), this high voltage converter being attacked by a voltage control device ( 10) which produces an output voltage varying under the effect of a control signal, while a conductive element (16) is connected to the converter so as to have a conduction level corresponding to the level with which the converter is driven to produce a high voltage, characterized in that: the voltage across the terminals of the conductive element is initially measured; we advance the control signal in a  l direction which increases the level with which the high voltage converter is attacked; the voltage across the conductive element is again measured after a predetermined interval after the first measurement of this voltage; and the control signal is varied in a direction which decreases the output voltage of the voltage control device under the effect of a predetermined variation in the level of the voltage across the conductive element, during the predetermined interval .  14. The method of claim 13, characterized in that the predetermined variation consists of a given increment of the voltage level across the conductive element (16).  15. Method according to claim 13, characterized in that the following operations are also carried out: the resulting variation of the output level of the voltage converter (T1, 18) is measured over the predetermined interval; and the control signal is varied in a direction which decreases the output level of the voltage control device (10) under the effect of a given decrement of the level of the output voltage of the voltage converter over the interval predetermined, thanks to which the reverse crown effects are reduced.  16. The method of claim 15, characterized in that the variation of the control signal on the predetermined interval has a predetermined relationship with respect to the decrease in the level of the output voltage of the high voltage converter (T1, 18 ); and in that a decrease in the level of the output voltage of the high-voltage converter exceeding the given decrement and a limit value results in a reduction of the control signal to a restoration value which corresponds to the cessation of the arc in the dust collector system.  17. The method of claim 16, characterized in that it further comprises the operation which consists in maintaining the control signal at the restoration value, at least until the level of the output voltage of the converter high voltage drops below a predetermined extinction value.