FR2424586A1 - Circuit d'addition dans le systeme binaire - Google Patents
Circuit d'addition dans le systeme binaireInfo
- Publication number
- FR2424586A1 FR2424586A1 FR7910516A FR7910516A FR2424586A1 FR 2424586 A1 FR2424586 A1 FR 2424586A1 FR 7910516 A FR7910516 A FR 7910516A FR 7910516 A FR7910516 A FR 7910516A FR 2424586 A1 FR2424586 A1 FR 2424586A1
- Authority
- FR
- France
- Prior art keywords
- circuit
- binary system
- addition circuit
- inputs
- sum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/502—Half adders; Full adders consisting of two cascaded half adders
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
- G06F2207/3868—Bypass control, i.e. possibility to transfer an operand unchanged to the output
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
Abstract
L'INVENTION CONCERNE UN CIRCUIT D'ADDITION DANS LE SYSTEME BINAIRE. IL COMPREND TROIS ENTREES A, B ET C ET DES SORTIES SOMME ET RETENUE. CE CIRCUIT, EN REPONSE A UN SIGNAL X DE SELECTION DE MODE, SE COMPORTE COMME SI LES DEUX SIGNAUX D'ENTREE PRESENTS A SES BORNES A ET B ETAIENT EGAUX, INDEPENDAMMENT DE LEURS VALEURS REELLES. DANS CETTE SITUATION, LE CIRCUIT FAIT FONCTION DE CONNECTEUR, C'EST-A-DIRE COUPLE DIRECTEMENT SON ENTREE C A SA SORTIE SOMME ET L'UNE OU L'AUTRE DE SES ENTREES A ET B A SA SORTIE RETENUE. L'INVENTION S'APPLIQUE A UN MONTAGE PERMETTANT D'EFFECTUER DES OPERATIONS D'ADDITION ET DE DECALAGE.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1618178 | 1978-04-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2424586A1 true FR2424586A1 (fr) | 1979-11-23 |
FR2424586B1 FR2424586B1 (fr) | 1986-03-07 |
Family
ID=10072634
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7910516A Expired FR2424586B1 (fr) | 1978-04-25 | 1979-04-25 | Circuit d'addition dans le systeme binaire |
Country Status (4)
Country | Link |
---|---|
US (1) | US4254471A (fr) |
JP (1) | JPS5814691B2 (fr) |
DE (1) | DE2913729C2 (fr) |
FR (1) | FR2424586B1 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2424587A1 (fr) * | 1978-04-25 | 1979-11-23 | Int Computers Ltd | Circuit additionneur binaire perfectionne |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4360891A (en) * | 1980-04-14 | 1982-11-23 | Sperry Corporation | Address and data interface unit |
JPS5896347A (ja) * | 1981-12-03 | 1983-06-08 | Toshiba Corp | 全加算器 |
US4507746A (en) * | 1982-07-28 | 1985-03-26 | The United States Of America As Represented By The Secretary Of The Army | Programmable matched filter for binary phase-coded signals |
JP2607538B2 (ja) * | 1987-08-28 | 1997-05-07 | 株式会社日立製作所 | 加算回路 |
US7991820B1 (en) | 2007-08-07 | 2011-08-02 | Leslie Imre Sohay | One step binary summarizer |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1582518A (fr) * | 1967-06-01 | 1969-10-03 | ||
US3482085A (en) * | 1966-06-23 | 1969-12-02 | Detrex Chem Ind | Binary full adder-subtractor with bypass control |
US3612847A (en) * | 1964-04-03 | 1971-10-12 | Saint Gobain | Electrical apparatus and method for adding binary numbers |
FR2424587A1 (fr) * | 1978-04-25 | 1979-11-23 | Int Computers Ltd | Circuit additionneur binaire perfectionne |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3417236A (en) * | 1964-12-23 | 1968-12-17 | Ibm | Parallel binary adder utilizing cyclic control signals |
US3571615A (en) * | 1969-06-19 | 1971-03-23 | Digital Equipment Corp | Logic circuit |
US3602705A (en) * | 1970-03-25 | 1971-08-31 | Westinghouse Electric Corp | Binary full adder circuit |
JPS48102939A (fr) * | 1972-04-07 | 1973-12-24 | ||
GB1468342A (en) * | 1973-01-28 | 1977-03-23 | Hawker Siddeley Dynamics Ld | Adder or priority-determining circuits for computers |
US3843876A (en) * | 1973-09-20 | 1974-10-22 | Motorola Inc | Electronic digital adder having a high speed carry propagation line |
US3932734A (en) * | 1974-03-08 | 1976-01-13 | Hawker Siddeley Dynamics Limited | Binary parallel adder employing high speed gating circuitry |
-
1979
- 1979-03-12 US US06/019,765 patent/US4254471A/en not_active Expired - Lifetime
- 1979-04-05 DE DE2913729A patent/DE2913729C2/de not_active Expired
- 1979-04-11 JP JP54044123A patent/JPS5814691B2/ja not_active Expired
- 1979-04-25 FR FR7910516A patent/FR2424586B1/fr not_active Expired
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3612847A (en) * | 1964-04-03 | 1971-10-12 | Saint Gobain | Electrical apparatus and method for adding binary numbers |
US3482085A (en) * | 1966-06-23 | 1969-12-02 | Detrex Chem Ind | Binary full adder-subtractor with bypass control |
FR1582518A (fr) * | 1967-06-01 | 1969-10-03 | ||
FR2424587A1 (fr) * | 1978-04-25 | 1979-11-23 | Int Computers Ltd | Circuit additionneur binaire perfectionne |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2424587A1 (fr) * | 1978-04-25 | 1979-11-23 | Int Computers Ltd | Circuit additionneur binaire perfectionne |
Also Published As
Publication number | Publication date |
---|---|
DE2913729C2 (de) | 1984-10-11 |
JPS5814691B2 (ja) | 1983-03-22 |
US4254471A (en) | 1981-03-03 |
FR2424586B1 (fr) | 1986-03-07 |
JPS54141535A (en) | 1979-11-02 |
DE2913729A1 (de) | 1979-11-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
TP | Transmission of property | ||
ST | Notification of lapse |