FR2267588B1 - - Google Patents

Info

Publication number
FR2267588B1
FR2267588B1 FR7511095A FR7511095A FR2267588B1 FR 2267588 B1 FR2267588 B1 FR 2267588B1 FR 7511095 A FR7511095 A FR 7511095A FR 7511095 A FR7511095 A FR 7511095A FR 2267588 B1 FR2267588 B1 FR 2267588B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7511095A
Other versions
FR2267588A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of FR2267588A1 publication Critical patent/FR2267588A1/fr
Application granted granted Critical
Publication of FR2267588B1 publication Critical patent/FR2267588B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
FR7511095A 1974-04-10 1975-04-09 Expired FR2267588B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/459,504 US3979726A (en) 1974-04-10 1974-04-10 Apparatus for selectively clearing a cache store in a processor having segmentation and paging

Publications (2)

Publication Number Publication Date
FR2267588A1 FR2267588A1 (fr) 1975-11-07
FR2267588B1 true FR2267588B1 (fr) 1978-09-01

Family

ID=23825057

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7511095A Expired FR2267588B1 (fr) 1974-04-10 1975-04-09

Country Status (6)

Country Link
US (1) US3979726A (fr)
JP (1) JPS50138738A (fr)
CA (1) CA1033464A (fr)
DE (1) DE2515696C2 (fr)
FR (1) FR2267588B1 (fr)
GB (1) GB1494365A (fr)

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5226124A (en) * 1975-08-22 1977-02-26 Fujitsu Ltd Buffer memory control unit
FR2348544A1 (fr) * 1976-04-15 1977-11-10 Honeywell Bull Soc Ind Ensemble double de memoire associative
US4096568A (en) * 1976-09-24 1978-06-20 Sperry Rand Corporation Virtual address translator
US4197580A (en) * 1978-06-08 1980-04-08 Bell Telephone Laboratories, Incorporated Data processing system including a cache memory
US4277826A (en) * 1978-10-23 1981-07-07 Collins Robert W Synchronizing mechanism for page replacement control
DE2947115A1 (de) * 1978-12-11 1980-06-26 Honeywell Inf Systems Loeschanordnung fuer einen cache- speicher eines prozessors in einem multiprozessorsystem
US4282572A (en) * 1979-01-15 1981-08-04 Ncr Corporation Multiprocessor memory access system
US4298929A (en) * 1979-01-26 1981-11-03 International Business Machines Corporation Integrated multilevel storage hierarchy for a data processing system with improved channel to memory write capability
US4264953A (en) * 1979-03-30 1981-04-28 Honeywell Inc. Virtual cache
FR2472232B1 (fr) * 1979-12-14 1988-04-22 Honeywell Inf Systems Dispositif et procede d'effacement d'antememoire
US4471429A (en) * 1979-12-14 1984-09-11 Honeywell Information Systems, Inc. Apparatus for cache clearing
US4386402A (en) * 1980-09-25 1983-05-31 Bell Telephone Laboratories, Incorporated Computer with dual vat buffers for accessing a common memory shared by a cache and a processor interrupt stack
US4400774A (en) * 1981-02-02 1983-08-23 Bell Telephone Laboratories, Incorporated Cache addressing arrangement in a computer system
DE3138972A1 (de) * 1981-09-30 1983-04-14 Siemens AG, 1000 Berlin und 8000 München Onchip mikroprozessorchachespeichersystem und verfahren zu seinem betrieb
JPS58147879A (ja) * 1982-02-26 1983-09-02 Toshiba Corp キヤツシユメモリ制御方式
US4567578A (en) * 1982-09-08 1986-01-28 Harris Corporation Cache memory flush scheme
US4714990A (en) * 1982-09-18 1987-12-22 International Computers Limited Data storage apparatus
US4819154A (en) * 1982-12-09 1989-04-04 Sequoia Systems, Inc. Memory back up system with one cache memory and two physically separated main memories
EP0128945B1 (fr) * 1982-12-09 1991-01-30 Sequoia Systems, Inc. Systeme de sauvegarde de memoire
US4701844A (en) * 1984-03-30 1987-10-20 Motorola Computer Systems, Inc. Dual cache for independent prefetch and execution units
FR2571163B1 (fr) * 1984-09-28 1989-02-10 Nec Corp Systeme de traitement de donnees pour traitement de vecteurs ayant un ensemble de commande d'invalidation d'antememoire.
JP2539357B2 (ja) 1985-03-15 1996-10-02 株式会社日立製作所 デ−タ処理装置
US5241638A (en) * 1985-08-12 1993-08-31 Ceridian Corporation Dual cache memory
US4755936A (en) * 1986-01-29 1988-07-05 Digital Equipment Corporation Apparatus and method for providing a cache memory unit with a write operation utilizing two system clock cycles
US5349672A (en) * 1986-03-17 1994-09-20 Hitachi, Ltd. Data processor having logical address memories and purge capabilities
US5237671A (en) * 1986-05-02 1993-08-17 Silicon Graphics, Inc. Translation lookaside buffer shutdown scheme
US4885680A (en) * 1986-07-25 1989-12-05 International Business Machines Corporation Method and apparatus for efficiently handling temporarily cacheable data
US4833601A (en) * 1987-05-28 1989-05-23 Bull Hn Information Systems Inc. Cache resiliency in processing a variety of address faults
US5214770A (en) * 1988-04-01 1993-05-25 Digital Equipment Corporation System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command
WO1989009442A1 (fr) * 1988-04-01 1989-10-05 Digital Equipment Corporation Commande "flush-on-rei" d'antememoire d'instruction
US5222224A (en) * 1989-02-03 1993-06-22 Digital Equipment Corporation Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system
US5041962A (en) * 1989-04-14 1991-08-20 Dell Usa Corporation Computer system with means for regulating effective processing rates
JPH0748190B2 (ja) * 1990-01-22 1995-05-24 株式会社東芝 キャッシュメモリ内蔵マイクロプロセッサ
AU8870291A (en) * 1990-10-12 1992-05-20 Intel Corporation Cache controller and associated method for remapping cache address bits
GB9118312D0 (en) * 1991-08-24 1991-10-09 Motorola Inc Real time cache implemented by dual purpose on-chip memory
JP3242161B2 (ja) * 1992-09-11 2001-12-25 株式会社日立製作所 データプロセッサ
USRE38651E1 (en) * 1994-05-18 2004-11-09 Altera Corporation Variable depth and width memory device
AU2663095A (en) * 1994-06-10 1996-01-05 Sequoia Systems, Inc. Main memory system and checkpointing protocol for fault-tolerant computer system
US6256694B1 (en) * 1994-06-30 2001-07-03 Compaq Computer Corporation Distributed early arbitration
JP3086779B2 (ja) * 1995-06-19 2000-09-11 株式会社東芝 メモリ状態復元装置
US5737514A (en) * 1995-11-29 1998-04-07 Texas Micro, Inc. Remote checkpoint memory system and protocol for fault-tolerant computer system
US5745672A (en) * 1995-11-29 1998-04-28 Texas Micro, Inc. Main memory system and checkpointing protocol for a fault-tolerant computer system using a read buffer
US5751939A (en) * 1995-11-29 1998-05-12 Texas Micro, Inc. Main memory system and checkpointing protocol for fault-tolerant computer system using an exclusive-or memory
US5864657A (en) * 1995-11-29 1999-01-26 Texas Micro, Inc. Main memory system and checkpointing protocol for fault-tolerant computer system
JP2656765B2 (ja) * 1996-01-16 1997-09-24 株式会社日立製作所 データ処理装置
TW379298B (en) * 1996-09-30 2000-01-11 Toshiba Corp Memory updating history saving device and memory updating history saving method
JP3620181B2 (ja) * 1996-12-05 2005-02-16 富士通株式会社 半導体装置及びリードアクセス方法
US6157981A (en) * 1998-05-27 2000-12-05 International Business Machines Corporation Real time invariant behavior cache
US6886063B1 (en) * 1999-11-10 2005-04-26 Digi International, Inc. Systems, devices, structures, and methods to share resources among entities
US6581142B1 (en) * 2000-09-01 2003-06-17 International Business Machines Corporation Computer program product and method for partial paging and eviction of microprocessor instructions in an embedded computer
JP2018013951A (ja) * 2016-07-21 2018-01-25 京セラドキュメントソリューションズ株式会社 電子機器及び情報更新プログラム
EP3924832A4 (fr) * 2019-02-14 2022-11-23 Telefonaktiebolaget Lm Ericsson (Publ) Procédés et dispositifs de commande de gestion de mémoire
US11074194B2 (en) * 2019-02-21 2021-07-27 International Business Machines Corporation Managing direct memory access
CN112328587A (zh) * 2020-11-18 2021-02-05 山东健康医疗大数据有限公司 ElasticSearch的数据处理方法和装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588829A (en) * 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store
US3588839A (en) * 1969-01-15 1971-06-28 Ibm Hierarchical memory updating system
US3800286A (en) * 1972-08-24 1974-03-26 Honeywell Inf Systems Address development technique utilizing a content addressable memory
US3800291A (en) * 1972-09-21 1974-03-26 Ibm Data processing system memory relocation apparatus and method
US3800292A (en) * 1972-10-05 1974-03-26 Honeywell Inf Systems Variable masking for segmented memory
US3848234A (en) * 1973-04-04 1974-11-12 Sperry Rand Corp Multi-processor system with multiple cache memories
US3840862A (en) * 1973-09-27 1974-10-08 Honeywell Inf Systems Status indicator apparatus for tag directory in associative stores
US3845474A (en) * 1973-11-05 1974-10-29 Honeywell Inf Systems Cache store clearing operation for multiprocessor mode
US3896419A (en) * 1974-01-17 1975-07-22 Honeywell Inf Systems Cache memory store in a processor of a data processing system

Also Published As

Publication number Publication date
CA1033464A (fr) 1978-06-20
JPS50138738A (fr) 1975-11-05
US3979726A (en) 1976-09-07
FR2267588A1 (fr) 1975-11-07
GB1494365A (en) 1977-12-07
DE2515696C2 (de) 1984-09-06
DE2515696A1 (de) 1975-10-23

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Legal Events

Date Code Title Description
ST Notification of lapse