FR2256511A1 - Non-volatile memory cell - has floating gate conductor layer between isolation layers - Google Patents
Non-volatile memory cell - has floating gate conductor layer between isolation layersInfo
- Publication number
- FR2256511A1 FR2256511A1 FR7400070A FR7400070A FR2256511A1 FR 2256511 A1 FR2256511 A1 FR 2256511A1 FR 7400070 A FR7400070 A FR 7400070A FR 7400070 A FR7400070 A FR 7400070A FR 2256511 A1 FR2256511 A1 FR 2256511A1
- Authority
- FR
- France
- Prior art keywords
- floating gate
- gate conductor
- conductor layer
- pockets
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 title abstract 4
- 238000002955 isolation Methods 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 abstract 2
- 239000002184 metal Substances 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
- H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
- H10D30/686—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection using hot carriers produced by avalanche breakdown of PN junctions, e.g. floating gate avalanche injection MOS [FAMOS]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7400070A FR2256511A1 (en) | 1974-01-02 | 1974-01-02 | Non-volatile memory cell - has floating gate conductor layer between isolation layers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7400070A FR2256511A1 (en) | 1974-01-02 | 1974-01-02 | Non-volatile memory cell - has floating gate conductor layer between isolation layers |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2256511A1 true FR2256511A1 (en) | 1975-07-25 |
FR2256511B1 FR2256511B1 (enrdf_load_stackoverflow) | 1977-09-09 |
Family
ID=9133036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7400070A Granted FR2256511A1 (en) | 1974-01-02 | 1974-01-02 | Non-volatile memory cell - has floating gate conductor layer between isolation layers |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2256511A1 (enrdf_load_stackoverflow) |
-
1974
- 1974-01-02 FR FR7400070A patent/FR2256511A1/fr active Granted
Also Published As
Publication number | Publication date |
---|---|
FR2256511B1 (enrdf_load_stackoverflow) | 1977-09-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |