FR2083421B1 - - Google Patents
Info
- Publication number
- FR2083421B1 FR2083421B1 FR7109677A FR7109677A FR2083421B1 FR 2083421 B1 FR2083421 B1 FR 2083421B1 FR 7109677 A FR7109677 A FR 7109677A FR 7109677 A FR7109677 A FR 7109677A FR 2083421 B1 FR2083421 B1 FR 2083421B1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19702013220 DE2013220A1 (de) | 1970-03-19 | 1970-03-19 | Verfahren zum Herstellen einer Transistor anordnung aus Silicium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2083421A1 FR2083421A1 (https=) | 1971-12-17 |
| FR2083421B1 true FR2083421B1 (https=) | 1977-01-21 |
Family
ID=5765627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7109677A Expired FR2083421B1 (https=) | 1970-03-19 | 1971-03-19 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US3754321A (https=) |
| AT (1) | AT312054B (https=) |
| CH (1) | CH522954A (https=) |
| DE (1) | DE2013220A1 (https=) |
| FR (1) | FR2083421B1 (https=) |
| GB (1) | GB1310806A (https=) |
| NL (1) | NL7103588A (https=) |
| SE (1) | SE378154B (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4999318A (en) * | 1986-11-12 | 1991-03-12 | Hitachi, Ltd. | Method for forming metal layer interconnects using stepped via walls |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3523038A (en) * | 1965-06-02 | 1970-08-04 | Texas Instruments Inc | Process for making ohmic contact to planar germanium semiconductor devices |
| US3571913A (en) * | 1968-08-20 | 1971-03-23 | Hewlett Packard Co | Method of making ohmic contact to a shallow diffused transistor |
| ES374318A1 (es) * | 1968-12-10 | 1972-03-16 | Matsushita Electronics Corp | Un metodo de fabricar un dispositivo semiconductor sensiblea la presion. |
-
1970
- 1970-03-19 DE DE19702013220 patent/DE2013220A1/de active Pending
-
1971
- 1971-03-02 CH CH304271A patent/CH522954A/de not_active IP Right Cessation
- 1971-03-09 AT AT203071A patent/AT312054B/de not_active IP Right Cessation
- 1971-03-17 NL NL7103588A patent/NL7103588A/xx unknown
- 1971-03-18 US US00125701A patent/US3754321A/en not_active Expired - Lifetime
- 1971-03-19 SE SE7103606A patent/SE378154B/xx unknown
- 1971-03-19 FR FR7109677A patent/FR2083421B1/fr not_active Expired
- 1971-04-19 GB GB2481871*A patent/GB1310806A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2013220A1 (de) | 1971-11-25 |
| FR2083421A1 (https=) | 1971-12-17 |
| CH522954A (de) | 1972-05-15 |
| GB1310806A (en) | 1973-03-21 |
| NL7103588A (https=) | 1971-09-21 |
| SE378154B (https=) | 1975-08-18 |
| AT312054B (de) | 1973-12-10 |
| US3754321A (en) | 1973-08-28 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |