FI20095885A0 - A method for verifying integrated circuit design in a verification environment - Google Patents

A method for verifying integrated circuit design in a verification environment

Info

Publication number
FI20095885A0
FI20095885A0 FI20095885A FI20095885A FI20095885A0 FI 20095885 A0 FI20095885 A0 FI 20095885A0 FI 20095885 A FI20095885 A FI 20095885A FI 20095885 A FI20095885 A FI 20095885A FI 20095885 A0 FI20095885 A0 FI 20095885A0
Authority
FI
Finland
Prior art keywords
integrated circuit
method
circuit design
verification environment
verifying integrated
Prior art date
Application number
FI20095885A
Other languages
Finnish (fi)
Swedish (sv)
Inventor
Martti Venell
Original Assignee
Martti Venell
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Martti Venell filed Critical Martti Venell
Priority to FI20095885A priority Critical patent/FI20095885A0/en
Publication of FI20095885A0 publication Critical patent/FI20095885A0/en

Links

Classifications

    • G06F30/33
FI20095885A 2009-08-27 2009-08-27 A method for verifying integrated circuit design in a verification environment FI20095885A0 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FI20095885A FI20095885A0 (en) 2009-08-27 2009-08-27 A method for verifying integrated circuit design in a verification environment

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20095885A FI20095885A0 (en) 2009-08-27 2009-08-27 A method for verifying integrated circuit design in a verification environment
PCT/FI2010/050250 WO2011023847A1 (en) 2009-08-27 2010-03-30 Method for integrated circuit design verification in a verification environment

Publications (1)

Publication Number Publication Date
FI20095885A0 true FI20095885A0 (en) 2009-08-27

Family

ID=41050709

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20095885A FI20095885A0 (en) 2009-08-27 2009-08-27 A method for verifying integrated circuit design in a verification environment

Country Status (2)

Country Link
FI (1) FI20095885A0 (en)
WO (1) WO2011023847A1 (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5831996A (en) * 1996-10-10 1998-11-03 Lucent Technologies Inc. Digital circuit test generator
US6453437B1 (en) * 1999-07-01 2002-09-17 Synopsys, Inc. Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation
US7076712B2 (en) * 2003-05-22 2006-07-11 Fujitsu Limited Generating a test sequence using a satisfiability technique
US7353470B2 (en) * 2005-02-14 2008-04-01 On-Chip Technologies, Inc. Variable clocked scan test improvements
JP2007024513A (en) * 2005-07-12 2007-02-01 Nec Electronics Corp Logic estimation method for logic circuit
US7895029B2 (en) * 2007-10-30 2011-02-22 International Business Machines Corporation System and method of automating the addition of RTL based critical timing path counters to verify critical path coverage of post-silicon software validation tools
JP5001190B2 (en) * 2008-02-14 2012-08-15 パシフィック・デザイン株式会社 LSI design verification system, LSI design verification method and program thereof

Also Published As

Publication number Publication date
FI20095885D0 (en)
WO2011023847A1 (en) 2011-03-03

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Legal Events

Date Code Title Description
FD Application lapsed