FI129707B - Led driver, and method for establishing information concerning input voltage - Google Patents

Abstract

A driver device for semiconductor light sources comprises a primary side and a galvanically isolated secondary side. A power input (102) on said primary side receives an input voltage at an amplitude and a frequency. A power output (103) on said secondary side outputs output power to said semiconductor light sources. A galvanically isolated voltage converter (104, 105) is coupled between said power input (102) and said power output (103), and a control circuit (106) is provided on said secondary side. The driver device comprises PWM encoder means (108) on said primary side, configured to encode primary information indicative of said amplitude and said frequency into a PWM signal. The driver device comprises also PWM decoder means (109) on said secondary side, configured to decode said PWM signal into secondary information indicative of said amplitude and said frequency for use by said control circuit (106). A galvanically isolating signal path (110) is provided for conveying said PWM signal from said PWM encoder means (108) to said PWM decoder means (109).

Description

LED DRIVER, AND METHOD FOR ESTABLISHING INFORMATION CONCERNING INPUT VOLTAGE

FIELD OF THE INVENTION The invention concerns the technical field of driver devices for semiconductor light sources. In particular the invention concerns a way in which a processor in such a driver device may keep track on appropriate characteristics of an input voltage to the driver device.

BACKGROUND OF THE INVENTION A driver device for semiconductor light sources, or a LED driver for short, is a device that receives input power from an electricity network and converts it into output power at voltage and current levels suitable for the semiconductor light sources coupled to its output. The input power comes typically in the form of AC mains, such as 230 volts AC at 50 Hz or 120 volts AC at 60 Hz. In many cases the LED driv- ers are designed to accept a wide variety of input voltages, including DC. For a processor that takes part in control- ling the operation of a LED driver, information about the voltage level and freguency of the input voltage N may be useful. The processor may utilize such infor- N mation for example to examine, whether the delivery of 3 input power takes place as usual or whether there is e 30 some exceptional situation like a power shortage. Some z standards, like the newer versions of the DALI (Digi- * tal Addressable Lighting Interface) standard for exam- 3 ple, may even require establishing such information as S a mandatory function. S 35 For the person skilled in the art it is rela- tively easy to present ways in which a processor may be made aware of a voltage level and frequency of an AC voltage occurring in a piece of circuitry to which the processor is coupled. However, an optimal solution in terms of simplicity, cost effectiveness, reliabil- ity, and versatility has not been seen in prior art. Such a solution should take into account the possibil- ity that the processor may be located behind a galvan- ic isolation with respect to the AC voltage that is to be monitored.

SUMMARY It is an objective to present a LED driver and a method in which a processor located behind a galvanic isolation can keep track of the voltage level and frequency of an input voltage. Another objective is to ensure that the circuit solution and method are reliable in operation and adaptable to a wide variety of LED drivers, yet incur only low cost in manufactur- ing. A further objective is to implement the method so that the required components need only a modest amount of space on the circuit board of the LED driver. A yet further objective is to ensure that the control pro- gram executed by the processor can be kept simple and well organized. These and further advantageous objectives are o achieved by using a single PWM (pulse width modulated) N signal to convey information about the detected input A voltage across the galvanic isolation and using two ? 30 detection methods to decode from said PWM signal both 0 the voltage level and the frequency of the original E monitored input voltage. o According to a first aspect there is provided 3 a driver device for semiconductor light sources, com- N 35 prising a primary side and a secondary side galvani- N cally isolated from said primary side. A power input is provided on said primary side for receiving an in-

put voltage that has an amplitude and a frequency, and a power output is provided on said secondary side for outputting output power to said semiconductor light sources.

A galvanically isolated voltage converter is coupled between said power input and said power out- put, and a control circuit is provided on said second- ary side.

The driver device comprises PWM encoder means on said primary side, configured to encode pri- mary information indicative of said amplitude and said freguency into a PWM signal.

The driver device com- prises also PWM decoder means on said secondary side, configured to decode said PWM signal into secondary information indicative of said amplitude and said fre- guency for use by said control circuit.

A galvanically isolating signal path is provided for conveying said PWM signal from said PWM encoder means to said PWM de- coder means.

According to an embodiment said PWM encoder means are coupled to receive an input signal indica- tive of said amplitude and frequency of said input voltage and configured to generate a PWM signal indic- ative of said input signal.

This involves the ad- vantage that the topology of the primary side can be kept relatively simple, and the information to be en- coded remains free of interference.

According to an embodiment said PWM encoder means are coupled to receive a derived version of said N input voltage as said input signal, and the driver de- N vice comprises at least one of the following to pro- 3 30 duce said derived version: a filter, a rectifier, a 0 scaler.

This involves the advantage that a simple and Ek advantageously priced off-the-shelf component can be * used as said PWM encoder means. 3 According to an embodiment said PWM encoder S 35 means are configured to produce said PWM signal at a S PWM pulse freguency higher than 500 Hz.

This involves the advantage that commonly encountered input AC fre-

quencies like 50 Hz or 60 Hz can be handled accurately and unambiguously.

According to an embodiment said PWM encoder means are configured to produce said PWM signal at a PWM pulse frequency lower than 5 kHz. This involves the advantage that a low-cost, yet reliable galvani- cally isolating component can be used to convey the PWM signal from the primary side to the secondary side, and that electromagnetic interference levels can be kept low.

According to an embodiment the galvanically isolating signal path comprises an optoisolator. This involves the advantage that manufacturing cost can be kept low and the use of circuit board space for this purpose is modest.

According to an embodiment said PWM decoder means comprise a first decoder and a second decoder, of which said first decoder is configured to decode sald PWM signal into an amplitude indicator signal and said second decoder is configured to decode said PWM signal into a frequency indicator signal. The control circuit may then be coupled to receive said amplitude indicator signal and said frequency indicator signal. This involves the advantage that the information can be delivered to the control circuit in a form that the control circuit can accept and utilize with only rea- sonable requirements to its programming.

x According to an embodiment said first decoder N comprises a first integrator, configured to produce 3 30 said amplitude indicator signal by integrating said 0 PWM signal over a first integration period, and said I second decoder comprises a second integrator, config- * ured to produce said freguency indicator signal by in- 3 tegrating said PWM signal over a second integration S 35 period, of which said second integration period is S shorter than said first integration period. This in-

volves the advantage that the decoders can be imple- mented with simple and reliable low-cost circuitry. According to an embodiment the driver device comprises a voltage source on said secondary side and 5 a controllable switch coupled between said voltage source and each of said first and second decoders. The controllable switch may have a control input, which is coupled to receive the PWM signal from said galvani- cally isolating signal path. This involves the ad- vantage of making the decoding essentially independent of the power levels that can be conveyed over the gal- vanically isolating signal path.

According to an embodiment said control cir- cuit is configured to derive detected values of said amplitude and said freguency from said secondary in- formation and to store the derived detected values in- to memory. This involves the advantage that the con- trol circuit may be made to operate according to e.g. the DALI standard.

According to a second aspect there is provid- ed a method for establishing information concerning an input voltage of a driver device for semiconductor light sources. The method comprises encoding primary information indicative of an amplitude and a frequency of said input voltage into a PWM signal, conveying said PWM signal through a galvanically isolating sig- nal path from a primary side to a secondary side of x the driver device, decoding said PWM signal into sec- N ondary information indicative of said amplitude and 3 30 sald frequency on said secondary side, and using the 0 secondary information for controlling the operation of =E the driver device.

* According to an embodiment producing said 3 primary information comprises at least one of: filter- S 35 ing the input voltage, rectifying the input voltage, S scaling the input voltage. This involves the advantage that a simple and advantageously priced off-the-shelf component can be used for the PWM encoding. According to an embodiment said PWM signal has a PWM pulse frequency higher than 500 Hz. This in- volves the advantage that commonly encountered input AC frequencies like 50 Hz or 60 Hz can be handled ac- curately and unambiguously. According to an embodiment said PWM pulse frequency is lower than 5 kHz. This involves the ad- vantage that a low-cost, yet reliable galvanically isolating component can be used to convey the PWM sig- nal from the primary side to the secondary side, and that electromagnetic interference levels can be kept low.

According to an embodiment said decoding of the PWM signal comprises producing an amplitude indi- cator signal and a frequency indicator signal, of which the amplitude indicator signal is produced by integrating said PWM signal over a first integration period and said frequency indicator signal is produced by integrating said PWM signal over a second integra- tion period, which is shorter than said first integra- tion period. This involves the advantage that the de- coders can be implemented with simple and reliable low-cost circuitry.

According to an embodiment said amplitude in- dicator signal and said frequency indicator signal are x produced simultaneously in parallel decoding branches. N This involves the advantage that a control circuit has 3 30 full freedom concerning how and according to which 0 timetable it wants to use the indicator signals. = a 3 BRIEF DESCRIPTION OF THE DRAWINGS S 35 The accompanying drawings, which are included N to provide a further understanding of the invention and constitute a part of this specification, illus-

trate embodiments of the invention and together with the description help to explain the principles of the invention. In the drawings: Figure 1 illustrates a principle of estab- lishing information concerning input voltage, figure 2 illustrates how a PWM signal may represent an AC voltage in certain cases, figure 3 illustrates a principle of deriving amplitude and frequency information from a PWM encoded signal, figure 4 illustrates an arrangement according to an embodiment, figure 5 illustrates decoder means according to an embodiment, and figure 6 illustrates an arrangement according to an embodiment.

DETAILED DESCRIPTION Fig. 1 is a simplified block diagram of a driver device for semiconductor light sources. It com- prises a primary side and a secondary side, of which the latter is galvanically isolated from the primary side as shown by the borderline 101. There is a power input 102 on the primary side for receiving an input voltage Vin that has, or is at least supposed to have, o an amplitude and a frequency. For the purpose of ac- N cepting also DC input voltage it may be defined here A that also a DC input voltage has a frequency, it is ? 30 just zero. The driver device has a power output 103 on 0 the secondary side for outputting output power (output E voltage Vout times output current Iout) to the semi- © conductor light sources (not shown in fig. 1). 3 The driver device of fig. 1 comprises a gal- N 35 vanically isolated voltage converter coupled between N the power input 102 and the power output 103. In fig. l it is shown to consist of a primary stage 104 and a secondary stage 105. The galvanically isolated trans- fer of power between the primary and secondary stages 104 and 105 may take place through a transformer, which is not separately shown in fig. 1. A control circuit 106 is provided on the sec- ondary side of the driver device.

The control circuit 106 may be a processor or a microcontroller, or it may consist of two or more processors and/or microcontrol- lers.

It may have various tasks in controlling the op- eration of the driver device: for example, it may be responsible for communicating with other devices through a control connection 107. The control connec- tion 107 may be a wired or wireless connection, and it may be used for example to make the control circuit 106 receive commands such as dimming commands, memory read and/or write operations, and others.

For the pur- poses of this description the concept ”controlling the operation” of the driver device should be understood in a wide sense to cover all kinds of operations that a control circuit 106 may have been programmed to do: as an example, using a memory to store detected diag- nostic values for possible later use may count as such controlling.

The driver device comprises PWM encoder means 108 on the primary side.

The PWM encoder means 108 are configured to encode information indicative of the am- plitude and frequency of the input voltage Vin into a N PWM signal.

For the purpose of unambiguous reference, N the information to be encoded is here called primary 3 30 information.

As shown by the arrow from block 104 to 0 block 108, the primary information may come from the =E primary stage 104 of the galvanically isolated voltage * converter.

It may also come directly from the power 3 input 102. S 35 The driver device comprises PWM decoder means S 109 on the secondary side.

The PWM decoder means 109 are configured to decode the PWM signal coming from the PWM encoder means 108 into what is here called secondary information. It is indicative of the ampli- tude and the frequency of the input voltage Vin. The secondary information becomes available for the con- trol circuit 106 for use in controlling the operation of the driver device, as shown by the two arrows from block 109 to block 106 in fig. 1. The driver device comprises a galvanically isolating signal path 110 for conveying the PWM signal from the PWM encoder means 108 to the PWM decoder means 109. The galvanically isolating signal path 110 may cross the borderline 101 between the primary and secondary sides of the driver device through a suita- ble component that implements galvanic isolation while allowing the transfer of information. Examples of such components are optoisolators, signal transformers, wireless transceivers, and the like.

Fig. 2 shows some examples of how a PWM sig- nal, also frequently referred to as a PWM pulse train, can represent a voltage signal in various cases. Graph 201 represents an AC mains voltage in a normal case, where the AC voltage has a nominal amplitude A and frequency, such as 230 V and 50 Hz for example. The duty cycle of the PWM signal 202 varies between cer- tain minimum and maximum values in concert with the varying momentary absolute voltage value, said varia- tion taking place at twice the AC frequency. The mini- N mum and maximum values of the duty cycle may be 0 and N 100%. Alternatively, the minimum duty cycle may be 3 30 larger than 0% and/or the maximum duty cycle may be 0 smaller than 100%, depending on how the voltage-to-PWM Ek conversion has been set up. Some other reference may * be used than 0 V. For example, if the maximum negative 3 value -A of the momentary voltage is used as a refer- S 35 ence, the frequency at which the PWM duty cycle varies S is the same as the AC frequency.

Graph 203 represents an AC voltage that has the same frequency as that of graph 201 but a smaller amplitude. As a result, the duty cycle of the PWM sig- nal 204 varies between the same minimum value but a lower maximum value than those of the PWM signal 202 described above. Graph 205 represents an AC voltage that has the same amplitude as that of graph 201 but a higher freguency. As a result, the duty cycle of the PWM signal 206 varies between the same minimum and maximum values as those of the PWM signal 202 but quicker. Graph 207 represents a DC voltage. As a re- sult, the duty cycle of the PWM signal 208 is con- stant.

Comparing the various cases in fig. 2 the following general conclusions can be drawn concerning a PWM signal that results from a voltage-to-PWM con- version: - the frequency of the original AC voltage can be found by detecting the rate at which the duty cycle varies between two regularly occurring values, - the amplitude of the original AC voltage can be found by detecting a suita- ble characteristic indicative of the maxi- mum duty cycle that the PWM signal goes to (e.g. the mean value of the PWM duty cycle over one full cycle of the original AC N voltage). N Fig. 3 can be considered as a principal il- 3 30 lustration of a method for establishing information 0 concerning an input voltage of a driver device for =E semiconductor light sources. The connection between * blocks 301 and 302 in fig. 3 represents taking - or 3 establishing - primary information that is indicative S 35 of the amplitude and frequency of the input voltage, S and block 302 represents encoding said primary infor- mation into a PWM signal. The PWM signal is conveyed through a galvanically isolating signal path from a primary side to a secondary side of the driver device, as illustrated by crossing the dashed line.

On the secondary side blocks 303 and 304 represent decoding the PWM signal into secondary information indicative of the amplitude of the input voltage (block 303) and frequency of the input voltage (block 304). This sec- ondary information can then be used for controlling the operation of the driver device.

Fig. 4 is a more hardware-oriented way of looking at basically the same thing.

The voltage-to- PWM encoder 401 represents what was called the PWM en- coder means above.

It is coupled to receive an input signal 402 indicative of the amplitude and frequency of the input voltage and configured to generate a PWM signal 403 indicative of the input signal 402. The in- put signal 402 may be the input voltage 404 of the driver device as such, or it may be a derived version thereof.

As examples of how a derived version can be produced, fig. 4 introduces filter(s), rectifier(s), and scaler(s). Filtering the input voltage may be used for example to fight effects of electromagnetic inter- ference; rectifying the input voltage can be used to make the voltage-to-PWM conversion more straightfor- ward and to set the reference level to 0 V, and scal- ing the input voltage may be used to select an input signal level that is most convenient for the operation

N of the voltage-to-PWM encoder 401. N The PWM pulse frequency of the PWM signal 403 3 30 should be selected so that the PWM signal 403 can car- 0 ry enough information of the characteristics of the Ek input voltage.

If prior information is available of * the expected input voltage frequencies that are to be 3 encountered, the PWM pulse frequency may be selected S 35 high enough so that the variations in duty cycle can S unambiguously reflect the input voltage frequencies that will occur in practice.

Another criterion to be considered is the signal transferring capabilities of the galvanic isolator 406 that will convey the PWM signal across the borderline between the primary and secondary sides of the driver device. If a signal transformer is used, a higher PWM pulse frequency typ- ically means smaller size. If an optoisolator is used, it may be advantageous to select the PWM pulse fre- quency not too high so that the optoisolator may be of the “slow” kind, which are usually cheaper and may be more reliable in long-term use than “fast” optoisola- tors.

The principle of using only one galvanic iso- lator to convey only one PWM signal from which both the amplitude and the freguency of the input voltage can be decoded is particularly advantageous, because it halves the incurred manufacturing cost compared to solutions where two galvanic isolators would need to be provided: one for conveying information indicative of the voltage and another for conveying information indicative of the frequency.

According to one embodiment, the PWM encoder means are configured to produce the PWM signal 403 at a PWM pulse frequency higher than 500 Hz. This should be high enough to maintain enough information about the typically occurring AC mains frequencies like 50 Hz or 60 Hz. On the other hand, the PWM encoder means may be configured to produce said PWM signal at a PWM N pulse freguency lower than 5 kHz, which would then en- N able using an advantageous, "slow” optoisolator. An 3 30 example of a PWM pulse frequency to be selected is 2 0 kHz. =E Fig. 3 illustrates slow and fast filtering * operations 303 and 304 as examples of PWM decoding. 3 Fig. 4 uses the term integrator and shows how the PWM S 35 decoder means may comprise a first decoder (or first S integrator) 407 and a second decoder (or second inte- grator) 408. Of these, the first decoder (or first in-

tegrator) 407 is configured to decode the PWM signal 403 into an amplitude indicator signal 409 and the second decoder (or second integrator) 408 is config- ured to decode the PWM signal 403 into a frequency in- dicator signal 410. The control circuit, shown as a processor 411 in fig. 4, is coupled to receive the am- plitude indicator signal 409 and the frequency indica- tor signal 410.

The term integrator is easily understandable by comparing to the PWM pulse trains in fig. 2. The first integrator 407 of fig. 4 may be configured to produce the amplitude indicator signal 409 by inte- grating the PWM signal 403 for a first integration pe- riod, which is a so-called “long” integration period. It may be of the order of the period of a typical ex- pected AC input voltage signal. As the variation in the duty cycle of the PWM signals 202, 204, and 206 makes two complete rounds during each period of the corresponding AC voltage waveforms 201, 203, and 205, integrating over the period of the AC voltage waveform gives essentially a value that is proportional to the amplitude of the corresponding AC waveform. On the other hand, the second integrator 408 of fig. 4 may be configured to produce the freguency indicator signal 410 by integrating the PWM signal 403 for a second in- tegration period, which is shorter than the first in- tegration period. The length of such a second integra- N tion period may be for example only few cycles of the N PWM pulse train. As a result, the cyclic variation in 3 30 the PWM duty cycle becomes visible: the frequency in- 0 dicator signal 410 is basically a scaled representa- =E tion of the original AC input voltage, with its phase * lagging that of the original AC input voltage by about 3 the length of the integration period. S 35 Fig. 5 illustrates an example of how the PWM S decoder means may be built on the secondary side of the driver device. According to fig. 5, the driver de-

vice comprises a voltage source, shown in fig. 5 as the voltage regulator 501, on the secondary side.

The same voltage source may deliver (regulated) operating voltage (s) also to other circuits on the secondary side, but this is not a necessary requirement.

Further according to fig. 5, the driver device comprises a controllable switch 502 coupled between the voltage source 501 and each of the first and second decoders, which appear as the slow filter 503 and the fast fil- ter 504 respectively in fig. 5. The switch 502 has a control input 505, which is coupled to receive the PWM signal from the galvanically isolating signal path.

The idea of the exemplary arrangement of fig. 5 is to make the filtering (or integrating) in blocks 503 and 504 independent of any attenuation and/or non- linear effects that may occur on the galvanically iso- lating signal path.

It suffices to get the PWM signal into the control input 505 of the switch 502 as a dig- ital, yes/no-type of signal.

The timing of the “yes’” and “nos”, i.e. the edges in the PWM signal, has sig- nificance, not the amplitude of the PWM pulses.

The regulated voltage obtained from the voltage source 501 ensures that the filtering (or integrating) in blocks 503 and 504 gives always a reliable result.

Fig. 6 illustrates a practical example of em- ploying some of the principles described above in a driver device.

Fig. 6 shows a part of the circuit dia- N gram of a driver device for semiconductor light N sources.

On the left, lines 601 may be coupled to the 3 30 power input or to a suitable location close to it, e like to the input side of a rectifier bridge that is Ek used to rectify the input voltage.

Resistors 602, 603, * 604, and 605 constitute a scaler that scales the volt- 3 age coming on lines 601 to a suitable level.

The diode S 35 package 606 implements half-wave rectification, and S the RC filter consisting of capacitor 607 and resistor 608 performs some interference rejection.

Circuit 609 is a voltage-to-PWM converter; circuits like this are readily available on the market as purpose-built packages. Its output drives the LED in the optoisolator 610.

On the secondary side a voltage regulator 611 may get its input voltage for example from a coil of the transformer in the galvanically isolated voltage converter, possibly through suitable rectification and filtering (not shown in fig. 6). The voltage regulator 611 produces a regulated supply voltage in the order of magnitude of some volts in its output, smoothened further by capacitor 612. A bias voltage to the col- lector of the phototransistor in the optoisolator 610 is taken from said regulated supply voltage through resistor 613. A scaled sample of the collector poten- tial of the phototransistor in the optoisolator 610 is taken to the base of a switch transistor 614 through the voltage divider consisting of resistors 615 and

616.

The switch transistor 614 corresponds to the switch that was earlier mentioned with reference to block 502 in fig. 5. The output voltage of the voltage regulator 611 comes to the collector of the switch transistor 614 through resistor 617. Thus, when the switch transistor 614 is non-conductive the potential at its collector is essentially equal to the output voltage of the voltage regulator 611, while when the x switch transistor 614 is conductive the potential at N its collector is essentially zero. This potential con- 3 30 stitutes the input to the first integrator 618 and e second integrator 619, which are simple R-C- Ek integrators with sufficient difference in their compo- * nent dimensioning to obtain the required difference 3 between their integration periods. Lines 620 can be S 35 used to couple the resulting amplitude indicator sig- S nal and frequency indicator signal to a processor (not shown in fig. ©).

Having two different indicator signals, one for amplitude and another for frequency, helps to keep the program executed by the processor simple. The pro- grammer may choose, at which rate the processor sam- ples the indicator signals in its inputs and how such sampling is interleaved with other operations that the processor may need to perform. How the processor (or other kind of control circuit) uses this information is not important for this description. As an example, the control circuit may be configured to derive de- tected (digital) values of the amplitude and freguency of the input voltage from the secondary information it gets from the PWM decoder means and to store the de- rived detected values into memory for some possible future use.

Variations and modifications can be made to the embodiments described above. As an example, while the description above has considered mostly two paral- lel decoder branches in which the amplitude indicator signal and said frequency indicator signal are pro- duced simultaneously, one possibility is to use a time-switched single decoder branch that toggles be- tween using longer and shorter integration times. By making the processor aware of the timing of such tog- gling, the processor can be arranged to derive the de- tected (digital) values of the amplitude and freguency of the input voltage in turns.

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Claims (16)

1. A driver device for semiconductor light sources, comprising: - a primary side, - a secondary side galvanically isolated from said primary side, - a power input (102) on said primary side for receiv- ing an input voltage that has an amplitude and a fre- quency, - a power output (103) on said secondary side for out- putting output power to said semiconductor light sources, - a galvanically isolated voltage converter (104, 105) coupled between said power input (102) and said power output (103), - a control circuit (106, 411) on said secondary side, - PWM encoder means (108, 401, 609) on said primary side, configured to encode primary information indica- tive of said amplitude into a PWM signal (403), - PWM decoder means (109, 303, 304, 407, 408, 503, 504) on said secondary side, and - a galvanically isolating signal path (110) for con- veying said PWM signal (403) from said PWM encoder means (108, 401, 609) to said PWM decoder means (109, 303, 304, 407, 408, 503, 504); characterized in that N - said PWM encoder means (108, 401, 609) are config- S ured to encode also primary information indicative of O said freguency into said PWM signal (403), and — 30 - said PWM encoder means (108, 401, 609) are config- > ured to decode said PWM signal (403) into secondary i information indicative of both said amplitude and said 3 frequency for use by said control circuit (106, 411).

S r r r r N 2. A driver device according to claim 1, N 35 wherein said PWM encoder means (108, 401, 609) are coupled to receive an input signal (402) indicative of said amplitude and frequency of said input voltage and configured to generate a PWM signal indicative of said input signal.

3. A driver device according to claim 2, wherein: - said PWM encoder means are coupled to receive a de- rived version of said input voltage (404) as said in- put signal (402), and - the driver device comprises at least one of the fol- lowing to produce said derived version: a filter, a rectifier, a scaler (405, 602, 603, 604, 605, 606, 607, 608).

4. A driver device according to any of claims 2 or 3, wherein said PWM encoder means (108, 401, 609) are configured to produce said PWM signal (403) at a PWM pulse frequency higher than 500 Hz.

5. A driver device according to claim 4, wherein said PWM encoder means (108, 401, 609) are configured to produce said PWM signal (403) at a PWM pulse frequency lower than 5 kHz.

6. A driver device according to any of the preceding claims, wherein the galvanically isolating signal path (110) comprises an optoisolator (610).

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7. A driver device according to any of the O 25 preceding claims, wherein: O - said PWM decoder means comprise a first decoder ? (303, 407, 503, 618) and a second decoder (304, 408, T 504, 619), z - said first decoder (303, 407, 503, 618) is config- © 30 ured to decode said PWM signal (403) into an amplitude x indicator signal (409), N - said second decoder (304, 408, 504, 619) is config- N ured to decode said PWM signal (403) into a frequency indicator signal (410), and

- said control circuit (106, 411) is coupled to re- ceive said amplitude indicator signal (409) and said frequency indicator signal (410).

8. A driver device according to claim 7, wherein: - said first decoder (303, 407, 503, 618) comprises a first integrator, configured to produce said amplitude indicator signal (409) by integrating said PWM signal (403) over a first integration period, - said second decoder (304, 408, 504, 619) comprises a second integrator, configured to produce said freguen- cy indicator signal (410) by integrating said PWM sig- nal (403) over a second integration period, and - said second integration period is shorter than said first integration period.

9. A driver device according to any of claims 7 or 8, wherein: - the driver device comprises a voltage source (501, 611) on said secondary side, - the driver device comprises a controllable switch (502, 614) coupled between said voltage source (501, 611) and each of said first and second decoders (503, 504, 618, 619), the controllable switch having a con- trol input (505), and - the control input (505) of said controllable switch — (502, 614) is coupled to receive the PWM signal (403) O from said galvanically isolating signal path (110).

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10. A driver device according to any of the —- preceding claims, wherein said control circuit (106, z 30 411) is configured to derive detected values of said N amplitude and said freguency from said secondary in- 3 formation and to store the derived detected values in- S to memory.

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11. A method for establishing information concerning an input voltage of a driver device for semiconductor light sources, the method comprising: - encoding (302) primary information indicative of an amplitude of said input voltage into a PWM signal, and - conveying said PWM signal through a galvanically isolating signal path (110) from a primary side to a secondary side of the driver device; characterized in that the method comprises: - encoding also information indicative of a frequency of said input voltage into said PWM signal, - decoding (303, 304) said PWM signal into secondary information indicative of both said amplitude and said frequency on said secondary side, and - using the secondary information for controlling the operation of the driver device.

12. A method according to claim 11, wherein producing said primary information comprises at least one of: filtering the input voltage, rectifying the input voltage, scaling the input voltage.

13. A method according to any of claims 11 or 12, wherein said PWM signal has a PWM pulse freguency higher than 500 Hz.

14. A method according to claim 13, wherein said PWM pulse frequency is lower than 5 kHz.

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15. A method according to any of claims 11 to S 14, wherein: — - said decoding of the PWM signal comprises producing > an amplitude indicator signal (409) and a frequency Ao a 30 indicator signal (410), 3 - said amplitude indicator signal is produced by inte- O grating (303, 407) said PWM signal over a first inte- O gration period, and - said freguency indicator signal is produced by inte-

grating (304, 408) said PWM signal over a second inte- gration period, which is shorter than said first inte- gration period.

16. A method according to claim 15, wherein said amplitude indicator signal (409) and said fre- quency indicator signal (410) are produced simultane- ously in parallel decoding branches.

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