EP4785052A1 - Improved radar system - Google Patents

Abstract

A Radio Frequency System-on-Chip, RFSoC, (12) for a radar system (10), the RFSoC (12) comprising a Programmable Logic, PL, module (30) and a Processing System, PS, module (32), operatively coupled to each other, the PS module (32) being configured to perform PS operations and the PL module (30) being configured to perform PL operations, the PL module (30) comprising at least: a Radio Frequency Data Converter, RFDC, module (36) configured to perform RFDC operations of said PL operations; a Digital Beam Forming, DBF, module (38) configured to perform DBF operations of said PL operations; and a Digital Pulse Compression, DPC, module (40) configured to perform DPC operations of said PL operations, the PS module (32) comprising at least: a Timing and Antenna Control, TAC, module (42) configured to perform TAC operations of said PS operations; a Signal Processor for Tactical Multi-Mission Radar, SPT, module (44) configured to perform SPT operations of said PS operations; a Message and Data Handler, MDH, module (46) configured to perform MDH operations of said PS operations; and an Enhanced Tracker, ETRK, module (48) configured to perform ETRK operations of said PS operations, and the RFSoC (12) being configured to receive a radar signal indicative of at least one target object (50) to be detected and to detect the at least one target object (50) by processing the radar signal through the PL module (30) and the PS module (32).

Description

IMPROVED RADAR SYSTEM

CROSS-REFERENCE TO RELATED APPLICATIONS

This Patent Application claims priority from European Patent Application No. 23200092.7 filed on September 27, 2023, and Italian Patent Application No. 102024000001542 filed on January 26, 2024 the entire disclosure of which is incorporated herein by reference.

TECHNICAL FIELD

The present invention concerns an improved radar (“radio detection and ranging”) system, in particular it concerns a Radio Frequency System-on-Chip (RFSoC), a radar system comprising the RFSoC and a method for detecting a target object through the RFSoC. The present invention finds its preferred, although not exclusive, application in the aerospace field.

BACKGROUND OF THE INVENTION

As known, radar systems are used to acquire a radar signal indicative of the position of an object to be detected and to process this radar signal in order to obtain information about this target object, such as its position, trajectory and speed.

Currently, radar systems are implemented as complex solutions comprising several boards with components used to perform the abovementioned activities. This results in a complex and cumbersome system that is prone to malfunctioning, for example due to heating of the components and breaking of the boards.

Therefore, the need is felt to provide a solution that overcomes the abovementioned issues and in particular that is small-sized and reliable.

SUMMARY OF THE INVENTION

An aim of the present invention is to satisfy the above-mentioned needs.

The aforementioned aim is reached by a Radio Frequency System-on-Chip (RFSoC), a radar system comprising the RFSoC and a method for detecting a target object through the RFSoC, as claimed in the appended set of claims.

BRIEF DESCRIPTION OF DRAWINGS

For a better understanding of the present invention, a preferred embodiment is described in the following, by way of a non-limiting example, with reference to the attached drawings wherein: • Figure 1 is a block diagram schematically showing a radar system, according to an embodiment of the present invention;

• Figures 2 and 3 are respective block diagrams schematically showing a Radio Frequency System-on-Chip (RFSoC) of the radar system of Figure 1, according to an embodiment of the present invention;

• Figure 4 is a block diagram schematically showing details of a Programmable Logic (PL) module of the RFSoC of Figures 2 and 3, according to an embodiment of the present invention;

• Figures 5-8 are respective block diagrams schematically showing respective details of a Processing System (PS) module of the RFSoC of Figures 2 and 3, according to an embodiment of the present invention; and

• Figure 9 shows the radar system of Figure 1 comprising the RFSoC of Figures 2 and 3, used to detect a target object.

DETAILED DESCRIPTION OF THE INVENTION

Figure 1 shows a radar system 10, according to an embodiment of the present invention.

The radar system 10 comprises a System-On-a-Chip (SoC) 12, in particular a Radio Frequency System-on-Chip (RFSoC) 12, configured to receive a radar signal indicative of the position of an object to be detected (external to the radar system 10 and, in the following, also called target object) and to process this radar signal in order to obtain information about the classification and kinematics of the target object, such as its position, trajectory and speed.

In general, the System-On-a-Chip (SoC) is a microchip that includes all the electronic circuits necessary to perform all the actions required for a specific application.

For example, the Radio Frequency System-on-Chip (RFSoC) is a known technology that implements a sensor processing chain for radio frequency applications by means of components allocated on a single chip. This allows to reduce the dimension of the system required to perform the desired actions and to increase its reliability.

Generally, the RFSoC is used in high-tech systems such as in the automotive field or in the telecommunication field, to implement communications at radio frequency. On the other hand, here the RFSoC 12 has been adapted to be used for radar applications. The RFSoC 12 is better described in the following, with reference to Figure 2.

The radar system 10 may also comprise a sensor module 14 coupled to the RFSoC 12, for example through an interface module 16 of the radar system 10.

The sensor module 14 comprises one or more sensors used to detect the target object.

In particular, the sensor module 14 comprises one or more radar antennae 18 configured to detect the target object according to per se known techniques in the radar field.

For example, Figure 1 shows the exemplary case of one radar antenna 18 generating the radar signal. However, more radar antennae 18 may be analogously considered and, in this case, a correspondent plurality of radar signals may be generated.

Moreover, the sensor module 14 may comprise additional sensors (not shown) configured to acquire data used by the RFSoC 12 to perform its activities. For example, the sensor module 14 may comprise a temperature sensor and an inertial measurement unit, IMU.

In the considered embodiment, the sensor module 14 is configured to generate as an output the radar signal, based on the detection of the target object carried out by the radar antenna 18. The radar signal is an electric signal indicative of the radar measurement of the target object, i.e. is correlated to radar information of the target object such as its position, trajectory and speed.

Optionally, the sensor module 14 is configured to generate further signals that can be used by the RFSoC 12 to perform its activities. For example, the sensor module 14 may be configured to generate a temperature signal indicative of the temperature of the components of the RFSoC 12, acquired by the temperature sensor and used to take precautions and countermeasures in case of high temperatures to avoid damaging the RFSoC 12.

The RFSoC 12 is configured to receive the radar signal outputted by the sensor module 14, for example after the radar signal has been pre-processed by means of the interface module 16.

In particular, the interface module 16 is operatively interposed between the RFSoC 12 and the sensor module 14 and can comprise interface components configured to interface the sensor module 14 with the interface module 16. In details, the interface module 16 may comprise a RTX adapter (not shown) of per se known type, configured to interface the radar antenna 18 with the RFSoC 12.

For example, the RTX adapter comprises filters, amplifiers and circulators necessary for RF performance and configured to pre-process the radar signal (e.g., to filter it, to amplify it, etc.).

The connections between the RFSoC 12 and the other components of the radar system 10 are made by using electrical connectors configured to carry power supplies and control signals.

Figure 2 and 3 show in details the RFSoC 12.

The RFSoC 12 comprises a Programmable Logic (PL) module (or section) 30 and a Processing System (PS) module (or section) 32, operatively (in particular electrically) coupled to each other by means of a bus of the RFSoC 12 (shown for example in Figure 3 with the reference number 34, for example a high data rate Advanced extensible Interface, AXI, bus).

In details, the RFSoC 12 comprises an electronic board (not shown, such as a printed circuit board, PCB) on which the PL module 30 and the PS module 32 are mounted. Therefore, the PL module 30 and the PS module 32 are fixed to the electronic board, thus forming an integral body and a respective monolithic assembly.

In particular, the electronic board can comprise a coldplate based on the heatpipe technology, to allow passive dissipation through the edgelocks of the heat generated by the components of the RFSoC 12.

In particular, the PL module 30 integrates a front end of the RF signal chain and comprises the set of firmware blocks for implementing the receiving and transmitting chain, whereas the PS module 32 integrates a software processing chain for performing signal analysis based on the specific application.

In order to better understand the differences between the software of the PS module 32 and the firmware of the PL module 30, the physical differences between the PL and PS modules 30, 32 can be discussed.

In the PS module 32 there are processors that have a fixed architecture and that may require RAM, ROM and peripherals. Processors are usually programmable, i.e. the code to be executed is stored in the form of instructions and data in a memory and the instructions are executed sequentially. A processor needs a central processing unit (CPU, i.e. an ALU and a control), RAM, Input, Output and Bus memory units.

In the PL module 30 there are FPGAs (Field Programmable Gate Arrays) made up of numerous blocks and cells that can be connected to each other via configurable connections. In practice, the FPGAs are a programmable integrated circuits in the sense that it is possible to program how to connect the various cells and the various blocks to each other. These logical units connected to each other can also perform very complex functions, making the FPGA highly flexible and with a reprogrammable or rather reconfigurable architecture with a high-level descriptive language that describes how to connect the various cells to each other.

FPGAs also have significant differences in performance compared to processors. Thanks to the high parallelism of the circuits made with connections programmed inside the FPGA, they excel at handling large-scale parallel data processing and high-speed signal processing. For example, they are widely used in fields such as real-time video processing, digital signal processing and high-speed communications.

Processors, on the other hand, perform better on tasks that are difficult to parallelize, such as controlling simple devices, performing basic logic operations and processing sensor data.

FPGAs, due to their parallel processing capacity and complex circuit architecture, generally consume more energy and have low latencies with respect to processors; however, they have greater calculation speed due to the high parallelism achievable by exploiting their hardware features. Since processors have a fixed architecture that performs logical operations in sequence, they generally consume less energy but have generally higher execution times.

FPGAs and processors are also programmed with two different types of languages.

In detail, FPGAs are programmed with hardware description languages (e.g., VHDL or Verilog), with more complex simulation and debugging features leading to longer development cycles with higher development costs. However, the flexibility and high performances of the FPGAs make them useful in high-end applications. In the following, this type of programming is also called firmware.

On the other hand, processor programming requires coding with high-level programming languages, such as C/C++, and the lack of knowledge of the hardware on which it is executed. In the following, this type of programming is also called software.

FPGAs, having no operating system and guaranteeing the programmer direct control of the hardware, are less susceptible to errors and malicious attacks than a processor, thus guaranteeing greater system security.

Moreover, FPGAs are provided with several programmable logic blocks and interconnect frameworks that can be reconfigured for rewiring. Logic gates can be interconnected using different configurations, which allows them to be wired together differently. It is thus possible to perform complex combined functions by configuring logic blocks and safe logic gates such as XOR and AND. FPGA programming is the process of configuring or reconfiguring the IC using hardware description languages such as VHDL and Verilog. Through programming, FPGAs can perform specific functions by connecting logic blocks and interconnects. FPGAs can thus process commands simultaneously and can execute numerous lines of code at any given time.

On the other hand, the processors use a software program to execute consecutive commands, using a high-level programming language and processing power tied to the processors’ clock speed. The processors read each line of the program sequentially, thus the commands are also processed sequentially.

Therefore, the choice between FPGA and processor generally depends on the performance requirements of the specific application. This is the reason for having the PS module 32 with processors and the PL module 30 with FPGAs.

In other words, in view of the above it is evident that here firmware is what is developed in the PL section using HW description language such as VHDL, whereas software is what runs in PS and developed with high-level programming languages such as C/C++.

In further details, the cooperation of the PL module 30 and the PS module 32 is ensured by the exchange of data through shared memories between the two components. Through the use of the AXI Bus 34, the processors allocated in the PS module 32 share with the firmware allocated in the PL module 30 an internal data area that is made accessible for this application. The exchange of information in this area of the PL module 30 creates an internal interface between the PL module 30 and the PS module 32.

According to an exemplary embodiment, the architecture and structure of the RFSoC 12 correspond to the ones of the system currently produced by Xilinx (https://www.xilinx.com/products/silicon-devices/soc/rfsoc.html), that integrates the front end of the RF signal chain on a SoC (System on Chip). This known system combines analog data converters and/or SD-FEC cores with high performance programmable logic and the ARM multi-processing system, to create a comprehensive analog-to-digital signal processing chain on a single monolithic device. In the present case, the functionalities of this known hardware architecture have been designed and adapted for the present radar application, as better described in the following.

As per se known, the RFSoC 12 may comprise elements (not shown) such as ADCs (“Analog to Digital Converters”, e.g., 8), DACs (“Digital to Analog Converters”, e.g., 8), UART interface, ETH1G interface, PCIE GEN2 interface, DDR controller etc.

Moreover, the RFSoC 12 can comprise a memory module (not shown) configured to store data required for the functioning of the RFSoC 12. For example, the memory module comprises one or more memory units, such as a QSPI flash memory (e.g., a 2Gbit one), a EEPROM data memory (e.g., a 1Mbit one), one or more DDR4 memories (e.g., of 512 Mbytes 64 bit type), an SD/EEMC memory.

For example, the PL module 30 can comprise a Field Programmable Gate Array (FPGA) with 4272 DSP, about 900.000 system logic cells and 38.0 Mb BRAM, one or more ADCs with 5.2 Gsps band (e.g., 8) and one or more DACs with 14 bit (e.g., 8), whereas the PS module 32 can comprise a 64-bit quad-core ARM Cortex- A53 processor and a dual-core ARM Cortex-R5 processor.

The PL module 30 comprises firmware modules for the transmitting and receiving chain (in details, for waveform synthesis), while the PS module 32 comprises the software processing chain that deals with timing management, bite, signal processing, target extraction, target tracking and classification. The functional allocation between the PS module 32 and the PL module 30 is based on real time requirements.

In general, the PL module 30 is configured to implement faster and more critical operations (e.g.: range counter of operative timing; transfer in DMA, “Direct Memory Acces”, to DAC; transfer in DMA from ADC (in particular and considering the presence of several ADCs, transfer in multiple-channel DMA from the ADCs); messages to be sent to the ARTEMIS modules; status and bite definition; calibration; Test TarGet, TTG; tap point for debug; programming of the LMK (Linear Monolithic K, for a new clocking group) and LMX (Linear Monolithic X, for clock and timing) modules of the PLLs, whereas the PS module 32 is configured to implement slower and less critical operations (e.g.: initialization management; configuration; logging; debug; asynchronous external requests, for example from config, file, lan, etc.; signal and data processing without special latency requirements). In other words, the PL module 30 is configured to perform operations (in details firmware operations, also called PL operations or second operations) that are faster and have a higher safety degree with respect to the operations (in details software operations, also called PS operations or first operations) of the PS module 32, i.e. the PL operations are faster to be executed (i.e., have lower latencies) and have a higher confidence of correct processing (in fact, the correctness of the operation result depends on the chosen hardware rather than on the implemented program instructions, thus resulting in being more reliable and more difficult to be altered by third parties) with respect to the PS operations.

In details, the operations carried out by the PL module 30 are at least the following: Radio Frequency Data Converter (RFDC) operations; Digital Beam Forming (DBF) operations; and Digital Pulse Compression (DPC) operations. Moreover, the operations carried out by the PS module 32 are at least the following: Timing and Antenna Control (TAC) operations (to define the scheduling of the radar activities and the bite information of the radar antenna 18); Signal Processor for TMMR (SPT) operations (for signal processing and target extraction), where TMMR is a Tactical MultiMission Radar; Message and Data Handler (MDH) operations (to interface with external actors); and Enhanced Tracker (ETRK) operations (for target tracking).

As evident, the PL module 30 and the PS module 32 can also be configured to perform other operations, here not discussed in detail because not relevant for the present invention.

In particular, the PL module 30 comprises a Radio Frequency Data Converter (RFDC) module configured to perform the RFDC operations and shown in Figure 4 with the reference number 36, a DBF module configured to perform the DBF operations and shown in Figure 4 with the reference number 38 and a DPC module configured to perform the DPC operations and shown in Figure 4 with the reference number 40. Moreover, the PS module 32 comprises a TAC module configured to perform the TAC operations and shown in Figure 5 with the reference number 42, an SPT module configured to perform the SPT operations (i.e., operations of Signal Processing) and shown in Figure 6 with the reference number 44, a MDH module configured to perform the MDH operations and shown in Figure 7 with the reference number 46 and a ETRK module configured to perform the ERTK operations and shown in Figure 8 with the reference number 48.

The RFDC operations can comprise processing and sampling the radar signal received from the radar antenna 18, for example by means of the ADCs and through per se known RF sampling techniques. For example, in case of a plurality of radar antennae 18, each ADC of the PL module 30 can be configured to receive the radar signal coming from a respective radar antenna 18 of these radar antennae 18, and to process it according to a respective acquisition channel.

In further detail, the RFDC module 36 can comprise an IP core that integrates the components for sampling data directly with functions that manage RF sampling (i.e., through ADC and DAC). The RFDC module 36 can be partly configured statically by the firmware (e.g., via ADC and DAC configurations) and partly configured by the software using software drivers (e.g., via a numerically controlled oscillator, NCO). For example, it can have 8 DACs, 8 ADCs, a MTS (Multi Tile Synchronization) function to phase align the signals acquired from the various channels, multiple AXI4-Stream data interfaces to take data from ADCs and DACs and transfer them via a bus, interpolation functions, decimation functions, inter-channel mixing functions, NCOs and quadrature modulation correction (QMC) functions. For example, the RFDC module 36 can be used to set both the input and the output signals for the decimation, the filter, the MTS for the channel synchronization, the NCO to set the frequency of the oscillators.

In the following, the RFDC module 36 can also be called Radio Frequency Data Sampler (RFDS).

The DBF operations can comprise performing digital beam forming based on the sampled radar signal, through per se known techniques of beam forming. For example, the radar signal processed by the ADC (analogously for the case of a plurality of radar antennae 18, the radar signals processed by the respective ADCs) is elaborated to generate DBF features, such as SUM, DELTA EL (DEL), DELTA AZ (DAZ), SLB.

The DPC operations can comprise processing the DBF features through per se known DPC techniques, to generate compressed data.

Further details of an exemplary embodiment of the PL module 30 are shown in Figure 4. Concerning the PS module 32, the TAC operations can comprise controlling the timing of the radar antenna 18, to schedule its functions and thus the radar activity. Moreover, the TAC operations can comprise controlling the timing of the components of the RFSoC 12, and in particular of the PS module 32, according to per se known techniques. In other words, the TAC operations can comprise generating one or more timing signals for controlling the RFSoC 12 and, more in general, the radar system 10.

For example, the TAC operations can be partially performed on the ARM Cortex- A53 processor and the ARM Cortex-R5 processor. In particular, the ARM Cortex-A53 processor can manage the initializations, configurations and asynchronous external requests, while the ARM Cortex-R5 processor can drive the firmware blocks of the PL module 30, for example to schedule the receipt of the radar signal. This is exemplarily shown in Figure 5.

The SPT operations can comprise processing the information received from the PL module 30 (i.e., the compressed data) to generate detection data indicative of data of the target object (e.g., in terms of distance range, doppler frequency shift of the target echo signal with respect to the radio signal emitted by the radar antenna 18, signal-to- noise ratio, etc.) extracted from the radar signal, according to per se known techniques.

Details of an exemplary embodiment of the processing chain of the SPT module 44 are shown in Figure 6.

In particular, the processing chain of the SPT module 44 comprises four main processing stages defining the SPT operations: signal integration; clutter elaboration; Constant False Alarm Rate (CFAR); and detection.

The signal integration can comprise performing transposition of the compressed data received from the DPC module 40 and then performing Moving Target Detector (MTD) operations, i.e. Chebychev Filtering and Fast Fourier Transforms (FFT), in order to calculate a Range/Doppler Matrix based on the input compressed data, according to per se known techniques.

The clutter elaboration and CFAR can comprise performing noise estimation, clutter detection, alpha calculation and CFAR threshold calculation, according to per se known techniques.

The detection can comprise performing detections extraction, monopulse ratio calculation, range/doppler interpolation and typing, according to per se known techniques.

In further details, the SPT operations can be executed on three out of the four cores of the ARM Cortex-A53 processor of the PS module 32. On each core, a respective elaboration thread (i.e., SPT_x in Figure 6, wherein x=0,l,2 is an index corresponding to the considered core) is executed in order to process the entire functional chain for a given burst in parallel. For example, each core: receives the compressed data outputted by the DPC module 40 (indicative of the compressed DBF features) from the FPGA module (e.g., at 9.216 Msps, i.e. 590 Mbit/s); processes them through the target elaboration chains, obtaining synthetic information on detections (such as range, monopulse ratios, doppler, SNR, ecc.); and sends detection data to the MDH module 46, for example encapsulated in UDP (“User Datagram Protocol”) packets.

For example, these operations may also be performed through a NEON math coprocessor of the PS module 32, which is a technology that can assist the ARM Cortex- A53 processor by using a separate instruction set, independent registers and separate code execution, thus allowing to free up CPU and to manage up to 16 operations simultaneously.

Moreover, between the FPGA of the PL module 30 and the elaboration threads of the PS module 32 there can be a separate component that receives data from the FPGA and makes the pointer to the data available for the first free elaboration thread SPT_x. This component can be implemented as a dispatcher thread, for example running on CORE 0 of the ARM Cortex-A53 processor. The communication between the FPGA and the dispatcher thread is based on a custom driver that is configured to: manage the hardware interrupt coming from the FPGA, which notifies for new data presence in the DDR4 memory of the PL module 30; after the interrupt, configure the DMA for sending source data from the DDR4 memory of the PL module 30 to the destination data address (e.g., the RAM of the ARM Cortex-A53 processor).

The MDH operations can comprise acquiring the detection data (indicative of the target information and generated by the SPT module 44) and then calculating the position of the target object, if present, based on the detection data.

Details of an exemplary embodiment of the MDH module 46 are shown in Figure 7.

In particular, the MDH module 46 comprises a Plot Extractor (PEX) 46a and a Message Handler (MH) 46b. The PEX 46a is configured to receive the detection data generated by the SPT module 44 and to extract the radar plots to be sent to the ETRK module 48, that are indicative of the position of the target object, whereas the MH 46b is configured to implement a state machine to manage the information sharing with other components of the radar system 10 (e.g., the representation and visualization of information by actors external to the PS module 32).

For example, the MDH operations are implemented on one of the four cores of the ARM Cortex- A53 processor of the PS module 32 (e.g., the one that is not used for the SPT operations).

The ETRK operations can comprise acquiring the position of the target object from the MDH module 46 through the generated radar plots and then tracking the target object based on said information, in order for example to analyse its features (e.g., its trajectory) and to classify it (e.g., which kind of object it is, which is its motion status, etc.). In other words, the ETRK module 48 associates between them consecutive radar observations of the same target object that is being tracked, in order to analyse the features of the target object according to per se known techniques.

Details of an exemplary embodiment of the ETRK module 48 are shown in Figure 8.

In particular, the ETRK module 48 is configured to implement an Interactive Multi Model (IMM) filter comprising several Kalman filters that run in parallel, each of them using a different model to target the motion detection and error determination of the target object. The IMM calculates an optimal weighted sum of the output of all the filters and is able to rapidly adapt to manoeuvres of the target object. This allows to implement the classification of the target object, in a per se known way. In other words, the IMM processes the information about the position of the target object to perform the tracking of the target object.

For example, the ETRK operations can be executed on one out of the four cores of the ARM Cortex- A53 processor of the PS module 32 when the radar system 10 is in a single face configuration, whereas the ETRK operations can be executed simultaneously on several cores of the ARM Cortex-A53 processor of the PS module 32 when the radar system 10 is in a multiple faces configuration, in order to better exploit the power computation of the PS module 32. During use, the RFSoC 12 implements a method for detecting the target object.

In particular, the method comprises: receiving, by the RFSoC 12, the radar signal indicative of the target object to be detected; and detecting the target object through processing of the radar signal by performing the software operations by means of the PS module 32 and the firmware operations by means of the PL module 30, wherein the firmware operations are faster and have a higher safety degree with respect to the software operations. The step of performing the firmware operations comprises at least: performing RFDC operations by means of the RFDC module 36; performing DBF operations by means of the DBF module 38; and performing DPC operations by means of the DPC module 40. The step of performing the software operations comprises at least: performing TAC operations by means of the TAC module 42; performing SPT operations by means of the SPT module 44; performing MDH operations by means of the MDH module 46; and performing ETRK operations by means of the ETRK module 48.

In view of the foregoing, the advantages of the Radio Frequency System-on-Chip, the radar system and the method for detecting the target object, according to the invention, are apparent.

The radar system 10, and in particular the RFSoC 12, is an innovative solution that can be used for all applications that require low-cost, easily deployable and transportable radars. It features simplified architecture and low cost of the product, since the computation is performed on a single board (i.e., the RFSoC 12). This allows to sample directly the signals at radio frequency and to obtain as an output the radar tracks, all through the use of a single chip.

It is also a sustainable solution featuring relevant reduction of power and of footprint.

The RFSoC 12 is based on a new and integrated firmware/software design for efficient implementation of applications.

In details, the innovative aspects are: the use of the RFSoC technology in the radar field, which allows to sample directly in radio frequency; a comprehensive analog-to- digital signal processing chain on a single monolithic device; low energy dissipation, allowing for a simple cooling system; the use of a very compact and light solution, allowing for a simple installation, deployment, configuration and portability.

The radar system 10 can be applied to C-band radars, but the present approach could also be used for other types of sensors.

In details, Figure 9 shows the use of the radar system 10 to detect the target object, here indicated with the reference number 50.

For example, the radar system 10 could be used as a Tactical Multi Mission Radar (TMMR). The TMMR provides advanced force and border protection through the detection, classification and tracking of air and surface intruders. It is a C-Band full AESA (Active Electronic Scanned Array) Radar designed as an extremely compact all-in-one and lightweight solution for battlefield applications. It can be easily integrated in any C4I system by using its standard Ethernet interfaces, to contribute to the tactical picture of a large-scale surveillance system as well as to cue a defensive weapon. Missions of the TMMR can be: C-UAS (Unmanned Aerial Systems); comprehensive border surveillance; force protection and battlefield surveillance; vehicles protection; gap filler for V- SHORAD (Very SHOrt Range Air Defence) applications; and land patrolling. The TMMR sensor can be deployed in a single face configuration for border protection scope or in multi faces configuration with four cooperating panels, e.g. for point defence mission.

The radar system 10 satisfies the SWAP (Size, Weight and Power) requirements. In details, it provides the following benefits: compact and light structure; low power dissipation (e.g., the monolithic integration of the ADCs and the DACs on the SoC eliminates the need for external data converters, thus allowing a reduction of up to 50% power and footprint compared to a known multicomponent solution); flexibility (the heterogeneous computing architecture formed by converters, FPGA and microprocessors, offers complete analog/digital programmability and extreme flexibility); maintainability and testability (much of the RF signal processing has moved into the digital domain and this makes testing, debugging and maintainability easier).

The radar system 10 is based on a heterogeneous processing system with 64-bit ARM Cortex-A53 processor, 32-bit ARM Cortex-R5 and Gate Array programmable logic.

The 32-bit Cortex-R5 processor has very modest performance (it has less memory, lower processing frequency and 32-bit architecture). It is suitable for tasks that require reliability, high availability, fault tolerance, maintainability and real-time response. Thus it can be used to start the applications that run on the A53 processor and, since it has high reliability features, it is typically used for monitoring operations of the correct functioning of the applications and, in case of malfunctions, it is able to stop and restart them on the A53 processor.

A normal software application can be carried out using the Cortex- A53 processor which has the performances of a high-performance processor suitable for running applications that have high processing requirements on advanced operating systems (such as Linux).

Therefore, the radar system 10 implements a new architecture where, at the end of the boot phase of the Linux operating system, the application processes that run on A53 are started. The TAC process running on the A53 processor instead starts a process on the R5 processor (contrary to what is usually done in the state of the art), so that the two processes run on different processors, are synchronized and communicate with each other with standard communication mechanisms (e.g., interrupt and shared memory). The two processors can use different operating systems (e.g., Linux and FreeRTOS) and can both interact with the PL module 30 via a communication bus. This architecture allows to run only the critical functions on the R5 processor with Real Time features and high reliability and to run the other numerous and less critical functions on the A53 processor which has high processing features on an advanced and versatile operating system (in the present case, Linux).

Therefore, the radar system 10 allows to implement on a single chip (with low dissipation and low consumption) a RADAR chain complete with transmitter and receiver with functions ranging from digital beam forming to target tracking and timing generation. With the radar system 10, high target detection performances with low RCS (Radar Cross Section) up to 40 Km can be obtained.

It is clear that modifications can be made to the described solution, which do not extend beyond the scope of protection defined by the claims.

For example, even though it has been previously described that the radar system 10 can be used to detect a target object (e.g., a flying or land vehicle/drone), it is evident that it can also be used to simultaneously detect a plurality of target objects.

Claims

1. A Radio Frequency System-on-Chip, RFSoC, (12) for a radar system (10), the RFSoC (12) comprising a Programmable Logic, PL, module (30) and a Processing System, PS, module (32), operatively coupled to each other, the PS module (32) being configured to perform PS operations and the PL module (30) being configured to perform PL operations, the PL module (30) comprising at least: a Radio Frequency Data Converter, RFDC, module (36) configured to perform RFDC operations of said PL operations; a Digital Beam Forming, DBF, module (38) configured to perform DBF operations of said PL operations; and a Digital Pulse Compression, DPC, module (40) configured to perform DPC operations of said PL operations, the PS module (32) comprising at least: a Timing and Antenna Control, TAC, module (42) configured to perform TAC operations of said PS operations; a Signal Processor for Tactical Multi-Mission Radar, SPT, module (44) configured to perform SPT operations of said PS operations; a Message and Data Handler, MDH, module (46) configured to perform MDH operations of said PS operations; and an Enhanced Tracker, ETRK, module (48) configured to perform ETRK operations of said PS operations, and the RFSoC (12) being configured to receive a radar signal indicative of at least one target object (50) to be detected and to detect the at least one target object (50) by processing the radar signal through the PL module (30) and the PS module (32).

2. The RFSoC (12) according to claim 1, wherein the RFDC module (36) is configured to, when performing the RFDC operations, perform radio frequency sampling on the radar signal, wherein the DBF module (38) is configured to, when performing the DBF operations, generate DBF features by performing digital beam forming based on the radar signal processed by the RFDC module (36), wherein the DPC module (40) is configured to, when performing the DPC operations, generate compressed data by processing the DBF features through DPC techniques, wherein the TAC module (42) is configured to, when performing the TAC operations, generate one or more timing signals for controlling the RFSoC (12), wherein the SPT module (44) is configured to, when performing the SPT operations, generate, based on the compressed data, detection data correlated to radar plots indicative of radar information of the at least one target object (50), wherein the MDH module (46) is configured to, when performing the MDH operations, calculating a position of the at least one target object (50) based on the detection data, wherein the ETRK module (48) is configured to, when performing the ETRK operations, track the at least one target object (50) based on the calculated position.

3. The RFSoC (12) according to claim 2, wherein the SPT module (44) is configured to, for generating the detection data, performing: signal integration; clutter elaboration; Constant False Alarm Rate, CFAR; and detection, wherein the SPT module (44) is configured to, for performing signal integration, perform transposition of the compressed data and then perform Moving Target Detector, MTD, operations, comprising performing Chebychev Filtering and Fast Fourier Transforms, in order to calculate a Range/Doppler Matrix, wherein the SPT module (44) is configured to, for performing clutter elaboration and CFAR, perform noise estimation, clutter detection, alpha calculation and CFAR threshold calculation, and wherein the SPT module (44) is configured to, for performing detection, performing detection extraction, monopulse ratio calculation, range/doppler interpolation and typing to obtain the detection data.

4. The RFSoC (12) according to claim 2 or 3, wherein the MDH module (46) comprises a Plot Extractor, PEX, (46a) and a Message Handler, MH, (46b), wherein the PEX (46a) is configured to receive the detection data and to determine said radar plots, and wherein the MH (46b) is configured to manage the sharing of information correlated to the radar plots.

5. The RFSoC (12) according to anyone of claims 2-4, wherein the ETRK module (48) is configured to, for tracking the at least one target object (50), implement an Interactive Multi Model, IMM, filter.

6. The RFSoC (12) according to anyone of the previous claims, wherein the PL module (30) comprises a Field Programmable Gate Array, FPGA, and the PS module (32) comprises an ARM Cortex-A53 processor with four cores and an ARM Cortex-R5 processor with two cores, wherein the TAC module (42) is configured to perform the TAC operations partially on the ARM Cortex- A53 processor and partially on the ARM Cortex-R5 processor, wherein the SPT module (44) is configured to perform the SPT operations on three out of the four cores of the ARM Cortex-A53 processor, wherein the MDH module (46) is configured to perform the MDH operations on one of the four cores of the ARM Cortex- A53 processor, and wherein the ETRK module (48) is configured to perform the ETRK operations on one or more of the four cores of the ARM Cortex- A53 processor.

7. The RFSoC (12) according to anyone of the previous claims, further comprising a bus, in particular an AXI bus, electrically connecting the PL module (30) and the PS module (32).

8. The RFSoC (12) according to anyone of the previous claims, further comprising an electronic board on which the PL module (30) and the PS module (32) are mounted, the electronic board comprising a coldplate configured to dissipate heat produced by the PL module (30) and the PS module (32).

9. A radar system (10) comprising a Radio Frequency System-on-Chip, RFSoC, (12), according to anyone of the previous claims, and at least one radar antenna (18) that is operatively coupled to the RFSoC (12) and is configured to generate said radar signal.

10. A method for detecting at least one target object (50), implemented through a Radio Frequency System-on-Chip, RFSoC, (12) for a radar system (10), the RFSoC (12) comprising a Programmable Logic, PL, module (30) and a Processing System, PS, module (32), operatively coupled to each other, the PL module (30) comprising at least: a Radio Frequency Data Converter, RFDC, module (36); a Digital Beam Forming, DBF, module (38); and a Digital Pulse Compression, DPC, module (40), the PS module (32) comprising at least: a Timing and Antenna Control, TAC, module (42); a Signal Processor for Tactical Multi-Mission Radar, SPT, module (44); a Message and Data Handler, MDH, module (46); and an Enhanced Tracker, ETRK, module (48), the method comprising: receiving, by the RFSoC (12), a radar signal indicative of at least one target object (50) to be detected; and detecting the at least one target object (50) through processing of the radar signal by performing PS operations by means of the PS module (32) and PL operations by means of the PL module (30), wherein performing PL operations comprises at least: performing RFDC operations by means of the RFDC module (36); performing DBF operations by means of the DBF module (38); and performing DPC operations by means of the DPC module (40), and wherein performing PS operations comprises at least: performing TAC operations by means of the TAC module (42); performing SPT operations by means of the SPT module (44); performing MDH operations by means of the MDH module (46); and performing ETRK operations by means of the ETRK module (48).