EP4732436A1 - Temperature sensing in a radio frequency (rf) device array - Google Patents

Abstract

Temperature sensing in a radio frequency (RF) device array is disclosed. In particular, an RF device array may include a plurality of closely arranged devices where a temperature gradient may exist between devices due to the geometry of the device. Aspects of the present disclosure compare measure a temperature-induced voltage difference between devices while subtracting out a common RF power component and using this difference signal as a proxy for a direct measure of instantaneous temperature. Based on this direct measurement, compensation for such temperature change may be provided (e.g., correcting for thermal droop).

Description

TEMPERATURE SENSING IN A RADIO FREQUENCY (RE) DEVICE ARRAY

Related Application

[0001] This application claims the benefit of U.S. provisional patent application serial number 63/522,739, filed on June 23, 2023, the disclosure of which is hereby incorporated herein by reference in its entirety.

BACKGROUND

I. Field of the Disclosure

[0002] The technology of the disclosure relates generally to techniques to sense temperature in radio frequency (RF) devices such as power amplifiers.

IL Background

[0003] Computing devices abound in modern society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences. With the advent of the myriad functions available to such devices, there has been increased pressure to find ways to increase the bandwidth available for wireless communication. This pressure has resulted in ever-faster wireless standards, which impose new requirements on radio frequency (RF) devices (e.g., power amplifiers) associated with wireless transceivers. One such requirement is rapid switching and rapid power pulses, which in turn create waste heat. Such waste heat may negatively impact the performance of the RF devices. Compensating for the thermally induced performance variation provides room for innovation.

SUMMARY

[0004] Aspects disclosed in the detailed description include systems and methods of temperature sensing in a radio frequency (RF) device array. In particular, an RF device array may include a plurality of closely arranged devices where a temperature gradient may exist between devices due to the geometry of the device. Aspects of the present disclosure compare a temperature-induced voltage difference between devices while subtracting out a common RF power component and using this difference signal as a proxy for a direct measure of instantaneous temperature. Based on this direct measurement, compensation for such temperature change may be provided (e.g., correcting for thermal droop).

[0005] In this regard, in one aspect, an array is disclosed. The array includes a plurality of devices physically proximate to one another such that waste heat generated during operation heats different ones of the plurality of devices to different degrees, each of the plurality of devices comprising at least one tap from which a junction voltage may be determined. The array further includes an extraction circuit coupled to the at least one tap on two devices of the plurality of devices and configured to generate a thermal droop control signal based on a difference in the junction voltage of the two devices.

[0006] In another aspect, a radio frequency (RF) power amplifier is disclosed. The RF power amplifier includes a plurality of RF devices physically proximate to one another and arranged such that waste heat forms a heat gradient across the plurality of RF devices, wherein the plurality of RF devices comprises a first RF device and a second RF device. The first RF device of the RF power amplifier includes a first transistor and at least one first tap from which a first junction voltage may be determined, and the second RF device of the RF power amplifier includes a second transistor and at least one second tap from which a second junction voltage may be determined. The RF power amplifier further includes an extraction circuit configured to receive the first junction voltage and the second junction voltage and generate a thermal droop compensation signal based on the first junction voltage and the second junction voltage.

[0007] In another aspect, a method of compensating for thermal droop is disclosed. The method includes measuring a first junction voltage for a first device and measuring a second junction voltage for a second device. The method also includes generating a thermal droop signal from the first junction voltage and the second junction voltage and adjusting behavior of a precursor circuit based on the thermal droop signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a block diagram of an exemplary array of radio frequency (RF) devices disposed in close proximity;

[0009] Figure IB shows how a heat gradient may be created in the array of Figure 1 A during operation;

[0010] Figure 2 is a circuit diagram of the array of Figure 1 A implemented in a bipolar technology with taps shown from which junction voltages may be determined for individual ones of the RF devices in the array;

[0011] Figure 3 is a circuit diagram of a differential amplifier which may be used with the taps from Figure 2 to generate a thermal droop compensation signal;

[0012] Figure 4 is a circuit diagram of the array of Figure 1 A implemented in a dual field effect transistor (FET) technology with taps shown from which junction voltages may be determined for individual ones of the RF devices in the array;

[0013] Figure 5 is a circuit diagram of the array of Figure 1 A implemented in a selfbiased FET technology with taps shown from which junction voltages may be determined for individual ones of the RF devices in the array;

[0014] Figure 6 is a circuit diagram of the array of Figure 1A implemented in an active bias FET technology with taps shown from which junction voltages may be determined for individual ones of the RF devices in the array;

[0015] Figure 7 is a flowchart illustrating an exemplary process for managing thermal compensation in an array of RF devices; and

[0016] Figure 8 is a block diagram of a mobile terminal, which may include the array of RF devices of Figure 4-8 according to the present disclosure.

DETAILED DESCRIPTION

[0017] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. [0018] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0019] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, no intervening elements are present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, no intervening elements are present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, no intervening elements are present.

[0020] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a," “an,” and “the” are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises," “comprising," “includes,” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0023] Aspects disclosed in the detailed description include systems and methods of temperature sensing in a radio frequency (RF) device array. In particular, an RF device array may include a plurality of closely arranged devices where a temperature gradient may exist between devices due to the geometry of the device. Aspects of the present disclosure compare measure a temperature-induced voltage difference between devices while subtracting out a common RF power component and using this difference signal as a proxy for a direct measure of instantaneous temperature. Based on this direct measurement, compensation for such temperature change may be provided (e.g., correcting for thermal droop).

[0024] Before addressing exemplary aspects of the present disclosure, a brief description of an array of RF devices and how waste heat may be trapped therein is provided with reference to Figures 1 A and IB. A discussion of exemplary aspects begins below with reference to Figure 2.

[0025] In this regard, Figure 1 A is a block diagram of an exemplary array 100 of radio frequency (RF) devices 102(l)-102(6) disposed in close proximity. In an exemplary aspect, the array 100 may be a plurality of transistors (e.g., Q1-Q6) stacked or cascaded to form a power amplifier such as may be used in a transceiver. As the array 100 operates, waste heat is generated. Physical geometries of the array 100 mean that waste heat may dissipate more readily at the edges 104L and 104R of a substrate 106, especially as compared to a central(ish) point 108.

[0026] Thus, Figure IB shows how a heat gradient may be created in the array 100, where the darker stipple for RF devices 102(3) and 102(4) shows trapped heat, especially as compared to the lighter stipple for RF devices 102(1) and 102(6). [0027] While six devices 102(1)- 102(6) are shown, it should be appreciated that six is arbitrary, and other array sizes are possible and may benefit from the present disclosure. Likewise, distinct arrays that are positioned proximate to one another may also create locations of trapped heat with different gradients. For example, two identical arrays mirrored across from one another (e.g., Q1A-Q6A/Q6B-Q1B) might have low heat concentrations at the endpoints (e.g., Q1A, Q1B) and high heat at the center (e.g., Q6A, Q6B).

[0028] When trapped heat, as shown in Figure IB, exists, operation of the individual RF devices 102(1)- 102(6) may change operation (e.g., thermal droop). Use of a mirror device to sense temperature may impose a finite time lag between the heat generated. This delay may impact pulsed performance, resulting in a time delay before the thermal droop compensation activates.

[0029] Accordingly, exemplary aspects provide direct sensing of junction temperatures by exploiting the temperature gradient across the array to extract a signal proportional to the temperature but independent of RF power. This extraction is possible because each of the devices 102(1)- 102(6) are amplifying the same RF signal, so taking a junction difference between a hot cell and a cold cell in the array 100 will subtract out the component due to RF power and leave only a component due to the difference in temperature between the two cells. There are various ways to get the junction voltage depending on the nature of the devices, as is better seen in Figures 2-6.

[0030] In this regard, Figure 2 is a circuit diagram of the array 100 implemented in a bipolar technology. Specifically, each of the devices 102(1)- 102(6) may be a bipolar junction transistor (BJT) having respective bases 102B(l)-102B(6) and emitters 102E(l)- 102E(6). An input inductor 200(l)-200(6) may be coupled to the bases 102B( 1)- 102B(6) . A grounding capacitor 202(l)-202(6) may be coupled to the input inductors 200(1)- 200(6) at a node 204(l)-204(6). The node 204(l)-204(6) may also provide a tap 206(1)- 206(6) that provides a base voltage signal B 1-B6. The emitters 102E( 1 )- 102E(6) may be coupled to an emitter resistor (Re) 208(l)-208(6) and an emitter inductor 210(l)-210(6). A capacitor 212(1)-212(6) may couple to the emitter inductor 210(l)-210(6) at an emitter node 214(1)-214(6). The node 214(1)-214(6) may also provide a tap 216( l)-216(6) that provides an emitter voltage signal ELE6. A junction voltage VBE may be found by subtracting E1-E6 from B 1-B6, respectively. It is possible to extract a difference between two VBE voltages and determine a thermal droop from this difference. From the thermal droop, a bias or other signal may be adjusted to compensate for the thermal droop.

[0031] Figure 3 is a circuit diagram of an extraction circuit 300 that can be used to extract the difference between two VBE voltages. The extraction circuit 300 includes a differential amplifier 302, which receives a first VBE signal (e.g., VBE 1) at a negative input through a first resistor 304 and a second VBE signal (e.g., VBE X) at a positive input through a second resistor 306. The positive input is coupled to ground 308 through a third resistor 310. An output of the differential amplifier 302 is coupled to the negative input through a feedback or fourth resistor 312. The output signal V_TDC will vary to make the inputs equal, making V_TDC indicative of the difference and able to act as a thermal droop compensation signal. Depending on the geometry of the array 100, it may make sense to compare the first device 102(1) to the last device 102(6) or to a middle device 102(3) or 102(4). In a more robust aspect, separate extraction circuits 300 may be provided for each combination of devices 102(1)- 102(6). Another aspect would include a switching network (not shown) that allowed any combination of devices 102(1)- 102(6) to be compared.

[0032] The present disclosure is not limited to BJTs and may be used with field effect transistor (FET) devices. In this regard, Figure 4 is a circuit diagram of the array 100 of Figure 1 A implemented in a dual FET technology. More specifically, the devices 102(1)- 102(6) may be dual FETs 400U(l)-400U(6), 400L(l)-400(6) coupled at a node 402(1)- 402(6). A source inductor 404(l)-404(6) may couple the node 402(l)-402(6) to a source node 406(l)-406(6) that provides a source signal S1-S6. The source node 406(l)-406(6) may couple to ground 408 through a source capacitor 410(l)-410(6). A gate of the upper FETs 400U(l)-400U(6) may couple to ground 408 through a ground capacitor 412(1)- 412(6). Likewise, the gates may couple to gate nodes 414(1)-414(6), which provides a gate signal G1-G6. A junction voltage VGS1-VGS6 may be determined by subtracting S1-S6 from G1-G6. The difference between two VGS voltages provides a measure of junction temperature and may be extracted with an extraction circuit 300.

[0033] Instead of a dual FET structure, the array 100 may be self-biased devices, as better illustrated in Figure 5. More specifically, the devices 102(1)- 102(6) may be FETs 500(l)-500(6). A source of the FETs 500(l)-500(6) may be coupled to a source resistor 502(l)-502(6). A source inductor 504( l)-504(6) may couple a source of the FETs 500(1)- 500(6) to a source node 506(l)-506(6) that provides a source signal S1-S6. The source node 506( l)-506(6) may couple to ground 508 through a source capacitor 510(l)-510(6). A gate of the FETs 500(l)-500(6) may couple to ground 508 through a ground inductor 512(1)-512(6). Likewise, the gates may couple to gate nodes 514(1)-514(6), which provides a gate signal G1-G6. A junction voltage VGSLVGS6 may be determined by subtracting S1-S6 from G1-G6. The difference between two VGS voltages provides a measure of junction temperature and may be extracted with an extraction circuit 300.

[0034] Instead of self-biasing, an active bias circuit may also be used, as is better seen in Figure 6. The devices 102(1)- 102(6) may be FETs 600(l)-600(6). A gate node 602(1)- 602(6) may couple to a differential amplifier 604(l)-604(6), which also couples to a source of the FET 600(l)-600(6). A source node 606(l)-606(6) may couple to a current source 608(l)-608(6) may also couple to the source node 606(l)-606(6). VGSLVGS6 may be directly measured at an output of the differential amplifier 604(l)-604(6). The difference between two VGS voltages provides a measure of junction temperature and may be extracted with an extraction circuit 300.

[0035] Again, it should be appreciated that while six devices 102(1)- 102(6) are described, aspects of the present disclosure may be applied to more or fewer devices.

[0036] Figure 7 is a flowchart illustrating an exemplary process 700 for managing thermal compensation in the array 100. The process 700 begins by providing at least one tap from which to measure a junction voltage for each device 102 (block 702). Two junction voltages are provided to the extraction circuit 300 (block 704). The extraction circuit 300 provides a thermal droop compensation signal V_TDC (block 706). A precursor circuit (e.g., a driver amplifier, a variable attenuator, or a bias circuit) uses V_TDC to compensate for droop (block 708).

[0037] With reference to Figure 8, the concepts described above may be implemented in various types of user elements 800, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user elements 800 will generally include a control system 802, a baseband processor 804, transmit circuitry 806 (which may include an array 100), receive circuitry 808, antenna switching circuitry 810, multiple antennas 812, and user interface circuitry 814. In a non-limiting example, the control system 802 can be a field-programmable gate array (FPGA) or an applicationspecific integrated circuit (ASIC), as an example. In this regard, the control system 802 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 808 receives radio frequency signals via the antennas 812 and through the antenna switching circuitry 810 from one or more base stations. A low noise amplifier and a filter of the receive circuitry 808 cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0038] The baseband processor 804 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. The baseband processor 804 is generally implemented in one or more digital signal processors (DSPs) and ASICs.

[0039] For transmission, the baseband processor 804 receives digitized data, which may represent voice, data, or control information, from the control system 802, which it encodes for transmission. The encoded data is output to the transmit circuitry 806, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier, which may include an array of devices 102(1)- 102(6), will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 812 through the antenna switching circuitry 810 to the antennas 812. The multiple antennas 812 and the replicated transmit and receive circuitries 806, 808 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0040] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications, as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0041] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

What is claimed is:

1. An array comprising: a plurality of devices physically proximate to one another such that waste heat generated during operation heats different ones of the plurality of devices to different degrees, each of the plurality of devices comprising at least one tap from which a junction voltage may be determined; and an extraction circuit coupled to the at least one tap on two devices of the plurality of devices and configured to generate a thermal droop control signal based on a difference in the junction voltage of the two devices.

2. The array of claim 1, wherein the plurality of devices comprises a plurality of radio frequency (RF) devices.

3. The array of claim 2, wherein the plurality of RF devices comprises a plurality of transistors.

4. The array of claim 3, wherein the plurality of transistors comprises bipolar junction transistors and the at least one tap comprises a base node and an emitter node.

5. The array of claim 3, wherein the plurality of transistors comprises a plurality of field effect transistors (FETs).

6. The array of claim 5, wherein each of the FETs is coupled to an active bias circuit.

7. The array of claim 5, wherein each of the FETs is coupled to a self-biasing circuit.

8. The array of claim 2, wherein each of the plurality of RF devices comprises a dual

FET device.

9. The array of claim 2, wherein the plurality of RF devices comprise a power amplifier.

10. The array of claim 1, wherein the extraction circuit comprises a differential amplifier.

11. A radio frequency (RF) power amplifier comprising: a plurality of RF devices physically proximate to one another and arranged such that waste heat forms a heat gradient across the plurality of RF devices, wherein the plurality of RF devices comprises a first RF device and a second RF device; the first RF device comprising a first transistor and at least one first tap from which a first junction voltage may be determined; the second RF device comprising a second transistor and at least one second tap from which a second junction voltage may be determined; and an extraction circuit configured to receive the first junction voltage and the second junction voltage and generate a thermal droop compensation signal based on the first junction voltage and the second junction voltage.

12. The RF power amplifier of claim 11, wherein the extraction circuit comprises a differential amplifier and the thermal droop compensation signal is based on a difference between the first junction voltage and the second junction voltage.

13 The RF power amplifier of claim 11, wherein the first RF device comprises a bipolar junction transistor (BJT) and the at least one first tap comprises a base node coupled to a base of the BJT through an input inductor.

14. The RF power amplifier of claim 13, wherein the RF device further comprises a second tap coupled to an emitter of the BJT through an emitter inductor and wherein the first junction voltage is based on a difference between a first voltage at the first tap and a second voltage at the second tap.

15. The RF power amplifier of claim 11, wherein the RF device comprises a dual gate pair of field effect transistors (FETs) and the at least one tap comprises a gate node coupled to a gate of an upper FET in the pair of FETs.

16. The RF power amplifier of claim 15, wherein the RF device further comprises a second tap comprising a source node coupled to a shared node between the pair of FETs through an inductor, and wherein the first junction voltage is based on a difference between a first voltage at the first tap and a second voltage at the second tap.

17. The RF power amplifier of claim 11, wherein the RF device comprises a selfbiased FET, and the at least one first tap comprises a gate node coupled to a gate of the self-biased FET.

18. The RF power amplifier of claim 17, wherein the RF device further comprises a second tap comprising a source node coupled to a source of the self-biased FET through an inductor, and wherein the first junction voltage is based on a difference between a first voltage at the first tap and a second voltage at the second tap.

19. The RF power amplifier of claim 11, wherein the RF device comprises an active biased FET, and the at least one first tap comprises a gate node coupled to a gate of the active biased FET.

20. A method of compensating for thermal droop, comprising: measuring a first junction voltage for a first device; measuring a second junction voltage for a second device; generating a thermal droop signal from the first junction voltage and the second junction voltage; and adjusting behavior of a precursor circuit based on the thermal droop signal.