EP4732387A2

EP4732387A2 - Optoelectronic devices and methods of making and using thereof

Info

Publication number: EP4732387A2
Application number: EP24743561.3A
Authority: EP
Inventors: Jung Han; Bingjun Li; Chenziyi MI
Original assignee: Yale University
Current assignee: Yale University
Priority date: 2023-06-22
Filing date: 2024-06-24
Publication date: 2026-04-29
Also published as: KR20260028070A; WO2024264039A3; CN121532916A; TW202520596A; WO2024264039A2

Abstract

Various semiconductor structures containing buried tunnel junctions or aperture regions are described. Further disclosed are methods for preparing and using such semiconductor structures which can be used, for example, in optoelectronic devices, such as vertical cavity surface emitting lasers (VCSELs), which can emit at long wavelengths.

Description

OPTOELECTRONIC DEVICES AND METHODS OF MAKING AND USING THEREOF CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Provisional Application No. 63/509,683 filed June 22, 2023, which is hereby incorporated by reference in its entirety. FIELD OF THE INVENTION This invention is in the field of optoelectronic devices, such as vertical cavity surface emitting lasers, which emit at long wavelengths at room-temperature (RT) and under continuous-wave (CW) operation. BACKGROUND OF THE INVENTION Considerable research and development and commercialization effort were invested into long wavelength (LW) vertical cavity surface emitting lasers (VCSELs), LW-VCSELs, in the late 1990s and early 2000s, motivated by applications in high-bandwidth optical networks and fueled by the so called “telecom bubble”. Unfortunately, these efforts did not yield their expected results and, with the collapse of the overheated optical telecommunication market in 2001, further progress in this area stalled. The wavelength range from 1,200 nm to 2,400 nm, is an important one since this is traditionally the range used in silica fibers for long-haul single-mode telecommunication. There has been a renewed and growing interest in LW-VCSELs which can function in this wavelength range because of multiple applications: 1) The need of low-power on-chip laser source for photonic-electronic integrated circuits; 2) the growing market for eye-safe optical sensing systems based on VCSELs and VCSEL arrays; 3) the emerging market for low-cost optical links based on single-mode fiber for distances exceeding 1 km; 4) free-space (last mile or indoor personal network) optical communication for 6G mobile and optical wireless networks; 5) the Internet of Things; 6) low-cost light detection and ranging systems; and 7) biomedical sensing and diagnostic devices and systems. In short, many applications in sensing and communication can be enabled by manufacturable VCSELs emitting at around 1,550 nm. However, one of the difficulties in developing NIR-MIR VCSELs is the need to combine semiconductor active regions providing high optical gain in the 1,200-2,400 nm range together with mirrors with high reflectivity, low optical absorption, and high thermal 1 45662394.1 conductivity. The semiconductor active regions of choice are, for example, InAlGaAs quantum wells prepared on InP substrates, while the best mirrors reported are AlAs-GaAs DBRs prepared on GaAs substrates. InP and GaAs-based structures, however, are generally incompatible in terms of epitaxial growth, which makes the realization of such VCSELs virtually impossible. There have been different approaches to make NIR-MIR VCSELs, even with some small-scale commercialization, but none have reached the point of cost-effective mass production to-date. Accordingly, fabrication of VCSELs which can emit at long a wavelength range remains very challenging. Therefore, there remains an essentially un-addressed need for long wavelength emitting VCSELs. Thus, there is a need for developing various types of structures, which can be used as mirrors, and can be fabricated via simplified methods, where the structures can be used to fabricate VCSELs having a desired emission wavelength. Therefore, it is an object of the invention to provide such structures which address and overcome the issues known to-date in the manufacture of devices, such as VCSELs. It is yet another object of the invention to provide novel methods for preparing such structures. It is still a further object of the invention to provide methods of using the structures described, such as for use in VCSELS. SUMMARY OF THE INVENTION Various semiconductor structures containing a buried tunnel junction (BTJ) are described herein. Such semiconductor structures may be used in the fabrication of optoelectronic devices, including vertical cavity surface emitting lasers (VCSELs). Details of the such semiconductor structures containing a BTJ, and optoelectronic devices formed thereof, are described herein. In addition, various light emitting structures containing an aperture region formed by ion implantation are also described herein. Such light emitting structures may be used in the fabrication of optoelectronic devices, such as vertical cavity surface emitting lasers (VCSELs). Details of the various light emitting structures containing an aperture region formed by ion implantation, and optoelectronic devices formed thereof, are further described herein. 2 45662394.1 The various semiconductor and light-emitting structures and optoelectronic devices thereof, such as VCSELs, can be used in various applications including, but not limited to, electronic, photonic, and optoelectronic applications. In particular, such VCSELs described can provide long-wavelength emission (i.e., emitting at red, near red, or infrared wavelengths from 900 to 3000 nm, as well as subranges and individual wavelengths contained therein). Further, the VCSELs described can provide optical and electrical performance with advantages compared to more commonly laser diodes and can demonstrate, for instance, superior beam quality, a compact form factor, low operating power, cost-effective wafer-level testing, higher yields, and lower cost in manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS Non-limiting embodiments are described by way of example with reference to the accompanying Figures, which are schematic and are not necessarily drawn to scale. In the Figures, each identical or nearly identical component illustrated is typically represented by a single numeral. For purposes of clarity, not every component is labeled in every figure, nor is every component shown where illustration is not necessary to allow those of ordinary skill in the art to understand the Figure(s). Figure 1A shows a non-limiting cross-sectional representation of an epitaxial semiconductor structure 100 formed from bottom to top of: (1) a stack 110 of 12 pairs of alternating layers of n⁺-indium phosphide (InP) and n--InP; (2) a layer 120 of a thick n-InP layer; (3) an emissive structure 130 of InAlGaAs, which provides an active region with a targeted emission wavelength of 1550 nm; (4) a layer 140 of p-InP; (5) an buried tunnel junction formed of: a layer 150 of p⁺⁺-InGaAs and a layer 160 of n⁺⁺-InGaAs; wherein (6) a current spreading layer 170 encapsulates the buried tunnel junction; and optionally (7) there is a non-planarity in the surface of the current spreading layer, which forms a step feature (180) and can provide an optical confinement effect. Figure 1B shows a non-limiting cross-sectional representation of an epitaxial semiconductor structure 100’ formed from bottom to top of: (1) a stack 110’ of 12 pairs of alternating layers of n⁺-indium phosphide (InP) and n--InP; (2) a layer 120’ of a thick n-InP layer; (3) an emissive structure 130’ of InAlGaAs, which provides an active region with a targeted emission wavelength of 1550 nm; (4) a layer 140’ of p-InP; (5) a layer 150’ of p⁺⁺- InGaAs; (6) a buried tunnel junction formed of a layer 160’ of n⁺⁺-InGaAs; wherein (7) a 3 45662394.1 current spreading layer 170’ encapsulates the buried tunnel junction; and optionally (7) there is a non-planarity in the surface of the current spreading layer, which forms a step feature (180’) and can provide an optical confinement effect. Figure 1C shows a non-limiting cross-sectional representation of an epitaxial semiconductor structure 100” having a p-doped second semiconductor layer 150” that was partially etched, such that the thickness of layer 150” under an n-doped second semiconductor layer 160” is thicker than the remaining layer 150”. Other layers and structures are not labeled for convenience. Figure 1D shows a non-limiting cross-sectional representation of an epitaxial semiconductor structure 100”’ having a p-doped second semiconductor layer 150”’ which was partially and completely etched, such that the thickness of layer 150” under an n-doped second semiconductor layer 160’” is thicker than the remaining layer 150” present and portions of the original layer were etched away completely. Other layers and structures are not labeled for convenience. Figure 1E shows a non-limiting cross-sectional representation of an epitaxial semiconductor structure 100”” having a p-doped second semiconductor layer 150”” having a uniform thickness and where portions of the original layer were etched away completely. It is also shown that n-doped current spreading layer 170”” can include additional non-planarity where some of the layer is partially etched away. Other layers and structures are not labeled for convenience. Figure 1f shows a non-limiting cross-sectional representation of an epitaxial semiconductor structure 100””’ having a p-doped second semiconductor layer 150”” which has been etched to have a smaller area than the n-doped second semiconductor layer 160’”’’ on top. Other layers and structures are not labeled for convenience. Figure 2 shows a non-limiting fabrication process for creating a structure having a buried tunnel junction (BTJ) therein, such as of semiconductor structure 100. Figure 3 shows a non-limiting cross-sectional representation of a light-emitting structure 200 containing a Distributed Bragg Reflector (DBR) and a buried tunnel junction (BTJ), where from bottom to top there exists: (1) a bottom structure 210 formed of a stack which consists of 12 pairs of alternating layers of n⁺-InP and n--InP, where the n⁺-InP are selectively porosified by electrochemical etching, as shown by dark bands; (2) a layer 220 of a thick n-InP layer; (3) a mesa structure which contains from bottom to top a layer 230 of 4 45662394.1 InAlGaAs, a layer 240 of p-InAlAs; a BJT formed of a layer 250 of p⁺⁺-InAlAs and a layer 260 of n⁺⁺-InP; and a current spreading layer 270 of n-InP on top, wherein the top surface of current spreading layer 270 includes a step feature 280. Additional layers of Al₂O₃ layer (295) and SiO2 (290) shown are present due to the fabrication process. Figure 4 shows a non-limiting fabrication process for creating a light-emitting structure 200 containing a Distributed Bragg Reflector (DBR) and buried tunnel junction (BTJ). Figure 5 shows a non-limiting cross-sectional representation of a vertical cavity surface emitting laser (VCSEL) 300 which is formed of light-emitting structure 200 containing a bottom DBR mirror, a top dielectric DBR mirror 310 which is present on the top of the mesa structure of light-emitting structure 200, and metal contacts 320. Figure 6 shows a non-limiting fabrication process for creating a vertical cavity surface emitting laser (VCSEL), such as VCSEL 300. Figure 7 is a graph of the I-V plots of a DBR device with 10 μm buried tunnel junction (BTJ) in diameter (solid line) and DBR device without a BTJ (dashed line). Figure 8A is a graph of the L-I or L-J relation of a NP-InP VCSEL with a 6 μm aperture region. Figure 8B is a graph of a single mode lasing spectrum of a NP-InP VCSEL with a 6 μm aperture region. Figure 9 shows a non-limiting cross-sectional representation of an epitaxial structure 400 formed from bottom to top of: (1) a stack 410 consists of 12 pairs of alternating layers of n⁺-InP and n--InP; (2) a layer 420 of a thick n-InP layer; (3) an emissive structure 430 of InAlGaAs which provides an active region with a targeted emission wavelength of 1550 nm; (4) a layer 440 of p-InAlAs; (5) a layer 450 of p⁺⁺-InAlAs; (6) a layer 460 of n⁺⁺-InP; and (7) a layer 470 of n-InP layer. Figure 10 shows a non-limiting fabrication process for creating a light-emitting structure 600 containing a Distributed Bragg Reflector (DBR) and an aperture region. Figure 11 is a graph showing a simulated implant-induced defect profile using SRIM, where the boundaries between layers are labelled by dashed black lines. Figure 12 shows a non-limiting cross-sectional representation of a light-emitting structure 600 containing a Distributed Bragg Reflector (DBR) and an aperture region therein, where from bottom to top there exists: (1) a bottom structure 610 formed of a stack which 5 45662394.1 consists of 12 pairs of alternating layers of n⁺-InP and n--InP, where the n⁺-InP are selectively porosified by electrochemical etching, as shown by dark bands; (2) a layer 620 of a thick n- InP layer; (3) a mesa structure which from bottom to top contains a layer 630 of InAlGaAs, which provides an active region with a targeted emission wavelength of 1550 nm; a layer 640 of p-InAlAs; a layer 650 of p⁺⁺-InAlAs; a layer 660 of n⁺⁺-InP; a current spreading layer 670 of n-InP on top, wherein the top surface of current spreading layer 670 includes a step feature 680. Within the mesa structure includes an aperture region formed of portions of p-InAlAs; p⁺⁺-InAlAs; n⁺⁺-InP; and n-InP, shown in part as the region of 645, 655, and 665 under step feature 680. Wherein the p-InAlAs, p⁺⁺-InAlAs, n⁺⁺-InP; and n-InP which are outside the aperture region is ion implanted to reduce conductivity and subsequent annealing restored conductivity in at least the current spreading layer of n-InP over the aperture region. Additionally, a layer of SiO₂ (690) is shown which is present due to the fabrication process. Figure 13 shows a non-limiting cross-sectional representation of a vertical cavity surface emitting laser (VCSEL) 700 which is formed of light-emitting structure 600 containing a bottom DBR, a top dielectric DBR mirror 710 which is present on the top of the mesa structure of light-emitting structure 600, and metal contacts 720. Figure 14 shows a non-limiting fabrication process for creating a vertical cavity surface emitting laser (VCSEL), such as VCSEL 700. Figure 15 is a graph of the I-V plots of a light-emitting device with 10 μm aperture region in diameter (solid line), formed by ion implantation, and a light-emitting device without an aperture region (dashed line). Figure 16A is a graph of the L-I or L-J relation of a 1380 nm NP-InP VCSEL with a 7 μm aperture region, where the threshold current was 0.5mA. Figure 16B is a graph of a single mode lasing spectrum of a 1380 nm NP-InP VCSEL with a 7 μm aperture region under an injection current of 8 mA, where the side-mode- suppression ratio was above 30dB. Figure 17A is a graph of the L-I or L-J relation of a 1550 nm NP-InP VCSEL with a 7 μm aperture region, where the threshold current was 0.67mA. Figure 17B is a graph of a single mode lasing spectrum of a 1550 nm NP-InP VCSEL with a 7 μm aperture region under an injection current of 7 mA, where the side-mode- suppression ratio was above 30dB. 6 45662394.1 DETAILED DESCRIPTION OF THE INVENTION Various semiconductor structures are described herein, as well as methods of manufacturing and using such semiconductor structures. For example, the semiconductor structures can be used as to fabricate light-emitting structures containing distributed Bragg reflector mirrors for high-performance VCSELs, which emit at long wavelengths. I. Definitions “Porosity,” as used herein refers to the volumetric ratio of air present in a porosified medium, such as a InP, GaAs, or GaSb layer(s), which is expressed as a percentage. “Electropolishing,” as used herein, refers to an n-doped indium phosphide or gallium arsenide being etched away completely or substantially etched away (where “substantially etched away” refers to etching greater than 95%, 96%, 97%, 98%, or 99%) leaving a void where n-doped material originally existed. The void represents the low-index medium (i.e., air). The air typically has a refractive index of about 1. “Refractive Index” or “Index of Refraction,” are used interchangeably and refer to the ratio of the velocity of light in a vacuum to its velocity in a specified medium, such as a layer of a InP, GaAs, or GaSb, according to the formula n = c/v, where c is the speed of light in vacuum and v is the phase velocity of light in the medium. “Refractive Index Contrast,” as used herein refers to the relative difference in refractive index between two mediums having different indices of refraction and which are in contact and form an interface. Numerical ranges include ranges of thicknesses, ranges of doping concentrations, ranges of integers, ranges of times, ranges of voltages, ranges of length, ranges of diameters, ranges of concentrations, etc. The ranges disclose individually each possible number that such a range could reasonably encompass, as well as any sub-ranges and combinations of sub-ranges encompassed therein. For example, a layer may have a thickness in the range of about 1 nm to 10 nm, where the range also discloses thicknesses that can be selected independently from about 2, 3, 4, 5, 6, 7, 8, and 9 nm, as well as any range between these numbers (for example, 3 nm to 8 nm), and any possible combination of ranges between these values. Use of the term "about" is intended to describe values either above or below the stated value, which the term “about” modifies, in a range of approx. +/- 10%; in other instances the values may range in value either above or below the stated value in a range of approx. +/- 7 45662394.1 5%. When the term "about" is used before a range of numbers (i.e., about 1-5) or before a series of numbers (i.e., about 1, 2, 3, 4, etc.) it is intended to modify both ends of the range of numbers and/or each of the numbers recited in the entire series, unless specified otherwise. II. Semiconductor Structures and Devices Containing a Buried Tunnel Junction (BTJ) Various semiconductor structures containing buried tunnel junctions are described These semiconductor structures may be used to fabricate, or otherwise form part of, other optoelectronic devices, such as light-emitting structures containing distributed Bragg reflector (DBR) mirrors, and vertical cavity surface emitting lasers (VCSELs). Details of the various semiconductor structures and optoelectronic devices containing a BTJ are described below. a. Semiconductor Structures Containing a Buried Tunnel Junction (BTJ) In some instances, a non-limiting semiconductor structure containing a buried tunnel junction (BTJ) includes: a bottom structure including alternating layers of n-doped and undoped (or low doped) semiconductor layers on a semiconductor substrate; a layer of an n-doped first semiconductor atop the bottom structure; an emissive structure including a multiple quantum well (MQW) atop the layer of n-doped first semiconductor; a layer of a p-doped first semiconductor atop the emissive structure; and a buried tunnel junction (BTJ) present on the layer of the p-doped first semiconductor, wherein the buried tunnel junction includes: a layer of p-doped second semiconductor having a p-doping level greater than about 1 × 10¹⁸ cm^-3; a layer of an n-doped second semiconductor having a n-doping level greater than about 1 × 10¹⁸ cm^-3 atop the layer of p-doped second semiconductor; wherein at least the layer of n-doped second semiconductor has a smaller surface area than the surface area of the layer of p-doped first semiconductor; 8 45662394.1 optionally wherein the layer of p-doped second semiconductor and the layer of an n-doped second semiconductor occupy equal areas or substantially equal areas on the layer of the p-doped first semiconductor; and an n-doped current spreading layer which encapsulates at least a portion of the layer of n-doped second semiconductor, and optionally at least a portion of the layer of p-doped second semiconductor, and wherein the current spreading layer outside of the portion having the layer of n-doped second semiconductor thereon contacts the p-doped second semiconductor or the p-doped first semiconductor; and wherein the current spreading layer surface optionally includes a region over the buried tunnel junction, which is elevated and forms a step feature, which provides an optical confinement effect. Exemplary non-limiting semiconductor structures containing a BTJ include those shown in Figures 1a to 1f. The BTJ is formed of a region which is buried by and within the current spreading layer. In semiconductor structure 100, for example, the BTJ is defined by layers of 150 and 160 which are encapsulated by the current spreading layer 170, which contacts layer 140. In semiconductor structure 100’, for example, the BTJ is defined by layer 160’ which is encapsulated by the current spreading layer 170’, which contacts layer 150’. As explained in Example 1, the BTJ defines a region which can provide a current confinement effect in a device containing such a tunnel junction. Further, as noted above, the top surface of the current spreading layer of the structure may include a stepped feature (i.e., 180 in Figure 1b) which is present over the BTJ and provides an optical confinement effect. For certain semiconductor materials forming part of the semiconductor structure, such as the layers of p-doped second semiconductor and n-doped second semiconductor, there are minimum doping concentrations, as detailed above. For the remaining p- or n-doped layers referenced, the p- or n- doping concentration levels are not particularly restricted. In some instances, the different p- or n- doped layers may each independently have a high doping concentration level of at least about 1 × 10¹⁹ cm^-3 or higher; or in a range of between about 0.1 × 10¹⁹ cm^-3 to 10 × 10²⁰ cm^-3. In some cases, the high doping concentration level may be about 1 × 10¹⁹ cm^-3, 2 × 10¹⁹ cm^-3, 3 × 10¹⁹ cm^-3, 4 × 10¹⁹ cm^-3, 5 × 10¹⁹ cm^-3, 6 × 10¹⁹ cm^-3, 7 × 10¹⁹ cm^-3, 8 × 10¹⁹ cm^-3, 9 × 10¹⁹ cm^-3, or 10 × 10¹⁹ cm^-3. In some other instances, the different p- or n- doped layers may each independently have a moderate doping concentration 9 45662394.1 level of greater than about 1 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 2 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 3 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 4 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, or 5 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3. In some instances, the moderately doped concentration level is in the range of 1 × 10¹⁹ cm^-3 to less than 1 × 10²⁰ cm^-3 or in the range of about 0.5 × 10¹⁹ cm^-3 to 10 × 10¹⁹ cm^-3. In some cases, the moderate doping concentration level may be about 1 × 10¹⁸ cm^-3, 2 × 10¹⁸ cm^-3, 3 × 10¹⁸ cm^-3, 4 × 10¹⁸ cm^-3, 5 × 10¹⁸ cm^-3, 6 × 10¹⁸ cm^-3, 7 × 10¹⁸ cm^-3, 8 × 10¹⁸ cm^-3, 9 × 10¹⁸ cm^-3, or 10 × 10¹⁸ cm^-3. In still other instances, however, the different p- or n- doped layers may each independently have a low doping concentration level of less than about 20 × 10¹⁷ cm^-3 or in the range of between about 0.5 × 10¹⁷ cm^-3 to 10 × 10¹⁷ cm^-3. In some cases, the low doping concentration level may be about 1 × 10¹⁷ cm^-3, 2 × 10¹⁷ cm^-3, 3 × 10¹⁷ cm^-3, 4 × 10¹⁷ cm^-3, 5 × 10¹⁷ cm^-3, 6 × 10¹⁷ cm^-3, 7 × 10¹⁷ cm^-3, 8 × 10¹⁷ cm^-3, 9 × 10¹⁷ cm^-3, or 10 × 10¹⁷ cm^-3. As noted above, at least the layer of n-doped second semiconductor has a smaller surface area than the surface area of the layer of p-doped first semiconductor. This is shown, for example, in Figures 1a to 1f, where the layer of n-doped second semiconductor occupies a smaller region or smaller surface area, as compared to the surface area of the layer of p-doped first semiconductor. In some non-limiting instances, the surface area occupied by the layer of n-doped second semiconductor may be about 1% to about 30%, as well as sub-ranges and individual values contained therein, of the total surface area of the layer of p-doped first semiconductor. In some instances, like in Figure 1a, the layer of p-doped second semiconductor and the layer of an n-doped second semiconductor occupy equal areas or substantially equal areas on the layer of the p-doped first semiconductor, as explained below. In other instances, the layer of p-doped second semiconductor and the layer of an n-doped second semiconductor occupy unequal areas on the layer of the p-doped first semiconductor. For example, the layer of p-doped second semiconductor may be of equal surface area to the layer of the p-doped first semiconductor, while the layer of an n-doped second semiconductor occupies a smaller surface area than the surface area of the layer of p-doped first semiconductor, as shown in Figure 1b. In other instances, the layer of p-doped second semiconductor can have any suitable area, may demonstrate variable thickness throughout the same layer, and/or may be etched away completely in certain portions/regions. As shown in Figure 1c, an epitaxial semiconductor structure 100” can have a p-doped second semiconductor layer 150” that was 10 45662394.1 partially etched, such that the thickness of layer 150” under an n-doped second semiconductor layer 160” is thicker than the remaining layer 150”. However, the thickness may vary in other ways and locations. As shown in Figure 1d, an epitaxial semiconductor structure 100”’ can have a p-doped second semiconductor layer 150”’ which has been partially and completely etched at different places of the same layer, such that the thickness of layer 150” under an n-doped second semiconductor layer 160’” is thicker than the remaining layer 150” present and portions of the original layer have been etched away completely, as shown. As shown in Figure 1e, an epitaxial semiconductor structure 100”” can have a p-doped second semiconductor layer 150”” with a uniform thickness throughout and portions of the original layer having been etched away completely. Figure 1e also shows that n-doped current spreading layer 170”” can include additional non-planar features, where some portions of the current spreading layer were partially etched away. Lastly, as shown in Figure 1f, an epitaxial semiconductor structure 100””’ can have a p-doped second semiconductor layer 150”” which has been etched to have a smaller surface area than the surface area of the n-doped second semiconductor layer 160’”’’ on top. Such instances can be considered an undercutting of the layer. In such instances, where the layer of n-doped second semiconductor and the layer of p-doped second semiconductor have equal areas or substantially equal areas, these are understood to lie on top of each other and form a bilayer stack present on the layer of the p- doped first semiconductor. See Figure 1a. “Substantially equal,” as used herein refers to a comparison of the areas of two different layers wherein the respective areas differ by less than about 5%, 4%, 3%, 2%, 1%, or less. For the semiconductor structures, the semiconductor substrate can be made of indium phosphide, gallium arsenide, or gallium antimonide. In certain instances, the alternating layers of the bottom structure include or are made of a binary semiconductor material selected from indium phosphide, gallium arsenide, or gallium antimonide, which is lattice- matched to, respectively, the selected semiconductor substrate made of any one of indium phosphide, gallium arsenide, or gallium antimonide. In other instances, the alternating layers of the bottom structure include or are made of a ternary semiconductor material which is lattice-matched to, respectively, the selected semiconductor substrate made of any one of indium phosphide, gallium arsenide, or gallium antimonide. In still other instances, the alternating layers of the bottom structure include or are made of a quaternary semiconductor 11 45662394.1 material which is lattice-matched to, respectively, the selected semiconductor substrate made of any one of indium phosphide, gallium arsenide, or gallium antimonide. In some instances, for the semiconductor structures described, the n-doped first semiconductor layer, the emissive structure, the p-doped first semiconductor layer, the p- doped second semiconductor layer, the n-doped second semiconductor layer, and the current spreading layer can each independently include semiconductor materials which are selected to be lattice-matched to the semiconductor substrate made of any one of indium phosphide, gallium arsenide, or gallium antimonide. Without limitation, suitable semiconductor materials which may form part of or all of the n-doped first semiconductor layer, the emissive structure, the p-doped first semiconductor layer, the p-doped second semiconductor layer, the n-doped second semiconductor layer, and the current spreading layer each can independently include semiconductor materials that are lattice-matched to an indium phosphide semiconductor substrate and are selected from, but not limited to, the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or semiconductor materials that are lattice-matched to a gallium arsenide semiconductor substrate and are selected from, but not limited to, the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or semiconductor materials that are lattice-matched to a gallium antimonide semiconductor substrate and are selected from, but not limited to, the group consisting of GaSb, AlAsSb, and AlGaAsSb. In some instances, the emissive structure, p-doped second semiconductor layer, and n- doped second semiconductor layer each can independently include semiconductor materials that are lattice-mismatched to the semiconductor substrate made of any one of indium phosphide, gallium arsenide, or gallium antimonide. In such instances, the semiconductor materials are lattice-mismatched to an indium phosphide semiconductor substrate and selected from, but not limited to, the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the semiconductor materials are lattice-matched to a gallium arsenide semiconductor substrate and are selected from, but not limited to, the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the semiconductor materials are lattice-matched to a gallium antimonide semiconductor substrate and are selected from, but not limited to, the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb. In some instances, non-limiting examples of binary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InP, GaAs, GaSb, and 12 45662394.1 AlAs. In some instances, non-limiting examples ternary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some instances, quaternary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It is understood that the selection of any binary, ternary, or quaternary semiconductor material for use in the one or more layers, as named above, is preferably based on the semiconductor materials of the layers of a given structure being lattice-matched to the selected semiconductor substrate, which may be made of any one of InP, GaAs, or GaSb. The skilled person would be able to select the appropriate semiconductor material for each layer which is lattice-matched to the semiconductor substrate, as well as the desired doping type and doping concentration level, as detailed above. For the layers and structures described above, these may have any suitable dimensions, shapes, and thicknesses suitable for their use. In some instances, the thicknesses of the different structures and layers can be as follows: Table 1. Thicknesses Layer or Structure Thickness Range* ness contained within the recited ranges in Table 1. It is understood that the thickness of the layers and structures given above for the semiconductor structures, which can be used to fabricate light-emitting structures, containing 13 45662394.1 DBR mirrors therein, and VCSELs from such structures, may also define the thicknesses of those layers and structures contained in the light-emitting structures and VCSELs. In some instances, for the bottom structures, the n-doped semiconductor layers present within the alternating layers each have identical thicknesses to each other and/or the undoped (or low doped) semiconductor layers present within the alternating layers each have identical thicknesses to each other. It is possible for the n-doped and undoped (or low doped) semiconductor layers to have the same or different thicknesses. A non-limiting method for making a semiconductor structure including a buried tunnel junction (BTJ), can include the steps of: (i) forming a bottom structure including alternating layers of n-doped and undoped (or low doped) semiconductor layers on a semiconductor substrate; (ii) depositing a layer of an n-doped first semiconductor atop the bottom structure; (iii) depositing or forming an emissive structure including a multiple quantum well (MQW) atop the layer of the n-doped first semiconductor; (iv) depositing a layer of a p-doped first semiconductor atop the emissive structure; (v) depositing a layer of p-doped second semiconductor, having a p-doping level greater than about 1 × 10¹⁸ cm^-3, atop the layer of the p-doped first semiconductor; (vi) depositing a layer of an n-doped semiconductor, having a n-doping level greater than about 1 × 10¹⁸ cm^-3, a top the layer of p-doped second semiconductor; (vii) forming or patterning a masking material over a top surface portion of the layer of n-doped semiconductor; (viii) etching to remove at least the layer of n-doped semiconductor and optionally the p-doped second semiconductor outside of the surface portion having the masking material thereon; (ix) removing the masking material; and (x) depositing an n-doped current spreading layer, which encapsulates at least a portion of the layer of n-doped second semiconductor, and optionally a portion of the layer of p-doped second semiconductor, and wherein the current 14 45662394.1 spreading layer outside the surface portion contacts the p-doped second semiconductor or the p-doped first semiconductor. Details for making the bottom structure are provided in Section IV below. An exemplary scheme of the above method is shown in Figure 2, where the BTJ is formed by selectively etching layer 160 and optionally layer 150 to define a tunnel junction which is subsequently buried by a current spreading layer. Due to the non-planarity resulting from etching of layer 160 and optionally layer 150, which are not protected by a masking material, when the current spreading layer is deposited it can produce a stepped feature on the top surface of the current spreading layer over the region of the BTJ. For the structures and layers formed or deposited in the methods described above, these can each be independently formed or deposited by art known deposition methods, including metal organic chemical vapor deposition (MOCVD). The selection of precursors, p- or n- dopants, and conditions for forming and doping such structures and layers at defined thicknesses are known in the art. Methods for depositing/forming the emissive structure including a multiple quantum well (MQW) are known in the art. In some instances, the masking material is, without limitation, selected from the group consisting of a dielectric (such as silicon dioxide, silicon nitride, aluminum oxide) and/or a photoresist. Such materials may be formed by various methods, such as plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods known in the art. For the methods described, patterning, etching, or removing of any materials, as needed, can be performed, for example, by any suitable technique, such as wet chemical etching, plasma etching, inductively coupled plasma reactive-ion etching (ICP-RIE). For the methods described, the semiconductor substrate can be made of indium phosphide, gallium arsenide, or gallium antimonide. In certain instances, the alternating layers of the bottom structure include or are made of a binary semiconductor material selected from indium phosphide, gallium arsenide, or gallium antimonide, which is lattice- matched to, respectively, the selected semiconductor substrate made of any one of indium phosphide, gallium arsenide, or gallium antimonide. In other instances, the alternating layers of the bottom structure include or are made of a ternary semiconductor material which is lattice-matched to, respectively, the selected semiconductor substrate made of any one of 15 45662394.1 indium phosphide, gallium arsenide, or gallium antimonide. In still other instances, the alternating layers of the bottom structure include or are made of a quaternary semiconductor material which is lattice-matched to, respectively, the selected semiconductor substrate made of any one of indium phosphide, gallium arsenide, or gallium antimonide. In some instances, for the semiconductor structures formed according to the methods, the n-doped first semiconductor layer, the emissive structure, the p-doped first semiconductor layer, the p-doped second semiconductor layer, the n-doped second semiconductor layer, and the current spreading layer can each independently include semiconductor materials which are selected to be lattice-matched to the semiconductor substrate made of any one of indium phosphide, gallium arsenide, or gallium antimonide. Without limitation, suitable semiconductor materials which may form part of or all of the n-doped first semiconductor layer, the emissive structure, the p-doped first semiconductor layer, the p-doped second semiconductor layer, the n-doped second semiconductor layer, and the current spreading layer each can independently include semiconductor materials that are lattice-matched to an indium phosphide semiconductor substrate and are selected from, but not limited to, the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or semiconductor materials that are lattice-matched to a gallium arsenide semiconductor substrate and are selected from, but not limited to, the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or semiconductor materials that are lattice-matched to a gallium antimonide semiconductor substrate and are selected from, but not limited to, the group consisting of GaSb, AlAsSb, and AlGaAsSb. In some instances of the methods, the emissive structure, p-doped second semiconductor layer, and n-doped second semiconductor layer each can independently include semiconductor materials that are lattice-mismatched to the semiconductor substrate made of any one of indium phosphide, gallium arsenide, or gallium antimonide. In such instances, the semiconductor materials are lattice-mismatched to an indium phosphide semiconductor substrate and selected from, but not limited to, the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the semiconductor materials are lattice-matched to a gallium arsenide semiconductor substrate and are selected from, but not limited to, the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the semiconductor materials are lattice- matched to a gallium antimonide semiconductor substrate and are selected from, but not limited to, the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb. 16 45662394.1 In some instances, non-limiting examples of binary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InP, GaAs, GaSb, and AlAs. In some instances, non-limiting examples ternary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some instances, quaternary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It is understood that the selection of any binary, ternary, or quaternary semiconductor material for use in the one or more layers, as named above, is preferably based on the semiconductor materials of the layers of a given structure being lattice-matched to the selected semiconductor substrate, which may be made of any one of InP, GaAs, or GaSb. The skilled person would be able to select the appropriate semiconductor material for each layer which is lattice-matched to the semiconductor substrate, as well as the desired doping type and doping concentration level, as detailed above. For the methods described, the layers, structures, and overall resulting semiconductor structure formed according to the method may have any suitable dimension, shape, and thickness. Exemplary and non-limiting thicknesses of the structures and layers of the overall resulting semiconductor structure are given in Table 1. b. Light-Emitting Structure containing a Distributed Bragg Reflector (DBR) Mirror and a Buried Tunnel Junction (BTJ) The semiconductor structures containing a BTJ, as described above, can be used in the fabrication of light-emitting structures which contain a distributed Bragg reflector and have a buried tunnel junction (BTJ) therein. In one instance, such a light-emitting structure containing a distributed Bragg reflector (DBR) mirror and a buried tunnel junction (BTJ) therein, includes: a bottom structure including alternating layers of n-doped and undoped (or low doped) semiconductor layers on a semiconductor substrate, wherein the n-doped layers are porous and comprise a plurality of pores; and, wherein the undoped (or low doped) layers are non-porous or substantially non-porous; a layer of an n-doped first semiconductor atop the bottom structure; an emissive structure including a multiple quantum well (MQW) atop the layer of n-doped first semiconductor; 17 45662394.1 a layer of a p-doped first semiconductor atop the emissive structure; and a buried tunnel junction present on a portion (or sub-region) of the layer of p- doped first semiconductor, wherein the buried tunnel junction (BTJ) defines an aperture region and includes: a layer of p-doped second semiconductor having a p-doping level greater than about 1 × 10¹⁸ cm^-3; a layer of an n-doped second semiconductor, having a n-doping level greater than about 1 × 10¹⁸ cm^-3, atop the layer of p-doped second semiconductor; wherein at least the layer of n-doped second semiconductor has a smaller surface area than the surface area of the layer of p-doped first semiconductor; optionally wherein the layer of p-doped second semiconductor and the layer of n-doped second semiconductor have equal areas or substantially equal areas on the layer of the p-doped first semiconductor; and an n-doped current spreading layer which encapsulates at least a portion of the layer of n-doped second semiconductor, and optionally at least a portion of the layer of p-doped second semiconductor, and wherein the current spreading layer outside of the portion having the layer of n-doped second semiconductor thereon contacts the p-doped second semiconductor or the p-doped first semiconductor; and wherein the current spreading layer surface optionally includes a region over the buried tunnel junction which is elevated and forms a step feature, which provides an optical confinement effect. A non-limiting example of a light-emitting structure which contains such a DBR mirror, as described above, is shown in Figure 3, as light-emitting structure 200 including a DBR and BTJ therein. In some instances, the porosity present in the n-doped layers of the bottom structure, which are porous, is of at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%. Due the presence of the porosity in the n-doped layers of the bottom structure, air can fill the plurality of pores, such that the refractive index of the porosified n-doped layers is 18 45662394.1 lower than that of the non-porous or substantially non-porous undoped (or low doped) layers. In some instances, a refractive index contrast (Δn) exists between the alternating layers, after porosification, which is in a range of about 0.1 to about 2, or about 0.1 to about 2.5. For the light-emitting structures, the semiconductor substrate can be made of indium phosphide, gallium arsenide, or gallium antimonide. In certain instances, the alternating layers of the bottom structure include or are made of a binary semiconductor material selected from indium phosphide, gallium arsenide, or gallium antimonide, which is lattice- matched to, respectively, the selected semiconductor substrate made of any one of indium phosphide, gallium arsenide, or gallium antimonide. In other instances, the alternating layers of the bottom structure include or are made of a ternary semiconductor material which is lattice-matched to, respectively, the selected semiconductor substrate made of any one of indium phosphide, gallium arsenide, or gallium antimonide. In still other instances, the alternating layers of the bottom structure include or are made of a quaternary semiconductor material which is lattice-matched to, respectively, the selected semiconductor substrate made of any one of indium phosphide, gallium arsenide, or gallium antimonide. In some instances, for the light-emitting structures described, the n-doped first semiconductor layer, the emissive structure, the p-doped first semiconductor layer, the p- doped second semiconductor layer, the n-doped second semiconductor layer, and the current spreading layer can each independently include semiconductor materials which are selected to be lattice-matched to the semiconductor substrate made of any one of indium phosphide, gallium arsenide, or gallium antimonide. Without limitation, suitable semiconductor materials which may form part of or all of the n-doped first semiconductor layer, the emissive structure, the p-doped first semiconductor layer, the p-doped second semiconductor layer, the n-doped second semiconductor layer, and the current spreading layer each can independently include semiconductor materials that are lattice-matched to an indium phosphide semiconductor substrate and are selected from, but not limited to, the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or semiconductor materials that are lattice-matched to a gallium arsenide semiconductor substrate and are selected from, but not limited to, the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or semiconductor materials that are lattice-matched to a gallium antimonide semiconductor substrate and are selected from, but not limited to, the group consisting of GaSb, AlAsSb, and AlGaAsSb. 19 45662394.1 In some instances, the emissive structure, p-doped second semiconductor layer, and n- doped second semiconductor layer each can independently include semiconductor materials that are lattice-mismatched to the semiconductor substrate made of any one of indium phosphide, gallium arsenide, or gallium antimonide. In such instances, the semiconductor materials are lattice-mismatched to an indium phosphide semiconductor substrate and selected from, but not limited to, the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the semiconductor materials are lattice-matched to a gallium arsenide semiconductor substrate and are selected from, but not limited to, the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the semiconductor materials are lattice-matched to a gallium antimonide semiconductor substrate and are selected from, but not limited to, the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb. For certain semiconductor materials forming part of the light emitting structure, such as the layers of p-doped second semiconductor and n-doped second semiconductor, there are minimum doping concentrations, as detailed above. For the remaining p- or n-doped layers referenced, the p- or n- doping concentration levels are not particularly restricted. In some instances, the different p- or n- doped layers may each independently have a high doping concentration level of at least about 1 × 10¹⁹ cm^-3 or higher; or in a range of between about 0.1 × 10¹⁹ cm^-3 to 10 × 10²⁰ cm^-3. In some cases, the high doping concentration level may be about 1 × 10¹⁹ cm^-3, 2 × 10¹⁹ cm^-3, 3 × 10¹⁹ cm^-3, 4 × 10¹⁹ cm^-3, 5 × 10¹⁹ cm^-3, 6 × 10¹⁹ cm^-3, 7 × 10¹⁹ cm^-3, 8 × 10¹⁹ cm^-3, 9 × 10¹⁹ cm^-3, or 10 × 10¹⁹ cm^-3. In some other instances, the different p- or n- doped layers may each independently have a moderate doping concentration level of greater than about 1 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 2 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 3 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 4 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, or 5 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3. In some instances, the moderately doped concentration level is in the range of 1 × 10¹⁹ cm^-3 to less than 1 × 10²⁰ cm^-3 or in the range of about 0.5 × 10¹⁹ cm^-3 to 10 × 10¹⁹ cm^-3. In some cases, the moderate doping concentration level may be about 1 × 10¹⁸ cm^-3, 2 × 10¹⁸ cm^-3, 3 × 10¹⁸ cm^-3, 4 × 10¹⁸ cm^-3, 5 × 10¹⁸ cm^-3, 6 × 10¹⁸ cm^-3, 7 × 10¹⁸ cm^-3, 8 × 10¹⁸ cm^-3, 9 × 10¹⁸ cm^-3, or 10 × 10¹⁸ cm^-3. In still other instances, however, the different p- or n- doped layers may each independently have a low doping concentration level of less than about 20 × 10¹⁷ cm^-3 or in the range of between about 0.5 × 10¹⁷ cm^-3 to 10 × 10¹⁷ cm^-3. In some cases, the low doping concentration level may be 20 45662394.1 about 1 × 10¹⁷ cm^-3, 2 × 10¹⁷ cm^-3, 3 × 10¹⁷ cm^-3, 4 × 10¹⁷ cm^-3, 5 × 10¹⁷ cm^-3, 6 × 10¹⁷ cm^-3, 7 × 10¹⁷ cm^-3, 8 × 10¹⁷ cm^-3, 9 × 10¹⁷ cm^-3, or 10 × 10¹⁷ cm^-3. In some instances, non-limiting examples of binary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InP, GaAs, GaSb, and AlAs. In some instances, non-limiting examples ternary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some instances, quaternary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It is understood that the selection of any binary, ternary, or quaternary semiconductor material for use in the one or more layers, as named above, is preferably based on the semiconductor materials of the layers of a given structure being lattice-matched to the selected semiconductor substrate, which may be made of any one of InP, GaAs, or GaSb. The skilled person would be able to select the appropriate semiconductor material for each layer which is lattice-matched to the semiconductor substrate, as well as the desired doping type and doping concentration level, as detailed above. For the light-emitting structures described above, the layers, structures, and overall resulting light-emitting structure may have any suitable dimension, shape, and thickness. Exemplary and non-limiting thicknesses of the structures and layers of the overall resulting light-emitting structure are given in Table 1. In some instances, the BTJ may form part of a mesa structure, as shown in Figure 3, the dimensions of such a mesa structure can be selected to be larger than the dimensions of the BTJ. In other words, the mesa structure contains the BTJ within. A non-limiting method for making such light-emitting structure including DBR mirrors and a buried tunnel junction (BTJ), can include the steps of: (i’) providing or forming a semiconductor structure including a buried tunnel junction (BTJ), wherein the semiconductor structure includes: a bottom structure including alternating layers of n-doped and undoped or low-doped semiconductor layers on a semiconductor substrate; a layer of an n-doped first semiconductor atop the bottom structure; 45662394.1 an emissive structure comprising a multiple quantum well (MQW) atop the layer of the n-doped first semiconductor; a layer of a p-doped first semiconductor atop the emissive structure; and a buried tunnel junction (BTJ) present on the layer of p-doped first semiconductor, wherein the buried tunnel junction includes: a layer of p-doped second semiconductor having a p-doping level greater than about 1 × 10¹⁸ cm^-3; a layer of an n-doped second semiconductor having a n-doping level greater than about 1 × 10¹⁸ cm^-3 atop the layer of p-doped second semiconductor; wherein at least the layer of n-doped second semiconductor has a smaller surface area than the surface area of the layer of p-doped first semiconductor; optionally wherein the layer of p-doped second semiconductor and the layer of n-doped second semiconductor have equal areas or substantially equal areas on the layer of the p-doped first semiconductor; and an n-doped current spreading layer which encapsulates at least a portion of the layer of n-doped second semiconductor, and optionally at least a portion of the layer of p-doped second semiconductor, wherein the current spreading layer outside of the portion having the layer of n-doped second semiconductor thereon contacts the p-doped second semiconductor or the p- doped first semiconductor; and wherein the current spreading layer surface optionally includes a region over the buried tunnel junction which is elevated and forms a step feature, which provides an optical confinement effect; 22 45662394.1 (ii’) forming a mesa structure by etching a portion of the current spreading layer, the layer of p-doped first semiconductor, optionally the layer of p-doped second semiconductor, and the emissive structure; (iii’) depositing a layer of silicon dioxide over the mesa structure, wherein at least a portion of the layer of n-doped first semiconductor is not covered by the layer of silicon dioxide; (iv’) etching the portion that is not covered by the layer of silicon dioxide to form a trench exposing a side-wall of the alternating layers of the bottom structure; (v’) selectively porosifying the n-doped semiconductor layers of the bottom structure, wherein a plurality of pores are formed and wherein the undoped (or low doped) semiconductor layers remain non-porous or substantially non- porous; (vi’) depositing one or more materials to cover the trench, the side-wall, and side-walls of the mesa structure; (vii’) selectively removing the one or more materials to expose at least a portion of the mesa structure top and optionally a portion of the layer of n- doped first semiconductor, if covered by the one or more materials; and (viii’) forming metal contacts on a portion of the mesa structure top and optionally a portion of the layer of n-doped first semiconductor. Methods for forming a structure including a BTJ are described above. A non-limiting example scheme for forming a light-emitting structure containing a DBR mirror and BTJ is shown in Figure 4. For the structures and layers formed or deposited in the methods described above, these can each be independently formed or deposited by art known deposition methods, including metal organic chemical vapor deposition (MOCVD). The selection of precursors, p- or n- dopants, and conditions for forming and doping such structures and layers at defined thicknesses are known in the art. For the methods described for preparing such light-emitting structures, patterning, etching, or removing can be performed, for example, by any suitable technique, such as wet chemical etching, plasma etching, inductively coupled plasma reactive-ion etching (ICP- RIE). 23 45662394.1 In some instances of the methods, the one or more materials are selected from the group consisting of silicon dioxide, aluminum oxide, and silicon nitride, spin-on-glass; and/or the one or more materials are organic materials selected from the group consisting of benzocyclobutene (BCB), a polyimide, and a photoresist; and combinations thereof. Various types of photoresists are known in the art. For the methods described, the deposition of layers of silicon oxide and the one or more materials each may be formed by various methods, such as plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods known in the art. Other selections for the light-emitting structure and layers therein are given above in Section IIb above. In some instances of the methods, the porosity formed in step (v’) is of at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%. In some instances of the methods, step (v’) is performed by electrochemical etching in an electrolyte solution and under an applied bias voltage. In certain instances, the electrolyte solution can include halide ions, hydrochloric acid (HCl), sulfuric acid (H₂SO₄), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)2, Ca(OH)2, Sr(OH)2, NH4OH, NaCl, NaF, nitric acid (HNO₃), organic acids and their salts (such as oxalic acid and citric acid), and mixtures thereof. In some instances of the methods, the metal contacts formed during step (viii’) are formed of or include one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof. Methods for forming such metal contacts are known to those of ordinary skill in the art. Regarding the mesa structure formed in step (ii’), the dimensions of the mesa structure are selected to be larger than the dimensions of the BTJ. In other words, the mesa structure contains the BTJ therein. The mesa structure can be formed, for example, by wet etching or plasma etching, such as RIE etching. c. Optoelectronic Devices Containing a Buried Tunnel Junction (BTJ) The light-emitting structure containing a DBR and BTJ, as described above, can be used in the fabrication of optoelectronic devices having a buried tunnel junction (BTJ) therein. In some instances, an optoelectronic device can include: a light-emitting structure including a bottom distributed Bragg reflector mirror and a buried tunnel junction (BTJ) therein; 24 45662394.1 a top distributed Bragg reflector mirror; and metal contacts. For the optoelectronic devices, the light-emitting structure contains a distributed Bragg reflector (DBR) and a BTJ, as described above. A non-limiting example of an optoelectronic device, such as a VCSEL, is shown in Figure 5. In some instances, the top distributed Bragg reflector is formed of or includes alternating layers of any one of a-Si/SiO2, TiO2/SiO2, Ta2O5/SiO2, Nb2O5/SiO2, ZnSe/SiO2, a- Si/Al2O3, a-Si/MgF, ZnS/MgF, a-Si/CaF2, or combinations thereof. In some instances, the metal contacts are formed of or include one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof. In some instances, the optoelectronic device is a vertical cavity surface emitting laser (VCSEL). In some cases, the vertical cavity surface emitting laser operates at room temperature (about 25 ºC) and in a continuous-wave mode. In some other cases, the vertical cavity surface emitting laser operates at temperatures below about 0 ºC, above about 25 ºC, or above about 85 ºC. In still other instances, the vertical cavity surface emitting laser can operate in a pulse-mode. The vertical cavity surface emitting laser, which includes a BTJ, can emit in the infrared and/or red wavelength region depending on the selection of the emissive structure material. In some cases, the vertical cavity surface emitting laser has a power conversion efficiency of at least about 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 7.5%, or 10%. A non-limiting method for making an optoelectronic device including a buried tunnel junction (BTJ), can include the steps of: (i”) providing or forming a light-emitting structure including a bottom distributed Bragg reflector mirror and a buried tunnel junction (BTJ) within; (ii”) providing or forming a top distributed Bragg reflector mirror on the light- emitting structure; and (iii”) providing or forming metal contacts on the optoelectronic device. For the optoelectronic devices formed according to the above method, the light- emitting structure contains a distributed Bragg reflector (BDR) mirror and a BTJ, as described above. A non-limiting scheme of a process of fabricating an optoelectronic device, such as a VCSEL, is shown in Figure 6. 25 45662394.1 In such methods, the top distributed Bragg reflector mirror of step (ii”) can include alternating layers of any one of a-Si/SiO2, TiO2/SiO2, Ta2O5/SiO2, Nb2O5/SiO2, ZnSe/SiO2, a- Si/Al₂O₃, a-Si/MgF, ZnS/MgF, a-Si/CaF₂, or combinations thereof. Methods of making such DBRs, having the aforementioned alternating layers, are known in the art. The number of alternating layers in such DBRs can depend on the materials selected. The top DBR mirror can be deposited by means known in the art and may include annealing to increase the reflectivity. In some instances, the top DBR mirror has a reflectivity of at least about 97% or higher. For the methods described above, the metal contacts of step (iii”) can be formed of or include one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof. For any of the methods described in Section II it is understood that the order of certain steps may be interchangeable, as permitted and without negatively impacting the structures or devices formed. For instance, steps (ii”) and (iii”) of the method of making an optoelectronic device may be performed in any suitable order. III. Light Emitting Structures and Devices Containing an Aperture Region formed by Ion Implantation Various light emitting structures and devices containing an aperture region formed by ion implantation are described herein. These light emitting structures may be used to fabricate, or otherwise form part of, other optoelectronic devices, such as light-emitting structures containing distributed Bragg reflector (DBR) mirrors therein, and vertical cavity surface emitting lasers (VCSELs). Details of the various light emitting structures and devices containing an aperture region formed by ion implantation are described below. a. Light-Emitting Structures containing a Distributed Bragg Reflector (DBR) Mirror and an Aperture Region formed by Ion Implantation In one instance, a light-emitting structure containing a distributed Bragg reflector (DBR) mirror and an aperture region formed by ion implantation, includes: a bottom structure including alternating layers of n-doped and undoped (or low doped) semiconductor layers on a semiconductor substrate, wherein the n- doped semiconductor layers are porous and comprise a plurality of pores; and, wherein the undoped (or low doped) are non-porous or substantially non- porous; 26 45662394.1 a layer of an n-doped first semiconductor atop the bottom structure; an emissive structure including a multiple quantum well (MQW) atop the layer of semiconductor; a layer of a p-doped first semiconductor atop the emissive structure; a layer of a p-doped second semiconductor, having a p-doping level greater than about 1 × 10¹⁸ cm^-3, atop the layer of p-doped first semiconductor; a layer of an n-doped second semiconductor, having a n-doping level greater than about 1 × 10¹⁸ cm^-3, atop the layer of p-doped second semiconductor; an n-doped current spreading layer atop the layer of n-doped second semiconductor; wherein an aperture region is present, wherein electrical conductivity of portions of the layer of p-doped first semiconductor within the aperture region is greater than electrical conductivity of the layer of p-doped first semiconductor outside of the aperture region; wherein the layer of p-doped first semiconductor, and optionally the p-doped second semiconductor, and optionally the n-doped second semiconductor have a higher electrical resistance outside of the aperture region, as compared to within the aperture region; wherein the current spreading layer is electrically conductive within and outside the aperture region; and wherein the current spreading layer optionally comprises a region on the top surface over the aperture region, which is elevated and forms a step feature which provides an optical confinement effect. A non-limiting example of a light-emitting structure 600 containing such a DBR mirror, as described above, is shown in Figure 12. The aperture region, as discussed above and shown in Figure 12, defines a portion of the light emitting structure formed of portions of certain layers. The aperture region is formed by ion implantation where an ion implant mask protects a region of the structure from damage to conductivity under the mask when exposed to and implanted with ions. This mask protected region defines the aperture region, which contains at least 645, 655, and 665, which are not ion implanted, as shown in Figure 12. For at least the n-doped current spreading layer, annealing restores conductivity following ion implantation outside of the aperture region. The aperture region discussed provides a current 27 45662394.1 confinement effect, since the implanted region of p-doped first semiconductor remains resistive, when the light-emitting structure containing a DBR mirror and aperture region is used in optoelectronic applications. Further, an etching step using the same mask as the ion implantation can create the presence of an optional stepped feature (680) over the aperture region which can provide an optical confinement effect so that the lasing mode has larger overlap with the aperture region. For certain semiconductor materials forming part of the light emitting structure, such as the layers of p-doped semiconductor and n-doped second semiconductor, there are minimum doping concentrations, as detailed above. For the remaining p- or n-doped layers referenced, the p- or n- doping concentration levels are not particularly restricted. In some instances, the different p- or n- doped layers may each independently have a high doping concentration level of at least about 1 × 10¹⁹ cm^-3 or higher; or in a range of between about 0.1 × 10¹⁹ cm^-3 to 10 × 10²⁰ cm^-3. In some cases, the high doping concentration level may be about 1 × 10¹⁹ cm^-3, 2 × 10¹⁹ cm^-3, 3 × 10¹⁹ cm^-3, 4 × 10¹⁹ cm^-3, 5 × 10¹⁹ cm^-3, 6 × 10¹⁹ cm^-3, 7 × 10¹⁹ cm^-3, 8 × 10¹⁹ cm^-3, 9 × 10¹⁹ cm^-3, or 10 × 10¹⁹ cm^-3. In some other instances, the different p- or n- doped layers may each independently have a moderate doping concentration level of greater than about 1 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 2 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 3 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 4 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, or 5 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3. In some instances, the moderately doped concentration level is in the range of 1 × 10¹⁹ cm^-3 to less than 1 × 10²⁰ cm^-3 or in the range of about 0.5 × 10¹⁹ cm^-3 to 10 × 10¹⁹ cm^-3. In some cases, the moderate doping concentration level may be about 1 × 10¹⁸ cm^-3, 2 × 10¹⁸ cm^-3, 3 × 10¹⁸ cm^-3, 4 × 10¹⁸ cm^-3, 5 × 10¹⁸ cm^-3, 6 × 10¹⁸ cm^-3, 7 × 10¹⁸ cm^-3, 8 × 10¹⁸ cm^-3, 9 × 10¹⁸ cm^-3, or 10 × 10¹⁸ cm^-3. In still other instances, however, the different p- or n- doped layers may each independently have a low doping concentration level of less than about 20 × 10¹⁷ cm^-3 or in the range of between about 0.5 × 10¹⁷ cm^-3 to 10 × 10¹⁷ cm^-3. In some cases, the low doping concentration level may be about 1 × 10¹⁷ cm^-3, 2 × 10¹⁷ cm^-3, 3 × 10¹⁷ cm^-3, 4 × 10¹⁷ cm^-3, 5 × 10¹⁷ cm^-3, 6 × 10¹⁷ cm^-3, 7 × 10¹⁷ cm^-3, 8 × 10¹⁷ cm^-3, 9 × 10¹⁷ cm^-3, or 10 × 10¹⁷ cm^-3. In some instances, the semiconductor substrate is preferably made of indium phosphide and the layer of p-doped first semiconductor is made of p-doped InAlAs or p- doped InAlGaAs. In other instances, the semiconductor substrate may be made of other 28 45662394.1 semiconductor materials, such as GaAs or GaSb. The choice of semiconductor material should be made to ensure it is lattice matched to the choice of semiconductor substrate. In some instances, the alternating layers of the bottom structure include or are formed of a binary semiconductor material (such as indium phosphide) that is lattice-matched to the semiconductor substrate. In some other instances, the alternating layers of the bottom structure include or are formed of a ternary semiconductor material that is lattice-matched to the semiconductor substrate. In yet other instances, the alternating layers of the bottom structure include or are formed of a quaternary semiconductor material that is lattice-matched to the semiconductor substrate. In some instances, the n-doped first semiconductor, the emissive structure, p-doped first semiconductor, the p-doped second semiconductor, n-doped second semiconductor, and current spreading layer each independently include or are formed of one or more materials that are lattice-matched to the semiconductor substrate. In some instances, the one or more materials are lattice-matched to, for example, an indium phosphide semiconductor substrate and are selected from, but not limited to, the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb. In other instances, the emissive structure, p-doped second semiconductor, and n- doped second semiconductor each independently include one or more materials that are lattice-mismatched to an indium phosphide semiconductor substrate. In such instances, the one or more materials can be selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb. In some instances, non-limiting examples of binary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InP, GaAs, GaSb, and AlAs. In some instances, non-limiting examples ternary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some instances, quaternary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It is understood that the selection of any binary, ternary, or quaternary semiconductor material for use in the one or more layers, as named above, is preferably based on the semiconductor materials of the layers of a given structure being lattice-matched to the selected semiconductor substrate, which may be made of any one of InP, GaAs, or GaSb. The skilled person would be able to select the appropriate 29 45662394.1 semiconductor material for each layer which is lattice-matched to the semiconductor substrate, as well as the desired doping type and doping concentration level, as detailed above. In some instances, the layer of p-doped first semiconductor, and optionally the p- doped second semiconductor, and optionally the n-doped second semiconductor outside the aperture region have an electrical conductivity which is about 1-4 orders of magnitude lower, as compared to within the aperture region. The choice of material which forms the layer of p- doped first semiconductor should preferably be a material which when ion implanted experiences a reduction in conductivity (becomes more resistive), as compared to before ion implantation, and which does not recover or significantly recover electrical conductivity when annealed at high temperatures. “Significantly recover,” as used herein refers to a recovery of less than about 50%, less than about 40%, less than about 30%, less than about 20%, less than about 10%, less than about 5%, less than about 1% of the original electrical conductivity of the material prior to ion implantation. In some instances, the porosity present in the n-doped layers of the bottom structure, which are porous, is of at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%. The porous n-doped semiconductor layers of the bottom structure have a plurality of pores, where air can fill the pores such that the refractive index of the porosified semiconductor layers is lower than that of the non-porous or substantially non-porous undoped semiconductor layers. In some instances, a refractive index contrast (Δn) exists between the alternating layers, after porosification, which is in a range of about 0.1 to about 2, or about 0.1 to about 2.5. For the layers and structures of the light-emitting structures described above, these may have any suitable dimensions, shapes, and thicknesses suitable for their use. In some instances, the thicknesses of the different structures and layers can be as follows: 30 45662394.1 Table 2. Thicknesses Layer or Structure Thickness Range* Bottom Structure 270 nm to 5,400 nm ness contained w e ec e a ges a e . It is understood that the thickness of the structures above which can be used to fabricate VCSELs from such light-emitting structures containing DBRs within may also define the thicknesses of those layers. In some instances, for the light emitting structures, the n-doped semiconductor layers present within the alternating layers each have identical thicknesses to each other and/or the undoped (or low doped) semiconductor layers present within the alternating layers each have identical thicknesses to each other. It is possible for the n-doped and undoped (or low doped) semiconductor layers to have the same or different thicknesses. In some instances, the aperture region is contained with a mesa structure, as shown in Figure 12. In such instances, the dimensions of the mesa structure are selected to be larger than the dimensions of the aperture region. A non-limiting method for making such light-emitting structures containing DBR mirrors and an aperture region formed by ion implantation, can include the steps of: (a) providing or forming a light emitting structure including: a bottom structure including alternating layers of n-doped and undoped (or low doped) semiconductor layers on a semiconductor substrate; a layer of an n-doped first semiconductor atop the bottom structure; 45662394.1 an emissive structure including a multiple quantum well (MQW) atop the layer of the first semiconductor; a layer of a p-doped first semiconductor atop the emissive structure; a layer of a p-doped second semiconductor, having a p-doping level greater than about 1 × 10¹⁸ cm^-3 atop the layer of p-doped first semiconductor; a layer of an n-doped second semiconductor, having a n-doping level greater than about 1 × 10¹⁸ cm^-3, atop the layer of p-doped second semiconductor; and an n-doped current spreading layer atop the layer of n-doped second semiconductor; (b) placing a masking material over a top surface region of the current spreading layer of the structure; (c) performing ion implantation to reduce the conductivity of at least the layer of p-doped first semiconductor, which is not covered by the masking material; (d) etching a portion of the current spreading layer, wherein the etching does not remove the current spreading layer under the masking material; (e) removing the masking material; (f) depositing a first layer of silicon dioxide over a portion of the current spreading layer to cover at least the area where the masking material was present; (g) annealing the structure to increase the electrical conductivity of the current spreading layer; (h) forming a mesa structure by etching the portion of the current spreading layer, the n-doped second semiconductor, the p-doped second semiconductor, the p-doped first semiconductor, and the emissive structure which are not covered by the first layer of silicon dioxide; (i) depositing a second layer of silicon dioxide over the mesa structure, wherein at least a portion of the n-doped first semiconductor layer is not covered by the second layer of silicon dioxide; (j) etching the structure that is not covered by the second layer of silicon dioxide to form a trench exposing a side-wall of the alternating layers of the bottom structure; 32 45662394.1 (k) selectively porosifying the n-doped semiconductor layers in the alternating layers of the bottom structure, wherein pores formed comprise air and wherein the undoped semiconductor layers remain non-porous or substantially non- porous; (l) depositing one or more materials to cover the trench, the side-wall, and side walls of the mesa structure; (m) selectively removing the one or more materials to expose at least a portion of the mesa structure top and optionally a portion of the layer of semiconductor, if covered by the one or more materials; and (n) forming metal contacts on a portion of the mesa structure top and optionally a portion of the layer of semiconductor. Details for making the bottom structure are provided in Section IV below. An exemplary scheme of the above method is shown in Figure 10. The process of Figure 10 starts from structure 400, as shown in Figure 9. Figure 10 shows a process where a masking material is placed on the top layer and protects a region thereunder from ion implantation (530). Annealing is used to selectively restore the conductivity of at least the top layer of n- doped material, as explained in Example 2. Methods for depositing/forming the emissive structure including a multiple quantum well (MQW) are known in the art. For the structures and layers formed or deposited in the methods described above, these can each be independently formed or deposited by art known deposition methods, including metal organic chemical vapor deposition (MOCVD). The selection of precursors, p- or n- dopants, and conditions for forming and doping such structures and layers at defined thicknesses are known in the art. Regarding annealing in step (g), annealing may be performed at any suitable elevated temperature and period of time needed to increase the electrical conductivity of the current spreading layer following ion implantation. In some instances, annealing restores at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or higher of the electrical conductivity of the ion implanted current spreading layer, as compared to the electrical conductivity of the current spreading layer before ion implantation. In some instances, annealing temperatures may be in a range of about 250 ºC to about 450 ºC, as well as sub- ranges or individual temperatures contained therein. Annealing may be applied for a time 33 45662394.1 within a range of about 1 min to 1h or 1 min to 30 mins, as well as sub-ranges or individual times contained therein. In some instances, such as when an n-InP current spreading layer is used, the annealing temperature may be 350 ºC and an annealing time of about 20 mins is applied to restore conductivity to the current spreading layer. Regarding the mesa structure formed in step (h), the dimensions of the mesa structure are selected to be larger than the dimensions of the aperture region. In other words, the mesa structure contains the aperture region therein. The mesa structure can be formed, for example, by wet etching or plasma etching, such as RIE etching. For certain semiconductor materials forming part of the light emitting structure, such as the layers of p-doped second semiconductor and n-doped second semiconductor, there are minimum doping concentrations, as detailed above. For the remaining p- or n-doped layers referenced, the p- or n- doping concentration levels are not particularly restricted. In some instances, the different p- or n- doped layers may each independently have a high doping concentration level of at least about 1 × 10¹⁹ cm^-3 or higher; or in a range of between about 0.1 × 10¹⁹ cm^-3 to 10 × 10²⁰ cm^-3. In some cases, the high doping concentration level may be about 1 × 10¹⁹ cm^-3, 2 × 10¹⁹ cm^-3, 3 × 10¹⁹ cm^-3, 4 × 10¹⁹ cm^-3, 5 × 10¹⁹ cm^-3, 6 × 10¹⁹ cm^-3, 7 × 10¹⁹ cm^-3, 8 × 10¹⁹ cm^-3, 9 × 10¹⁹ cm^-3, or 10 × 10¹⁹ cm^-3. In some other instances, the different p- or n- doped layers may each independently have a moderate doping concentration level of greater than about 1 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 2 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 3 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 4 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, or 5 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3. In some instances, the moderately doped concentration level is in the range of 1 × 10¹⁹ cm^-3 to less than 1 × 10²⁰ cm^-3 or in the range of about 0.5 × 10¹⁹ cm^-3 to 10 × 10¹⁹ cm^-3. In some cases, the moderate doping concentration level may be about 1 × 10¹⁸ cm^-3, 2 × 10¹⁸ cm^-3, 3 × 10¹⁸ cm^-3, 4 × 10¹⁸ cm^-3, 5 × 10¹⁸ cm^-3, 6 × 10¹⁸ cm^-3, 7 × 10¹⁸ cm^-3, 8 × 10¹⁸ cm^-3, 9 × 10¹⁸ cm^-3, or 10 × 10¹⁸ cm^-3. In still other instances, however, the different p- or n- doped layers may each independently have a low doping concentration level of less than about 20 × 10¹⁷ cm^-3 or in the range of between about 0.5 × 10¹⁷ cm^-3 to 10 × 10¹⁷ cm^-3. In some cases, the low doping concentration level may be about 1 × 10¹⁷ cm^-3, 2 × 10¹⁷ cm^-3, 3 × 10¹⁷ cm^-3, 4 × 10¹⁷ cm^-3, 5 × 10¹⁷ cm^-3, 6 × 10¹⁷ cm^-3, 7 × 10¹⁷ cm^-3, 8 × 10¹⁷ cm^-3, 9 × 10¹⁷ cm^-3, or 10 × 10¹⁷ cm^-3. In some instances, the masking material of step (b) is, without limitation, selected from the group consisting of a dielectric (such as silicon dioxide, silicon nitride, aluminum 34 45662394.1 oxide), a metal (such as nickel), and/or a photoresist. Such materials may be formed by various methods, such as plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods known in the art. For the methods described, patterning, etching, or removing of any materials, as needed, can be performed, for example, by any suitable technique, such as wet chemical etching, plasma etching, inductively coupled plasma reactive-ion etching (ICP-RIE). In some instances, for the light-emitting structures, the n-doped first semiconductor layer, p-doped first semiconductor layer, p-doped second semiconductor layer, n-doped second semiconductor, and current spreading layer suitable semiconductor materials are discussed in detail above in Section IIIa above. For the methods described, the layers, structures, and overall resulting light-emitting structures formed according to the method may have any suitable dimension, shape, and thickness. Exemplary and non-limiting thicknesses of the structures and layers of the overall resulting structure are given in Table 2. In some instances of the methods, the one or more materials are selected from the group consisting of silicon dioxide, aluminum oxide, and silicon nitride, spin-on-glass; and/or the one or more materials are organic materials selected from the group consisting of benzocyclobutene (BCB), a polyimide, and a photoresist; and combinations thereof. For the methods described, the deposition of layers of silicon oxide and the one or more materials each may be formed by various methods, such as plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods known in the art. In some instances of the methods, the porosity formed in step (k) is of at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%. In some instances of the methods, step (k) is performed by electrochemical etching in an electrolyte solution and under an applied bias voltage. In certain instances, the electrolyte solution can include halide ions, hydrochloric acid (HCl), sulfuric acid (H2SO4), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)₂, Ca(OH)₂, Sr(OH)₂, NH₄OH, NaCl, NaF, nitric acid (HNO3), organic acids and their salts (such as oxalic acid and citric acid), and mixtures thereof. In some instances of the methods, the metal contacts formed during step (n) are formed of or include one or more metals selected from the group consisting of Ti, Pt, Au, Ge, 35 45662394.1 Ni, Pd, In, and combinations thereof. Methods for forming such metal contacts are known to those of ordinary skill in the art. i. Ion Implantation Regarding the ion implantation of step (c), this can be performed based on the following details. The masking material of step (b) can be formed from the materials specified above. More particularly, the masking material can be said to an ion implant masking material which have any size, area, or shape to controllably select what area(s) of a surface are masked from the ion implant. Such ion implant masks can be formed using several methods. Without limitation, some non-limiting examples include: (1) Photoresist method: A layer of photoresist is spin coated onto a substrate. Then using photolithography, electron beam lithography or stamping techniques, the photoresist mask layer can be pattered into the desired shape. Based on the source of ions and ion energies used, the mask layer can vary from less than about 1 µm to greater than 10 µm, as needed. (2) Hard mask, etching method: A hard mask layer of a material is deposited. This material can be dielectric (such as, for example, silicon dioxide or silicon nitride) or a metal, such as titanium, aluminum, etc. Based on the material, different deposition techniques can be used such as, for example, thermal evaporators, electron beam evaporators, sputters, spin coating, chemical vapor deposition, atomic layer depositions, etc. Then a layer of photoresist can be spin coated and patterned on top of the deposited hard mask layer of material. Then the hard mask layer of material can be etched away, either chemically or physically, in order to transfer the patterns from the photoresist to the underlying layer of the material. (3) Hard mask, liftoff method: Similar to the above technique (hard mask, etching method) but carried out in reverse order. First, a layer of photoresist is spin coated and then patterned. Then, a hard mask layer is deposited on top of the photoresist using one of the techniques previously described in (2). The photoresist is then etched away causing the lifting off of regions within the hard mask layer thus transferring the pattern to the hard mask layer. In the ion implanting step, ion implants are made only in the exposed areas of layer(s) which are not masked. The ion implant ions can come from various ion sources. Many ion species and sources can be used, such as aluminum, gold, nitrogen, hydrogen, helium, carbon, 36 45662394.1 oxygen, titanium, iron, to modify (i.e., damage/reduce) the electrical conductivity of the ion implanted areas or regions. In some instances, the ion may be chosen on the basis of higher atomic mass. For example, aluminum ions may be selected due to their greater atomic mass compared to hydrogen ions. The selected energy depends on the depth required of the ion implant. These energies can range from less than about 10 keV to greater than about 1 MeV to control implant at depths in a range from less than about 10 nm up to greater than about 1 µm, about 10 nm to about 750 nm, about 10 nm to about 500 nm, about 10 nm to about 250 nm, about 10 nm to about 100 nm, or any suitable sub-range or individual depth value within those ranges disclosed here. The ion dosage can also be used to control the number of implanted ions and therefore the modification in the electrical conductivity. Typical ion implant dosages can range from, but not are limited to about 10¹² to 10¹⁶ cm^-3, based on the ion species and desired depth. The energy of the ion implant source exposure can be used to control the depth of the ion implants made into a layer(s). b. Optoelectronic Devices Containing an Aperture Region formed by Ion Implantation The light-emitting structures containing a DBR and an aperture region, as described above, can be used in the fabrication of optoelectronic devices having an aperture region therein. In some instances, an optoelectronic device can include: a light-emitting structure including a bottom distributed Bragg reflector mirror and an aperture region; a top distributed Bragg reflector mirror; and metal contacts. For the optoelectronic devices, the light-emitting structure includes a bottom distributed Bragg reflector (BDR) mirror and an aperture region, as described above. A non- limiting example of an optoelectronic device, such as a VCSEL, is shown in Figure 13. In some instances, the top distributed Bragg reflector is formed of or includes alternating layers of any one of a-Si/SiO2, TiO2/SiO2, Ta2O5/SiO2, Nb2O5/SiO2, ZnSe/SiO2, a- Si/Al₂O₃, a-Si/MgF, ZnS/MgF, a-Si/CaF₂, or combinations thereof. In some instances, the metal contacts are formed of or include one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof. 37 45662394.1 In some instances, the optoelectronic device is a vertical cavity surface emitting laser (VCSEL). In some cases, the vertical cavity surface emitting laser operates at room temperature (about 25 ºC) and in a continuous-wave mode. In some other cases, the vertical cavity surface emitting laser operates at temperatures below about 0 ºC, above about 25 ºC, or above about 85 ºC. In still other instances, the vertical cavity surface emitting laser can operate in a pulse-mode. The vertical cavity surface emitting laser, which includes an aperture region, can emit in the infrared and/or red wavelength region depending on the selection of the emissive structure material. In some cases, the vertical cavity surface emitting laser has a power conversion efficiency of at least about 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 7.5%, or 10%. A non-limiting method for making an optoelectronic device including an aperture region, can include the steps of: (a’) providing or forming a light-emitting structure including a bottom distributed Bragg reflector mirror and an aperture region; (b’) providing or forming a top distributed Bragg reflector mirror on the light- emitting structure; and (c’) providing or forming metal contacts on the optoelectronic device. For the optoelectronic devices formed according to the above method, the light- emitting structure includes a bottom distributed Bragg reflector (BDR) mirror and an aperture region, as described above. A non-limiting scheme of a process of fabricating an optoelectronic device, such as a VCSEL, is shown in Figure 14. In such methods, the top distributed Bragg reflector mirror of step (b’) can include alternating layers of any one of a-Si/SiO₂, TiO₂/SiO₂, Ta₂O₅/SiO₂, Nb₂O₅/SiO₂, ZnSe/SiO₂, a- Si/Al2O3, a-Si/MgF, ZnS/MgF, a-Si/CaF2, or combinations thereof. Methods of making such DBRs, having the aforementioned alternating layers, are known in the art. The number of alternating layers in such DBRs can depend on the materials selected. The top DBR mirror can be deposited by means known in the art and may include annealing to increase the reflectivity. In some instances, the top DBR mirror has a reflectivity of at least about 97% or higher. For the methods described above, the metal contacts of step (c’) can be formed of or include one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof. 38 45662394.1 For any of the methods described in Section III it is understood that the order of certain steps may be interchangeable, as permitted and without negatively impacting the structures or devices formed. For instance, steps (b’) and (c’) of the method of making an optoelectronic device may be performed in any suitable order. IV. Bottom Structure and Methods of Making and Porosifying Thereof The bottom structure of the various structures described, such as semiconductor structures and light-emitting structures, as well as optoelectronic devices described in Sections II and III above are described in detail below. For semiconductor structures, 100, 100’, 100”’, 100””, 100””’, 10, and 400, each include a bottom structure having alternating layers of doped and undoped (or low doped) semiconductor layers on a semiconductor substrate. The semiconductor substrate can be made, for example, of indium phosphide (InP), gallium arsenide (GaAs), or gallium antimonide (GaSb). In these particular structures, the n-doped semiconductor layers have not yet been subjected to a selective porosifying treatment, such as by an electrochemical etching process, and remain intact. In one instance, a non-limiting exemplary bottom structure contains a plurality of undoped or low doped (see below) semiconductor layers, which may be made of indium phosphide, gallium arsenide, or gallium antimonide layers, where at least one layer of an n- doped semiconductor is present between at least two layers of undoped or low doped semiconductor and can be porosified (or electropolished) due to electrochemical etching. The bottom structures include alternating layers of semiconductor layer on a semiconductor substrate. In some instances, the semiconductor substrate is chosen and a suitable semiconductor material, which is lattice-matched to the semiconductor substrate, is chosen to form alternating n-doped and undoped (or low doped) semiconductor layers. For instance, the semiconductor substrate of the bottom structure may be made of any one of InP, GaAs, or GaSb. It is understood that the semiconductor substrate of the bottom structure and the alternating do not necessarily need to be made of the same material, but should preferably be made of lattice-matched materials, which the skilled person is able to select. The dimensions of semiconductor substate and layer(s), whether doped or undoped (or low doped), thereon can be of any suitable dimensions, area, or shape for a specific application. Typically, the semiconductor substrate and all layers thereon are of equal dimension, area, 39 45662394.1 and shape. In some instances, the overall bottom structure has dimensions (i.e., length and width) of or up to about 100 microns by 100 microns, as well as sub-ranges contained within. In some instances, the alternating layers of the bottom structure include or are made of a binary semiconductor material selected from, but not limited, to the group consisting of indium phosphide, gallium arsenide, and gallium antimonide, and are lattice-matched to the semiconductor substrate. In some other instances, the alternating layers of the bottom structure include or are made of a ternary semiconductor material that is lattice-matched to the semiconductor substrate. In still other instances, the alternating layers of the bottom structure include or are made of a quaternary semiconductor material that is lattice-matched to the semiconductor substrate. In some instances, non-limiting examples of binary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InP, GaAs, GaSb, and AlAs. In some instances, non-limiting examples ternary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some instances, quaternary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It is understood that the selection of any binary, ternary, or quaternary semiconductor material for use in the one or more layers, as named above, is preferably based on the semiconductor materials of the layers of a given structure being lattice-matched to the selected semiconductor substrate, which may be made of any one of InP, GaAs, or GaSb. The skilled person would be able to select the appropriate semiconductor material for each layer which is lattice-matched to the semiconductor substrate, as well as the desired doping type and doping concentration level, as detailed above. In some instances, the bottom structure includes at least 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, or more pairs of n-doped and undoped (or low doped) semiconductor layers which are in contact at least prior to electrochemical etching. The person of ordinary skill in the art is familiar with methods for fabricating such a bottom structure, such as by epitaxially or homoepitaxially art known methods, such as metal organic chemical vapor deposition (MOCVD), molecular-beam epitaxy (MBE), or liquid 40 45662394.1 phase epitaxy (LPE), and using known reactants, dopants, and precursors to afford doped and undoped (or low doped) semiconductor layers. As shown in Figure 4, the bottom structure can be subjected to electrochemical (EC) etching conditions wherein the layers of n-doped semiconductor present are selectively porosified and a plurality of pores are formed within the n-doped semiconductor layers that are confined by and adjacent to undoped or low n-doped semiconductor layers which remain non-porous or substantially non-porous under EC conditions (where “substantially non- porous” refers to having a degree of porosity of less than 25%, 20%, 15%, 10%, 5%, 4%, 3%, 2%, or 1% in the undoped (or low doped) layers). In some other instances, the plurality of pores are horizontally aligned (i.e., parallel) with a plane direction of the n-doped semiconductor layer. In certain instances, the bottom structure is made of a single type of doped and undoped (or low doped) semiconductor. For example, the bottom structure can made of all indium phosphide layers, all gallium arsenide layers, or all gallium antimonide layers, which alternate in doping as explained. However, mixtures of different types of materials are possible. N-doped semiconductor layers, which are sufficiently doped, can be selectively electrochemically etched, as described below, to selectively porosify the doped semiconductor layer or to selectively electropolish (i.e., remove) the doped semiconductor layers or regions within. The undoped or low doped semiconductor layers are generally not electrochemically etched. The conditions that control the degree of porosification or that permit electropolishing are described in further detail below. Porosification and electropolishing need not remove the entirety of the n-doped semiconductor layer, where only a portion or region therein may be porosified or electropolished in a given EC process. Porosification or electropolishing forms structures which contain (air) pores or channels that can form in a horizontal direction due to selective lateral etching which proceeds from one or more side walls of the bottom structure, when EC etched. Electrochemical etching requires that n-doped semiconductor layers be doped with an n-type dopant. Accordingly, n-doped semiconductor layers, as present, are formed during deposition/formation. Exemplary dopants can include, but are not limited to, n-type Ge and Si dopants. Such dopant sources can include, for example, silane (SiH4), germane (GeH4), and isobutylgermane (IBGe). For n-type doped layers, the n-type doping concentration can be 41 45662394.1 uniform across the entirety of the layer or the doping concentration may form a gradient (i.e., a layer having a graded dopant concentration across an axis of the layer, such width). The doping concentration is considered high at doping concentration levels of at least about 1 × 10¹⁹ cm^-3 or higher; or is the range of between about 0.1 × 10¹⁹ cm^-3 to 10 × 10²⁰ cm^-3. In some cases, the high doping concentration level may be about 1 × 10¹⁹ cm^-3, 2 × 10¹⁹ cm^-3, 3 × 10¹⁹ cm^-3, 4 × 10¹⁹ cm^-3, 5 × 10¹⁹ cm^-3, 6 × 10¹⁹ cm^-3, 7 × 10¹⁹ cm^-3, 8 × 10¹⁹ cm^-3, 9 × 10¹⁹ cm^-3, or 10 × 10¹⁹ cm^-3. The doping concentration is considered to be moderate at doping concentration levels of greater than about 1 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 2 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 3 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, 4 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3, or 5 × 10¹⁸ cm^-3 to less than 1 × 10²⁰ cm^-3. In some instances, the moderately doped concentration level is in the range of 1 × 10¹⁹ cm^-3 to less than 1 × 10²⁰ cm- 3 or in the range of about 0.5 × 10¹⁹ cm^-3 to 10 × 10¹⁹ cm^-3. In some cases, the moderate doping concentration level may be about 1 × 10¹⁸ cm^-3, 2 × 10¹⁸ cm^-3, 3 × 10¹⁸ cm^-3, 4 × 10¹⁸ cm^-3, 5 × 10¹⁸ cm^-3, 6 × 10¹⁸ cm^-3, 7 × 10¹⁸ cm^-3, 8 × 10¹⁸ cm^-3, 9 × 10¹⁸ cm^-3, or 10 × 10¹⁸ cm- 3. Moderate to high n-type doping is subject to the electrochemical etching process and results in controlled porosification and/or electropolishing of the doped layers, depending on the conditions used during the electrochemical etching process. As noted above, the bottom structure contains layers of undoped semiconductor which are not affected (porosified or etched) when the bottom structure is electrochemically etched. In some instances, however, the bottom structure may contain layers of low doped or lowly doped semiconductor where the doping concentration is considered to be low at doping concentration levels of less than about 20 × 10¹⁷ cm^-3 or in the range of between about 0.5 × 10¹⁷ cm^-3 to 10 × 10¹⁷ cm^-3. In some cases, the moderate doping concentration level may be about 1 × 10¹⁷ cm^-3, 2 × 10¹⁷ cm^-3, 3 × 10¹⁷ cm^-3, 4 × 10¹⁷ cm^-3, 5 × 10¹⁷ cm^-3, 6 × 10¹⁷ cm^-3, 7 × 10¹⁷ cm^-3, 8 × 10¹⁷ cm^-3, 9 × 10¹⁷ cm^-3, or 10 × 10¹⁷ cm^-3. The thicknesses of any one of the n-doped or undoped (low doped) layers, prior to electrochemical etching, may each independently range in between about 50 to 500 nm (and subranges or individual thicknesses disclosed therein). In some instances, the total thickness of the bottom structure, before or after electrochemical etching, may range from between about 600 nm to about 8,000 nm or 600 nm to about 6,000 nm, and sub-ranges within. The dimensions and/or shape of the layers or semiconductor substrate may be of any suitable shape/dimension required for an application. In some instances, for the bottom structures, the 42 45662394.1 n-doped semiconductor layers present within the alternating layers each have identical or substantially identical thicknesses to each other; and/or the undoped (or low doped) semiconductor layers present within the alternating layers each have identical or substantially identical thicknesses to each other. “Substantially identical,” as used herein refers to each of the particular layers, as described in the above instances, each having a thickness which differs by less than about 5%, 4%, 3%, 2%, 1%, or lower to the thickness of all the other similar layers present. It is possible for the n-doped and undoped (or low doped) semiconductor layers to have the same or different thicknesses. Following electrochemical etching, in the bottom structures the undoped or low doped semiconductor layers are typically unaffected (i.e., non-porosified or substantially non- porosified (where “substantially non-porosified” refers to having a degree of porosity of less than 25%, 20, 15%, 10%, 10%, 5%, 4%, 3%, 2%, or 1% in the undoped (or low doped) semiconductor layers). In some instances of the method, unintentional porosification of undoped (or lowly doped) semiconductor layers can occur, where even lowly n-doped semiconductor layers can be porosified during EC etching. Following electrochemical etching, in the bottom structures the n-doped semiconductor layers are porosified, as compared to prior to electrochemical etching. Porosification can be high where the layer contains at least one portion which has between about 10% and 90%, or greater porosity. In some instances, the porosity is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90% or greater. Incorporation of a low index material, such as air, into layer (or portion thereof) by porosification has the effect of lowering the refractive index, as compared to the bulk semiconductor layer before porosification. For the n-doped semiconductor layers, electrochemical etching can result in different degrees of porosities and pore morphologies by changing the type and concentration of electrolyte, n-doping concentration of the layers, and applied bias voltage, as discussed in detail below. Electrochemical etching can be used to selectively create lateral or horizontal pores in the porosified n-doped semiconductor layers of the bottom structure. These selectively form from side surfaces of the multilayer structure. Without limitation, lateral or horizontal pores formed during the electrochemical etching process may be of any suitable length. Porosified semiconductor layers (or regions therein) contained within the multilayer structures are 43 45662394.1 preferably nanoporous but may be further defined as being micro-, meso-, or macro-porous, or any combination thereof. The porosified layer or region therein may be further categorized as microporous (d < 2 nm), mesoporous (2 nm < d < 50 nm), or macroporous (d > 50 nm); where d is the average pore diameter. The morphology of the pores contained within the layer or region therein can also be classified as circular, semicircular, ellipsoidal, or a combination thereof. The pores may have an average size (i.e., length) of between about 5 to 100 nm, 5 to 75 nm, 5 to 50 nm, or 5 to 25 nm. In some instances, the average pore size is about 5, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 nm or greater. In some instances, based on the original doping concentration, the etchant used, and the applied voltage during the electrochemical porosification process, the average size of the pores can range from between less than about 20 nm to greater than 50 nm. The spacing between any adjacent pores (which is also defines a measure of wall thickness of the pores) can range from between about 1 to 50 nm, 5 to 50 nm, 5 to 40 nm, 5 to 30 nm, 5 to 25 nm, 5 to 20 nm, 5 to 15 nm, or 5 to 10 nm. In a given bottom structure, all or a portion of the doped semiconductor layer may be porosified during electrochemical etching. In some instances, electrochemical etching proceeds from a side wall and the extent of porosification of a layer is at least about 10, 20, 30, 40, 50, 60, 80, or 90% of the longest planar dimension of the doped layers. In some other instances, where electropolishing occurs, the extent of electropolishing of a layer is at least about 10, 20, 30, 40, 50, 60, 80, or 90% of the longest planar dimension of the doped layers. Porosification may occur uniformly or non-uniformly within each doped layer during the electrochemical etching process. Electropolishing may occur uniformly or non-uniformly within each doped layer during the electrochemical etching process. As noted above, in some instances the n-doped semiconductor layer is electropolished away (completely removed) which leaves little or no material between the undoped (or low doped) layers, where the doped semiconductor material used to be. The dimensions of the void space formed due to electropolishing depends on the dimensions of the doped semiconductor layer and the extent of material that was electropolished away. Electropolishing can, in some instances, create lateral or horizontal (air) pores or channels between the undoped layers where the doped material has been removed. a. Optical Properties of Bottom Structure Selective incorporation of a low index material, such as air, into selected regions or layers of the bottom structures by electrochemical etching has the effect of lowering the 44 45662394.1 refractive index, as compared to the bulk semiconductor making up the structure. Thus, it is possible to tune the refractive index of the porosified regions within the bottom structure selectively. For example, prior to electrochemical etching, in bottom structures formed of InP each of the layers has an index of refraction of about 3.2. Electrochemical etching selectively porosifies or may completely electropolish n-doped InP layers which lowers the index of refraction below 3.2. In some instances, the index of refraction of porosified InP layers is about 1.5 to 2.7. When the InP layers are electropolished away the index of refraction is about 1. Consequently, the refractive index contrast (Δn) between the InP layers, after electrochemical etching, may be in the range of about 0.1 to about 2. In some instances, the refractive index contrast (Δn) is at least about 1.1, 1.2, 1.3, 1.4, or 1.5. In still other instances, the refractive index contrast ratio (Δn) is at least about 1.5. Prior to electrochemical etching, in bottom structures formed of GaAs each of the layers has an index of refraction of about 3.95. Electrochemical etching, selectively porosifies or may completely electropolish doped InP layers which lower the index of refraction below 3.95. In some instances, the index of refraction of porosified GaAs layers is about 1.5 to 3.4. When the GaAs layers are electropolished away the index of refraction is about 1. Consequently, the refractive index contrast (Δn) between the GaAs layers, after electrochemical etching, may be in the range of about 0.1 to about 2.5. In some instances, the refractive index contrast (Δn) is at least about 1.1, 1.2, 1.3, 1.4, or 1.5. In still other instances, the refractive index contrast ratio (Δn) is at least about 1.5. Prior to electrochemical etching, in bottom structures formed of GaSb each of the layers has an index of refraction of about 3.85. Electrochemical etching, selectively porosifies or may completely electropolish doped InP layers which lower the index of refraction below 3.85. In some instances, the index of refraction of porosified GaAs layers is about 1.2 to 3.4. When the GaAs layers are electropolished away the index of refraction is about 1. Consequently, the refractive index contrast (Δn) between the GaAs layers, after electrochemical etching, may be in the range of about 0.1 to about 2. In some instances, the refractive index contrast (Δn) is at least about 1.1, 1.2, 1.3, 1.4, or 1.5. In still other instances, the refractive index contrast ratio (Δn) is at least about 1.5. The bottom structures can act as a mirror and can demonstrate a reflectance of at least about 99%, 99.1%, 99.2%, 99.3%, 99.4%, 99.5%, 99.6%, 99.7%, 99.8%, or 99.9%. 45 45662394.1 b. Methods of Electrochemically (EC) Etching the Bottom Structures As explained above, methods of forming the alternating layers of doped and undoped (or low doped) semiconductor layers are known in the art. Nevertheless, a non-limiting example of a method of forming a bottom structure, can include the steps of: (a) forming a first layer of undoped or low doped semiconductor above a semiconductor substrate; (b) depositing a second layer of an n-doped semiconductor over the first layer; (c) depositing a third layer of undoped or low doped semiconductor above the second layer; (d) optionally repeating steps (b) and (c) to form additional alternating layers of the n- doped and the undoped or low doped semiconductor. The bottom structures, as formed, can be used in the fabrication of other structures, such as shown in Figures 2, 4, and 10. In such processes, they can be subjected to electrochemical (EC) etching, as shown in Figures 4 and 10. Electrochemical (EC) etching of n-doped semiconductor layers can be carried out in the presence of an electrolyte and under an applied bias voltage to selectively porosify or electropolish at least a portion of the n-doped semiconductor present; Porosification and/or electropolishing which occurs during the electrochemical (EC) etching process can be controlled based on the concentration of electrolyte, doping concentration, and applied bias voltage (as discussed below). The applied bias voltage is typically a positive voltage in the range of about 0.1 to 10 V, 1.0 to 5V, or 1.0 to 2.5V. In some instances, based on the original doping concentration and the type of etchant used, the applied bias ranges from less than about 1V to at least about 10V, or greater. In some instances, porosity can be selectively minimized when lower relative doping concentration(s) are used, where in one non-limiting instance, a doping concentration of 5 × 10¹⁸ cm^-3 in a sample produces a lower porosity as compared to a doping concentration of 2 × 10¹⁹ cm^-3 when both are etched under the same conditions. This can be generally expected for all relative concentration differences, where the higher doping concentration will be subject to greater porosification when compared to a lower relative doping concentration, all other electrochemical etching parameters being constant. In some instances, depending on concentration of electrolyte, doping concentration, and selection of applied bias voltage applied voltage(s), electrochemical etching conditions may selectively and controllably result 46 45662394.1 in only porosification (having between about 30% and 90%, or greater porosity introduced) or complete electropolishing (i.e., total or near total removal (i.e., greater than 95%, 96%, 97%, 98%, or 99% removal of doped material). The electric field direction during the EC etching process can be used to control the direction of the etching direction and thereby control the direction of the pores etched into the n-doped semiconductor layer. For example, the EC etching direction may be a function and determined by the electric field direction. The EC etching preferably produces a lateral etching direction. The rate of lateral etching can be about 0.1 μm/min, 0.2 μm/min, 0.3 μm/min, 0.4 μm/min, 0.5 μm/min, 0.6 μm/min, 0.7 μm/min, 0.8 μm/min, 0.9 μm/min, 1 μm/min, 2 μm/min, 3 μm/min, 4 μm/min, 5 μm/min, 6 μm/min, 7 μm/min, 8 μm/min, 9 μm/min, 10 μm/min, 20 μm/min, 30 μm/min, 40 μm/min, or 50 μm/min. The EC etching can be carried out under an applied bias voltage from about 1 min to 24 hours, 1 min to 12 hours, 1 min to 6 hours, 1 min to 4 hours, 1 min to 2 hours, 1 min to 1 hour, or 1 min to 30 minutes. In some instances, the EC etching is carried out under an applied bias voltage for at least about 5 min, 10 min, 15 min, 20 min, 25 min, 30 min, 35 min, 40 min, 45 min, 50 min, 55 min, 60 min, 2 hours, 3 hours, 4 hours, 5 hours, 6 hours, 10, hours, 15 hours, 20 hours, 24 hours, or greater. The EC etching can be carried out under an applied bias voltage at room temperature or at a temperature in the range of about 10 ºC to about 50 ºC. The EC etching can be carried out under an applied bias voltage under ambient conditions or optionally under an inert atmosphere (such as of nitrogen or argon). The EC etching can be carried out in different types and concentrations of a high conductivity electrolyte (either salt or acid). Exemplary high conductivity electrolytes can include, but are not limited to halide ions (fluoride, chloride, bromide, iodide), hydrochloric acid (HCl), sulfuric acid (H2SO4), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)2, Ca(OH)2, Sr(OH)₂, NH₄OH, NaCl, NaF, nitric acid (HNO₃), organic acids and their salts (such as oxalic acid and citric acid), and mixtures thereof. The concentration of the electrolyte in the high conductivity electrolyte solutions, typically aqueous, can be in the range of between about 0.1 to 10M. In some other instances, concentration of the electrolyte in the high conductivity electrolyte solutions, typically aqueous, can be defined as a percentage (volume/volume) of the electrolyte to solvent(s), such as water, in which it is dissolved in and can be in the range of between about 0.1 to 30% by volume. In still other instances, concentration of the electrolyte in the high conductivity electrolyte solutions, typically 47 45662394.1 aqueous, can be defined as a percentage (weight/volume) of the electrolyte to solvent(s), such as water, in which it is dissolved in and can be in the range of between about 0.1 to 30% by weight. The electrolytes listed above normally do not etch semiconductors, such as InP, GaAs, or GaSb, at room temperature, but can etch semiconductors, such as InP, GaAs, or GaSb, under the electrochemical anodic conditions applied. It is believed that electrochemical etching, as described herein, proceeds from the edge of exposed sidewall(s), such as in a lateral direction to preferentially form horizontal pores. Lateral etching causes porosification producing pores, typically nanopores, to be formed horizontally or predominantly horizontally within a doped layer. The bottom structure has a vertical axis from the lowest to the top-most layer where planar layers of alternating doped and undoped (or lowly doped) semiconductor exist. When EC etching is induced, porosification of n-doped layers occurs perpendicular or predominantly perpendicularly to the vertical axis. Predominantly perpendicular, as used herein, refers to pores that, on average, are oriented within about 20, 15, 10, or 5 degrees of the perpendicular/horizontal plane to the vertical axis. In other words, porosification occurs along or predominantly along a horizontal direction that is parallel or near parallel to the planar direction of doped layers. For the bottom structures, following electrochemical etching, there may be little, if any, pores that are vertically aligned with the vertical axis. Pores need not be aligned with the vertical axis of the bottom structure. In some instances, no vertically aligned pores are formed in the doped layers and only horizontal pores are formed during electrochemical etching. In some instances, substantially non-porosified undoped (or lowly doped) InP, GaAs, or GaSb also have nanopores formed along the [111] crystallographic direction, which are at an angle of 45 degree inclined from vertical [001] and horizontal directions. In some other instances, it may be the said that macroscopically nanopores formed in n-doped semiconductor laterally propagate during porosification, while microscopically nanopore generation can occur along a specific crystallographic directions (such as, +45º, -45º inclined from the doped layer surface). Electrochemical etching generally consists of oxide formation and removal steps (Quill, N., et al. (2013). ECS transactions, 58(8), 25-38). It is believed that the presence of free holes at the semiconductor/electrolyte interface are important for oxidation, and oxides formed can be easily dissolved in the various electrolytes. The free holes are supplied by electric-field assisted tunneling and their amount mainly depends on anodic bias and doping concentration. 48 45662394.1 In some instances, electrochemical (EC) etching conditions result in no EC etching at low anodic bias and/or low doping concentrations (low doping is described above), whereas electropolishing (i.e., complete etching) is observed at large bias and/or high n-doping concentrations. Porosification is observed at intermediate bias and/or doping concentrations. V. Methods of Using the Structures and Optoelectronic Devices The various structures and optoelectronic devices, such as light-emitting structure containing DBR mirrors and VCSELs, described herein can be used in various applications including electronic, photonic, and optoelectronic applications. Without limitation, exemplary applications can include: low-power on-chip laser sources for photonic-electronic integrated circuits; eye-safe optical sensing systems based on VCSELs and VCSEL arrays; low-cost optical links based on single-mode fiber for distances exceeding 1 km; free-space (last mile or indoor personal network) optical communication for 6G mobile and optical wireless networks; Internet of Things; low-cost light detection and ranging systems; and biomedical sensing and diagnostic devices and systems. In particular, the VCSELs described can provide long-wavelength emission (i.e., emitting at red, near red, or infrared wavelengths from 900 to 3000 nm, as well as subranges and individual wavelengths contained therein). In certain instances,. the VCSELs described can emit at a particular wavelength or wavelength range, such as about 650 nm, about 850 nm to about 940 nm, about 1300 nm to about 1600 nm, or about 2000 nm to about 2400 nm. In some instances, the VCSELs can emit in the red wavelength range of the spectrum. VCSELs, in general, find important applications in various fields including information processing, micro-display, pico-projection, laser headlamps, high-resolution printing, biophotonics, spectroscopic probing, and atomic clocks. The various VCSELs described can provide optical and electrical performance with advantages compared to more commonly used edge emitting laser diodes (EELDs), such as superior beam quality, compact form factor, low operating power, cost-effective wafer-level testing, higher yield and lower cost in manufacturing. The present invention will be further understood by reference to the following non- limiting examples. 45662394.1 Example 1: Nanoporous Vertical Cavity Surface Emitting Laser (VCSEL) having a Buried Tunnel Junction (BTJ) Materials and Methods: A semiconductor structure 100 having a buried tunnel junction (BTJ), as shown in Figure 1, was prepared starting from an epitaxially grown structure 10, as shown in Figure 2 (top row, left most). All the layers were grown planarly and continuously. From bottom to top, structure 10 consists of six portions: (1) a stack 110 of 12 pairs of alternating layers of n⁺-indium phosphide (InP) (darker bands, doping concentration: 5 × 10¹⁸ cm^-3) and n--InP (lighter bands, lightly doped, doping concentration: < 5 × 10¹⁸ cm^-3), where the n⁺-InP can be porosified by electrochemical etching to form nanoporous (NP)-InP layers with a low refractive index (lower than the refractive index of the layer before porosification); (2) a layer 120 of a thick n-InP layer (light gray, doping concentration: 5 x 10¹⁷ cm^-3) of at least about 200 nm, which constitutes the majority volume of the structure; (3) an emissive structure 130 of InAlGaAs which provides an active region with a targeted emission wavelength of 1550 nm; (4) a layer 140 of p-InP (doping concentration: 5 × 10¹⁷ cm^-3); (5) a layer 150 of p⁺⁺- InGaAs (doping concentration > 1 × 10¹⁹ cm^-3); and (6) a layer 160 of n⁺⁺-InGaAs (black, doping concentration > 1 × 10¹⁹ cm^-3). Structure 10 was grown by metal organic chemical vapor deposition (MOCVD). Semiconductor structure 100, as shown in Figure 1, includes from bottom to top: (1) a stack 110 of 12 pairs of alternating layers of n⁺-indium phosphide (InP) and n--InP; (2) a layer 120 of a thick n-InP layer of at least about 200 nm; (3) an emissive structure 130 of InAlGaAs, which provides an active region with a targeted emission wavelength of 1550 nm; (4) a layer 140 of p-InP; (5) an buried tunnel junction formed of: a layer 150 of p⁺⁺-InGaAs and a layer 160 of n⁺⁺-InGaAs; wherein (6) a current spreading layer 170 encapsulates the buried tunnel junction; and optionally (7) there is a non-planarity in the surface of the current spreading layer, which forms a step feature (180) and can provide an optical confinement effect. Starting from structure 10, a non-limiting schematic of the process for creating the BTJ structure is demonstrated in Figure 2. The process proceeded by patterning a masking material on the top surface of structure 10 (Figure 2, top row, center). Next, wet etching by a mixture of citric acid and hydrogen peroxide was performed to remove portions of layers 150 and 160 50 45662394.1 outside the masked region (Figure 2, top row, right most). After removing the mask (Figure 2, bottom row, left most), a layer of n-InP (layer 170 in Figure 1) was regrown to bury the patterned tunnel junction underneath (Figure 2, bottom row, right most). At the end of the process, a tunnel junction was formed of layers 150 (p⁺⁺-InGaAs) and 160 (n⁺⁺-InGaAs), as in Figure 1, which were confined to a small region, and were surrounded with n-InP (layer 170). It is believed that the BTJ structure formed provides for: 1) current which is mainly injected through the region with the BTJ (this region may alternatively be called an aperture region). In optoelectronic devices, only the region with carrier injection emits light and provides optical gain for lasing. Thus, the confined current injection is believed to lead to gain guiding for optical confinement; and 2) after regrowth to form layer 170, the process results in a top surface in semiconductor structure 100 which is not planarized. In other words, the surface over the BTJ or aperture region is higher than the rest of the surrounding surface of layer 170 and can be viewed as a step feature 180 present on the structure, which provides an optical confinement effect to optoelectronic devices formed using structure 100. A light-emitting structure 200 including a Distributed Bragg Reflector (DBR) mirror therein, as shown in Figure 3, was fabricated starting from semiconductor structure 100, discussed above. The fabrication processes to provide the light-emitting structure with a DBR therein are shown in Figure 3. From semiconductor structure 100 (Figure 4, top row, left most) a mesa structure was formed through an etching process, which can be either a wet etching (dilute HCl followed by citric acid and H2O2) or a dry etching, (Figure 4, top row, center), where the bottom of the mesa structure was at layer 120. A layer of plasma-enhanced chemical vapor deposition (PECVD) deposited SiO2 (30) was formed and patterned to cover most of the top surface, except for the left portion (Figure 4, top row, right most). In other words, SiO230 was deposited over the entire mesa structure and only an edge portion of the top surface was not covered by SiO₂30 at a side-wall. The purpose of SiO₂30 was to: 1) serve as a dry etching mask for the next step in the process; and 2) also to protect the structure in the mesa from being attacked during the electro-chemical (EC) etching process which followed. Next, a deep dry etching (8sccm CH4, 4sccm H2, 10sccm Cl2 with 100W HF power and 1200W ICP power) was performed using SiO₂30 as the mask to form a trench which reached the bottom of stack 110 (Figure 4, middle row, left most). Next, the structure (anode) and a platinum (Pt) wire/plate (cathode) were immersed into an electrolyte for electrochemical (EC) etching (Figure 4, middle row, center). By applying a forward bias to 51 45662394.1 the structure, EC etching initiated from the trench sidewall. The porosified regions (dark regions) expanded laterally to cover the entire BTJ or aperture region above. It is noted that porosification was confined only in the n+-InP layers of stack 110, leaving the lightly doped InP layers intact (un-porosified). The selectivity between porosified and un-porosified regions was achieved through the difference in the doping concentration. As a result of porosification, n⁺-InP layers were filled with air, and provided a lower refractive index, as compared to the lightly doped InP layers. An alternating structure with high- and low-index layers forms a mirror in the DBR structure, which is used to form a VCSEL. Following selective porosification of the stack, another layer of PECVD SiO2 (40) was deposited on the porosified sample (Figure 4, middle row, right most). The purpose of layer 40 was to cover and protect the entrance of the porosified stack, the nanoporous (NP)- InP. However, because PECVD SiO₂ is known to cause leakage current especially through the mesa sidewall (Jpn. J. Appl. Phys.381195 (1999)), the SiO2 of 30 and 40 present on the mesa structure were removed (Figure 4, bottom row, left most) with a buffered oxide etchant and a layer of Al2O3 (50) was deposited thereon (Figure 4, bottom row, middle) by atomic layer deposition (ALD). Finally, a portion of the Al₂O₃ (50) was removed to expose the top of the mesa structure and at least a portion of the top surface of layer 120 (Figure 4, bottom row, right most) to provide a light-emitting structure including a DBR mirror therein. A light-emitting structure 200 including a DBR mirror therein is shown in detail in Figure 3. From bottom to top, the light-emitting structure 200 consists of: (1) a bottom structure 210 formed of a stack which consists of 12 pairs of alternating layers of n⁺-InP and n--InP, where the n⁺-InP are selectively porosified by electrochemical etching, as shown by dark bands; (2) a layer 220 of a thick n-InP layer of at least about 200 nm; (3) a mesa structure which contains from bottom to top a layer 230 of InAlGaAs, a layer 240 of p- InAlAs; a BJT formed of a layer 250 of p⁺⁺-InAlAs and a layer 260 of n⁺⁺-InP; and a current spreading layer 270 of n-InP on top, wherein the top surface of current spreading layer 270 includes a step feature 280. Additional layers shown in Figure 3 include an Al₂O₃ layer (295) and a layer of SiO2 (290) which are present due to the fabrication process but are not needed for function of the light-emitting or DBR contained therein. Light-emitting structure 200, containing a DBR mirror therein, was used to form a VCSEL 300, as shown in Figure 5. Light-emitting structure 200, which contains a DBR, forms the bottom DBR mirror of the VCSEL and a top dielectric DBR mirror 310 is present 52 45662394.1 on the top of the mesa structure, as well as metal contacts 320, as shown in Figure 5. The process to form VCSEL 300 is shown in Figure 6 and proceeds by forming the top DBR 310 and metal contacts 320 on the light-emitting structure 200. The top DBR mirror was a lift-off of sputtering-deposited dielectric DBR (patterning photoresist, depositing DBR blanketly on the surface, and lift-off DBR on the photoresist using solvent). As a result, the top DBR only remained in the previous PR opening region. The top DBR mirror can also be formed through sputtering deposition blanketly followed by patterned dry etching to remove DBR outside the intended region. Metal contacts 320 were formed through lift-off of metal stacks deposited by e-beam evaporation. Characterization and Discussion of Light-Emitting Structure and VCSEL having a buried tunnel junction (BTJ): To assure the current aperture effect of the BTJ structure, the current-voltage (I-V) characteristics of a light-emitting structure containing a DBR mirror having a BTJ (diameter is 10 μm) and a control light-emitting structure containing a DBR mirror without a BTJ were compared. Both devices were measured before the deposition of a top dielectric DBR. The device without a BTJ was used to simulate the structure outside the aperture region. The I-V curves of these two devices are summarized in Figure 7 which showed that the current at 2V in the device with a BTJ (solid line) was 5 times higher than the current in the device without a BTJ (dashed line). This indicated that current was mainly confined in the BTJ or aperture region in the light-emitting structure 200 containing a DBR mirror. It was also noted that the current in the device without a BTJ was much higher than the literature reported value (Jpn. J. Appl. Phys. Vol.39 (2000)), which was likely due to the punch-through of p-InP layer. When a large forward bias (> 1.5V) was applied, the p-n junction between layer 140 and 170 was reversely biased, and the p-InP layer (layer 120) was fully depleted. Electrons from the n-InP layer (layer 120) were swept through the p-InP layer, leading to the high current in the device without a BTJ. Multiple VCSEL 300 devices (at least 10 and up to 10,000 to > million, depending on wafer size) were fabricated and tested at wafer level on a probe station. All the testing was performed under continuous-wave (CW) operation. The current source used for the characterization was a Keithley 2400, and the optical power was measured with a photodiode (Thorlab S122C) positioned directly above the device being tested. The photodiode was calibrated with a separate commercial 1550 nm EEL against the factory calibration and found 53 45662394.1 to be mutually consistent. Figure 8a shows the measured light output power vs. injected current or current density (L-I or L-J) plot from a device with 6 μm aperture (in diameter). A clear lasing threshold current density of 2.37 kA/cm2 was measured. Figure 8b shows the emission spectrum above the lasing threshold with a single lasing mode at ~1553 nm collected using Thorlab OSA 203. The linewidth reached 63 pm above the threshold current density. The side mode suppression ration (SMSR) was above 30 dB. The output power were orders of magnitude lower than the literature reported value in the SWIR wavelength. In addition to the large leakage current outside the aperture region, the fabricated VCSEL 300 devices included: 1) a highly reflective top dielectric mirror (~99.9%), which is believed to have adversely affected the light extraction from the cavity; and 2) a possible oxide layer may have formed at the interface between layers 260 and 270 which hindered the effective current injection, and may have increased the device resistance and internal heating. In summary, fabricated VCSEL300 devices used a NP-InP-based bottom DBR mirror having a BTJ structure for current confinement. A single-mode VCSEL operation at ~1,553 nm was demonstrated at room temperature. CW operation with a threshold current density of 2.37 kA/cm2, and a narrow linewidth of 63 pm was observed. Example 2: Nanoporous Vertical Cavity Surface Emitting Laser (VCSEL) having an Aperture Region formed by Ion Implantation Materials and Methods: In contrast to the BJT used in Example 1, a second VCSEL structure was made using a light-emitting structure including a nanoporous (NP)-InP-based bottom DBR mirror and an aperture region. A light emitting structure containing a Distributed Bragg Reflector (DBR) mirror was prepared starting from an epitaxially grown structure 400, as shown in Figure 9. All the layers were grown planarly and continuously. From bottom to top, structure 400 consists of seven portions: (1) a stack 410 consists of 12 pairs of alternating layers of n⁺-InP (darker bands, doping concentration: 5 x 10¹⁸ cm^-3) and n--InP (lighter bands, lightly doped, doping concentration: < 5 × 10¹⁸ cm^-3), where the n⁺-InP can be porosified by electrochemical etching to form NP-InP with a low refractive index (lower than the refractive index of the layer before porosification); (2) a layer 420 of a thick n-InP layer (light gray, doping concentration: 5 x 10¹⁷ cm^-3) of at least about 200 nm; (3) an emissive structure 430 of 54 45662394.1 InAlGaAs which provides an active region with a targeted emission wavelength of 1550 nm; (4) a layer 440 of p-InAlAs (doping concentration: 1 x 10¹⁸ cm^-3); (5) a layer 450 of p⁺⁺-InAlAs (doping concentration > 1 x 10¹⁹ cm^-3); (6) a layer 460 of n⁺⁺-InP (black, doping concentration > 1 x 10¹⁹ cm^-3); and (7) a layer 470 of n-InP layer (light gray, doping concentration: 2 x 10¹⁸ cm^-3) on top. Structure 400 was grown by metal organic chemical vapor deposition (MOCVD). Figure 10 shows a non-limiting process for a NP InP VCSEL fabrication starting with epitaxial structure 400 (Figure 10, top row, left most) where SiO2 (510) was deposited and patterned with a photoresist (520) onto the top surface of structure 400 to define the position of the aperture region (Figure 10, top row, middle). Next, ion implantation (H+; 530) was performed to damage/reduce the conductivity in layer 440 which is outside the aperture region. Ion implantation was achieved with an energy of 38-45 keV and an ion implant dosage of 6.4 × 10¹³ cm^-2. In other words, the ion implantation does not occur under the area covered by 510 and 520. The ion implantation typically occurs down to layer 430. For instance, a simulated implant-induced defect profile using Stopping and Range of Ions in Matter (SRIM) is shown in Figure 11, wherein the boundaries of different layers are marked with black dashed lines. It can be seen that the top n-InP (layer 470) was damaged during the ion implantation to some extent. According to the literature (“Ion implantation for isolation of III-V semiconductors”, Materials Science Reports 4 (1990)), InAlAs requires much higher annealing temperature, compared to InP, to recover the electrical conductivity. Based on this difference, it was possible to selectively recover the conductivity of top n-InP layer through annealing while keeping the InAlAs layer 440 resistive. A self-aligned process was utilized wherein the patterned mask formed of 510 and 520 also functioned as the mask wherein a dry etching was performed to remove a portion of layer 470 so that the area under the patterned mask was higher than the rest of the surrounding surface of layer 470, where this can be viewed as a step feature 540 present on the structure, which provides an optical confinement effect to optoelectronic devices and an ion implantation zone 535 is also shown (Figure 10, second row, left most). The region outside the aperture region was etched down by around 20 nm during the dry etching leading to the index guiding for the optical modes and helping to reduce the threshold. After removing the masking material, a PECVD SiO2 layer 550 was deposited on a portion of the surface, and the structure was annealed at 350 °C for 20 min (Figure 10, second row, center). Annealing is 55 45662394.1 believed to restore the conductivity of layer 470 which was damaged by ion implantation. Next, a mesa structure 560 was formed through a wet etching process, performed by a wet chemical etching with diluted HCl solution, followed by citric acid + hydrogen peroxide, where the bottom of the mesa structure reached the layer 420 (Figure 10, second row, right most). Next, a layer of PECVD SiO₂ (570) was deposited and patterned to cover most of the surface, except the left most portion, and served as a dry etching mask for the next step and also served to protect the mesa structure from being attacked during the electrochemical (EC) etching process (Figure 10, third row, left most). In other words, SiO2570 was deposited over the entire mesa structure and only an edge portion of the top surface was not covered by SiO2 570 at a side-wall. A deep dry etching was performed using SiO₂570 as the mask and a trench reaching the bottom of periodic layers (stack 410) was formed (Figure 10, third row, middle). Next, the structure (anode) and a platinum (Pt) wire/plate (cathode) were immersed into an electrolyte for electrochemical (EC) etching (Figure 10, third row, right most). By applying a forward bias to the structure, EC etching initiated from the trench sidewall. The porosified regions (dark regions) expanded laterally to cover the entire aperture region above. It is noted that porosification was confined only in the n+-InP layers of stack 410, leaving the lightly doped InP layers intact (un-porosified). The selectivity between porosified and un- porosified regions was achieved through the difference in the doping concentration. As a result of porosification, n⁺-InP layers were filled with air, and provided a lower refractive index, as compared to the lightly doped InP layers. An alternating structure with high- and low-index layers forms a mirror in the DBR structure, which used to form a VCSEL. Subsequently, a layer of 600 nm PECVD SiO2 (580) was deposited to provide a uniform and thorough coverage on the exposed sidewall (Figure 10 continued, bottom row, left). SiO₂ layer 580 served as: 1) a mesa sidewall passivation layer; and 2) an EC etching sidewall protection which prevents wet chemicals in the following steps from entering the nanoporous (NP) InP in stack 410. Lastly, light-emitting structure 600 containing a DBR mirror was formed by forming an opening of SiO₂ layer 580 on top of and besides the mesa structure for purposes of placing metal contacts and a top dielectric DBR deposition, as shown in Figure 10, continued, bottom row, right. A light-emitting structure 600 containing a DBR mirror is shown in detail in Figure 12. From bottom to top, the light-emitting structure 600 consists of: (1) a bottom structure 610 formed of a stack which consists of 12 pairs of alternating layers of n⁺-InP and n--InP, 56 45662394.1 where the n⁺-InP are selectively porosified by electrochemical etching, as shown by dark bands; (2) a layer 620 of a thick n-InP layer of at least about 200 nm; (3) a mesa structure which from bottom to top contains a layer 630 of InAlGaAs, which provides an active region with a targeted emission wavelength of 1550 nm; a layer 640 of p-InAlAs; a layer 650 of p⁺⁺-InAlAs; a layer 660 of n⁺⁺-InP; a current spreading layer 670 of n-InP on top, wherein the top surface of current spreading layer 670 includes a step feature 680. Within the mesa structure includes an aperture region formed of portions of p-InAlAs; p⁺⁺-InAlAs; n⁺⁺-InP; and n-InP, shown in part as the region of 645, 655, and 665 under step feature 680. Wherein the p-InAlAs, p⁺⁺-InAlAs, n⁺⁺-InP; and n-InP which are outside the aperture region was ion implanted to reduce conductivity and subsequent annealing was used to restore conductivity in at least the current spreading layer of n-InP over the aperture region. Additional layers shown in Figure 12 include a layer of SiO₂ (690) which is present due to the fabrication process but are not needed for function of the light-emitting structure or the DBR mirror contained therein. A light-emitting structure 600 containing a DBR mirror was used to form a VCSEL 700, as shown in Figure 13. The light-emitting structure 600, which contains a DBR mirror within, forms the bottom DBR mirror of the VCSEL and a top dielectric DBR mirror 710 is present on the top of the mesa structure, as well as metal contacts 720, as shown in Figure 13. The process to form VCSEL 300 is shown in Figure 14 and proceeds by forming the top DBR 710 and metal contacts 720 on light-emitting structure 600. The top DBR mirror was a lift-off of sputtering-deposited dielectric DBR (patterning photoresist, depositing DBR blanketly on the surface, and lift-off DBR on the photoresist using solvent). As a result, the top DBR only remained in the previous PR opening region. The top DBR mirror can also be formed through sputtering deposition blanketly followed by patterned dry etching to remove DBR outside the intended region. Metal contacts 720 were formed through lift-off of metal stacks deposited by e-beam evaporation. Characterization and Discussion of Light-Emitting Structures and VCSEL having an Aperture Region formed by Ion Implantation: Two light-emitting structures were fabricated to assure the current confinement using the ion implantation approach, where one structure has a current aperture region with 10 μm in diameter, while the other did not have one. Both light-emitting structures had a NP-InP- based bottom DBR mirror with porosified regions. The forward I-V curves of these two 57 45662394.1 devices are shown in Figure 15. It was found that at 2 V, the current for the device with an aperture region, such as of the light-emitting structure 600 containing a DBR mirror, was close to three orders of magnitude higher than the device without such an aperture. This confirmed that the current was successfully confined within the aperture region. Different structures of VCSELs emitting at 1380 nm and 1550 nm were designed, while they both went through the same fabrication process presented in Figure 10. Fully fabricated VCSEL devices were tested at wafer level on a probe station. All the testing was performed under continuous-wave (CW) operation. The current source used for the characterization is Keithley 2400, and the optical power was measured with a photodiode (Thorlab S122C) positioned directly above the device. Figure 16a displays the L-I-V curve of a 1380 nm VCSEL device with a 7 µm aperture. The threshold current is 0.5mA, equivalent to a current density of 1.3kA/cm², and the extracted slope efficiency is approximately 0.23W/A. The power conversion efficiency of the present device reaches a maximum of 10.4% at an injection current of 2.5mA. Lasing spectrum was collected with a Thorlab OSA 203 and is shown in Figure 16b. Single mode operation with a side-mode-suppression ratio (SMSR) close to 30dB was observed. As the injection current increases from 0.5 mA (threshold) to 8mA (close to the point of thermal rollover), a red-shift in the lasing wavelength was observed due to device heating. Similarly, room-temperature CW operation of a 1550 nm VCSEL was also achieved from a different InP VCSEL structure in which all the dimensions were scaled proportionally to the wavelength. The L-I-V curve and lasing spectra of a 7 µm aperture device are presented in Figures 17a and 17b, respectively. The threshold current is 0.67mA, equivalent to a current density of 1.7kA/cm², and the extracted slope efficiency is approximately 0.15W/A. The apparently higher threshold current density and a lower slope efficiency of 1550 nm VCSEL (as compared to the 1380 nm device) was likely due to an unoptimized process of top dielectric DBR (a-Si:H/SiO₂) mirror which took place during the deposition of the 1550 nm devices and was then corrected in the subsequent process for the 1380 nm devices. Nonetheless, single-mode operation with side-mode-suppression ratio (SMSR) above 30dB was also achieved. 58 45662394.1 Conclusion: Examples 1 and 2 above demonstrate the concept of forming light-emitting structures containing NP-InP DBRs with two distinct processes of forming current confinement, which lead to demonstrations of CW VCSEL operation. These exemplary VCSELs demonstrated room temperature CW operation, a threshold current density of around 1 kA/cm², ~mW-class output power, and a power conversion efficiency (PCE) of 10%, for VCSELs containing NP- InP DBRs in short-wave infrared (SWIR) VCSELs. Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of skill in the art to which the disclosed invention belongs. Publications cited herein and the materials for which they are cited are specifically incorporated by reference. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments of the invention. Such equivalents are intended to be encompassed by the following claims. 59 45662394.1

Claims

We claim: 1. A semiconductor structure comprising a buried tunnel junction (BTJ), the structure comprising: a bottom structure comprising alternating layers of n-doped and undoped or low- doped semiconductor layers on a semiconductor substrate; a layer of an n-doped first semiconductor atop the bottom structure; an emissive structure comprising a multiple quantum well (MQW) atop the layer of the n-doped first semiconductor; a layer of a p-doped first semiconductor atop the emissive structure; and a buried tunnel junction (BTJ) present on the layer of p-doped first semiconductor, wherein the buried tunnel junction comprises: a layer of p-doped second semiconductor having a p-doping level greater than about 1 × 10¹⁸ cm^-3; a layer of an n-doped second semiconductor having a n-doping level greater than about 1 × 10¹⁸ cm^-3 atop the layer of p-doped second semiconductor; wherein at least the layer of n-doped second semiconductor has a smaller surface area than the surface area of the layer of p-doped first semiconductor; optionally wherein the layer of p-doped second semiconductor and the layer of n-doped second semiconductor have equal areas or substantially equal areas on the layer of the p-doped first semiconductor; an n-doped current spreading layer which encapsulates at least a portion of the layer of n-doped second semiconductor, and optionally at least a portion of the layer of p-doped second semiconductor; wherein the current spreading layer outside of the portion having the layer of n-doped second semiconductor thereon contacts the p-doped second semiconductor or the p-doped first semiconductor; and wherein the current spreading layer surface optionally comprises a region over the buried tunnel junction which is elevated and forms a step feature, which provides an optical confinement effect. 60 45662394.1

2. The semiconductor structure of claim 1, wherein the semiconductor substrate is made of indium phosphide, gallium arsenide, or gallium antimonide.

3. The semiconductor structure of any one of claims 1-2, wherein the n-doped semiconductor layers in the bottom structure each have identical thicknesses; and/or the undoped or low doped semiconductor layers in the bottom structure each have identical thicknesses.

4. The semiconductor structure of any one of claims 1-3, wherein the alternating layers of the bottom structure comprise a binary semiconductor material selected from the group consisting of indium phosphide, gallium arsenide, and gallium antimonide; and wherein the alternating layers are lattice-matched to the semiconductor substrate.

5. The semiconductor structure of any one of claims 1-4, wherein the alternating layers of the bottom structure comprise a ternary semiconductor material that is lattice-matched to the semiconductor substrate.

6. The semiconductor structure of any one of claims 1-4, wherein the alternating layers of the bottom structure comprise a quaternary semiconductor material that is lattice-matched to the semiconductor substrate.

7. The semiconductor structure of any one of claims 1-6, wherein the n-doped first semiconductor, the emissive structure, the p-doped first semiconductor, p-doped second semiconductor, n-doped second semiconductor and the current spreading layer comprise one or more semiconductor materials that are lattice-matched to the semiconductor substrate.

8. The semiconductor structure of claim 7, wherein the one or more semiconductor materials are lattice-matched to an indium phosphide semiconductor substrate and are selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or the semiconductor materials are lattice-matched to a gallium arsenide semiconductor substrate and are selected from the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or the semiconductor materials are lattice-matched to a gallium antimonide semiconductor substrate and are selected from the group consisting of GaSb, AlAsSb, and AlGaAsSb.

9. The semiconductor structure of any one of claims 1-6, wherein the emissive structure, the p-doped second semiconductor layer, and the n-doped second semiconductor layer each comprise one or more semiconductor materials that are lattice-mismatched to the semiconductor substrate. 61 45662394.1

10. The semiconductor structure of claim 9, wherein the one or more semiconductor materials are lattice-mismatched to an indium phosphide semiconductor substrate and are selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the one or more semiconductor materials are lattice-mismatched to a gallium arsenide semiconductor substrate and are selected from the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the one or more semiconductor materials are lattice-mismatched to gallium antimonide semiconductor substrate and are selected from the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

11. A method of making a semiconductor structure comprising a buried tunnel junction (BTJ), the method comprising the steps of: (i) forming a bottom structure comprising alternating layers of n-doped and undoped or low doped semiconductor layers on a semiconductor substrate; (ii) depositing a layer of an n-doped first semiconductor atop the bottom structure; (iii) depositing or forming an emissive structure comprising a multiple quantum well (MQW) atop the layer of the first semiconductor; (iv) depositing a layer of a p-doped first semiconductor atop the emissive structure; (v) depositing a layer of p-doped second semiconductor, having a p-doping level greater than about 1 × 10¹⁸ cm^-3, atop the layer of the p-doped first semiconductor; (vi) depositing a layer of an n-doped second semiconductor, having a n-doping level greater than about 1 × 10¹⁸ cm^-3, a top the layer of p-doped second semiconductor; (vii) forming or patterning a masking material over a top surface portion of the layer of n-doped second semiconductor; (viii) etching to remove at least the layer of n-doped second semiconductor and optionally the p-doped second semiconductor outside the surface portion having the masking material thereon; (ix) removing the masking material; and (x) depositing an n-doped current spreading layer, which encapsulates at least a portion of the layer of n-doped second semiconductor, and optionally a portion of 62 45662394.1 the p-doped second semiconductor, and wherein the current spreading layer outside the surface portion contacts the layer of p-doped second semiconductor or the p-doped first semiconductor.

12. The method of claim 11, wherein any of the structures or layers are each independently formed or deposited by metal organic vapor deposition (MOCVD), molecular- beam epitaxy (MBE), or liquid phase epitaxy (LPE).

13. The method of any one of claims 11-12, wherein the masking material is selected from the group consisting of a dielectric (such as silicon dioxide, silicon nitride, aluminum oxide) and/or a photoresist.

14. The method of any one of claims 11-13, wherein the semiconductor substrate is made of indium phosphide, gallium arsenide, or gallium antimonide.

15. The method of any one of claims 11-14, wherein the n-doped semiconductor layers in the bottom structure each have identical thicknesses; and/or the undoped or low doped semiconductor layers in the bottom structure each have identical thicknesses.

16. The method of any one of claims 11-15, wherein the alternating layers of the bottom structure comprise a binary semiconductor material selected from the group consisting of indium phosphide, gallium arsenide, or gallium antimonide; and wherein the alternating layers are lattice-matched to the semiconductor substrate.

17. The method of any one of claims 11-15, wherein the alternating layers of the bottom structure comprise a ternary semiconductor material that is lattice-matched to the semiconductor substrate.

18. The method of any one of claims 11-15, wherein the alternating layers of the bottom structure comprise a quaternary semiconductor material that is lattice-matched to the semiconductor substrate.

19. The method of any one of claims 11-18, wherein the n-doped first semiconductor, the emissive structure, the p-doped first semiconductor, p-doped second semiconductor, n-doped second semiconductor and the current spreading layer comprise one or more semiconductor materials that are lattice-matched to the semiconductor substrate.

20. The method of claim 19, wherein the one or more semiconductor materials are lattice- matched to an indium phosphide semiconductor substrate and are selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or the semiconductor materials are lattice-matched to a gallium arsenide semiconductor substrate 63 45662394.1 and are selected from the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or the semiconductor materials are lattice-matched to a gallium antimonide semiconductor substrate and are selected from the group consisting of GaSb, AlAsSb, and AlGaAsSb.

21. The method of any one of claims 11-18, wherein the emissive structure, the p-doped second semiconductor layer, and the n-doped second semiconductor layer each comprise one or more semiconductor materials that are lattice-mismatched to the semiconductor substrate.

22. The method of claim 21, wherein the one or more semiconductor materials are lattice- mismatched to an indium phosphide semiconductor substrate and are selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the one or more semiconductor materials are lattice-mismatched to a gallium arsenide semiconductor substrate and are selected from the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the one or more semiconductor materials are lattice-mismatched to gallium antimonide semiconductor substrate and are selected from the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

23. A light-emitting structure comprising a buried tunnel junction (BTJ), the light- emitting structure comprising: a bottom mirror structure comprising alternating layers of n-doped, and undoped or low-doped semiconductor layers on a semiconductor substrate; wherein the n-doped layers are porous and comprise a plurality of pores; and, wherein the undoped or low-doped semiconductor layers are non-porous or substantially non- porous; a layer of n-doped first semiconductor atop the bottom structure; an emissive structure comprising a multiple quantum well (MQW) atop the layer of semiconductor; a layer of a p-doped first semiconductor atop the emissive structure; and a buried tunnel junction (BTJ) present on a portion of the layer of p-doped first semiconductor, wherein the buried tunnel junction defines an aperture region and comprises: a layer of p-doped second semiconductor having a p-doping level greater than about 1 × 10¹⁸ cm^-3; 64 45662394.1 a layer of an n-doped second semiconductor, having a n-doping level greater than about 1 × 10¹⁸ cm^-3, atop the layer of p-doped second semiconductor; wherein at least the layer of n-doped second semiconductor has a smaller surface area than the surface area of the layer of p-doped first semiconductor; optionally wherein the layer of p-doped second semiconductor and the layer of n-doped second semiconductor have equal areas or substantially equal areas on the layer of the p-doped first semiconductor; an n-doped current spreading layer which encapsulates at least a portion of the layer of n-doped second semiconductor, and optionally at least a portion of the layer of p-doped second semiconductor; wherein the current spreading layer outside of the portion having the layer of n-doped second semiconductor thereon contacts the p-doped second semiconductor or the p-doped first semiconductor; and wherein the current spreading layer surface optionally comprises a region over the buried tunnel junction which is elevated and forms a step feature, which provides an optical confinement effect.

24. The light-emitting structure of claim 23, wherein the semiconductor substrate is made of indium phosphide, gallium arsenide, or gallium antimonide.

25. The light-emitting structure of any one of claims 23-24, wherein the n-doped semiconductor layers in the bottom structure each have identical thicknesses; and/or the undoped or low doped semiconductor layers in the bottom structure each have identical thicknesses.

26. The light-emitting structure of any one of claims 23-25, wherein the alternating layers of the bottom structure comprise a binary semiconductor material selected from the group consisting of indium phosphide, gallium arsenide, or gallium antimonide; and wherein the alternating layers are lattice-matched to the semiconductor substrate.

27. The light-emitting structure of any one of claims 23-25, wherein the alternating layers of the bottom structure comprise a ternary semiconductor material that is lattice-matched to the semiconductor substrate. 65 45662394.1

28. The light-emitting structure of any one of claims 23-25, wherein the alternating layers of the bottom structure comprise a quaternary semiconductor material that is lattice-matched to the semiconductor substrate.

29. The light-emitting structure of any one of claims 23-28, wherein the n-doped first semiconductor, the emissive structure, the p-doped first semiconductor, p-doped second semiconductor, n-doped second semiconductor and the current spreading layer comprise one or more semiconductor materials that are lattice-matched to the semiconductor substrates.

30. The light-emitting structure of claim 29, wherein the one or more semiconductor materials are lattice-matched to an indium phosphide semiconductor substrate and are selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or the semiconductor materials are lattice-matched to a gallium arsenide semiconductor substrate and are selected from the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or the semiconductor materials are lattice-matched to a gallium antimonide semiconductor substrate and are selected from the group consisting of GaSb, AlAsSb, and AlGaAsSb.

31. The light-emitting structure of any one of claims 23-28, wherein the emissive structure, the p-doped second semiconductor layer, and the n-doped second semiconductor layer each comprise one or more semiconductor materials that are lattice-mismatched to the semiconductor substrate.

32. The light-emitting structure of claim 31, wherein the one or more semiconductor materials are lattice-mismatched to an indium phosphide semiconductor substrate and are selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the one or more semiconductor materials are lattice-mismatched to a gallium arsenide semiconductor substrate and are selected from the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the one or more semiconductor materials are lattice-mismatched to gallium antimonide semiconductor substrate and are selected from the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

33. The light-emitting structure of any one of claims 23-32, wherein the porosity is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

34. The light-emitting structure of any one of claims 23-33, wherein a refractive index contrast (Δn) exists between the alternating layers which is in a range of about 0.1 to about 2 or about 0.1 to about 2.5. 66 45662394.1

35. A method of forming a light-emitting structure comprising the steps of: (i’) providing or forming a structure comprising a buried tunnel junction (BTJ), wherein the structure comprises: a bottom structure comprising alternating layers of n-doped and undoped or low-doped semiconductor layers on a semiconductor substrate; a layer of an n-doped first semiconductor atop the bottom structure; an emissive structure comprising a multiple quantum well (MQW) atop the layer of the n-doped first semiconductor; a layer of a p-doped first semiconductor atop the emissive structure; and a buried tunnel junction (BTJ) present on the layer of p-doped first semiconductor, wherein the buried tunnel junction comprises: a layer of p-doped second semiconductor having a p-doping level greater than about 1 × 10¹⁸ cm^-3; a layer of an n-doped second semiconductor having a n-doping level greater than about 1 × 10¹⁸ cm^-3 atop the layer of p-doped second semiconductor; wherein at least the layer of n-doped second semiconductor has a smaller surface area than the surface area of the layer of p-doped first semiconductor; optionally wherein the layer of p-doped second semiconductor and the layer of n-doped second semiconductor have equal areas or substantially equal areas on the layer of the p-doped first semiconductor; and an n-doped current spreading layer which encapsulates at least a portion of the layer of n-doped second semiconductor, and optionally at least a portion of the layer of p-doped second semiconductor; wherein the current spreading layer outside of the portion having the layer of n-doped second semiconductor 67 45662394.1 thereon contacts the p-doped second semiconductor or the p- doped first semiconductor; and wherein the current spreading layer surface optionally comprises a region over the buried tunnel junction which is elevated and forms a step feature, which provides an optical confinement effect; (ii’) forming a mesa structure by etching a portion of the current spreading layer, the emissive structure, the layer of p-doped first semiconductor, optionally the layer of p-doped second semiconductor; (iii’) depositing a layer of silicon dioxide over the mesa structure, wherein at least a portion of the layer of n-doped first semiconductor is not covered by the layer of silicon dioxide; (iv’) etching the portion that is not covered by the layer of silicon dioxide to form a trench exposing a side-wall of the alternating layers of the bottom structure; (v’) selectively porosifying the n-doped semiconductor layers in the alternating layers of the bottom structure, wherein a plurality of pores are formed and wherein the undoped or low-doped semiconductor layers remain non-porous or substantially non-porous; (vi’) depositing one or more materials to cover the trench, the side-wall, and side-walls of the mesa structure; (vii’) selectively removing the one or more materials to expose at least a portion of the mesa structure top, and optionally a portion of the n-doped first semiconductor, if covered by the one or more materials; and (viii’) forming metal contacts on a portion of the mesa structure top and optionally a portion of the n-doped first semiconductor.

36. The method of claim 35, wherein the porosity formed in step (v’) is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

37. The method of any one of claims 35-36, wherein step (v’) is performed by electrochemical etching in an electrolyte solution and under an applied bias voltage.

38. The method of claim 37, wherein the electrolyte solution comprises halide ions, hydrochloric acid (HCl), sulfuric acid (H₂SO₄), hydrofluoric acid (HF), KOH, NaOH, 68 45662394.1 Ba(OH)2, Ca(OH)₂, Sr(OH)₂, NH₄OH, NaCl, NaF, nitric acid (HNO₃), organic acids and their salts (such as oxalic acid and citric acid), and mixtures thereof.

39. The method of any one of claims 35-38, wherein the one or more materials are selected from the group consisting of silicon dioxide, aluminum oxide, and silicon nitride, spin-on-glass; and/or the one or more materials are organic materials selected from the group consisting of benzocyclobutene (BCB), a polyimide, and a photoresist; and combinations thereof.

40. The method of any one of claims 35-39, wherein the metal contacts formed during step (viii’) comprise one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

41. An optoelectronic device comprising: a light-emitting structure according to any one of claims 23-34; a top distributed Bragg reflector mirror; and metal contacts.

42. The optoelectronic device of claim 41, wherein the top distributed Bragg reflector comprises alternating layers of any one of a-Si/SiO₂, TiO₂/SiO₂, Ta₂O₅/SiO₂, Nb₂O₅/SiO₂, ZnSe/SiO2, a-Si/Al2O3, a-Si/MgF, ZnS/MgF, a-Si/CaF2, or combinations thereof.

43. The optoelectronic device of any one of claims 41-42, wherein the metal contacts comprise one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

44. The optoelectronic device of any one of claims 41-43, wherein the optoelectronic device is a vertical cavity surface emitting laser (VCSEL).

45. The optoelectronic device of claim 44, wherein the vertical cavity surface emitting laser operates at room temperature (about 25 ºC) and in a continuous-wave mode.

46. The optoelectronic device of claim 44, wherein the vertical cavity surface emitting laser operates at temperatures below about 0 ºC, above about 25 ºC, or above about 85 ºC.

47. The optoelectronic device of claim 44, wherein the vertical cavity surface emitting laser operates in a pulse-mode.

48. The optoelectronic device of claim 44, wherein the vertical cavity surface emitting laser emits in the infrared wavelength region. 69 45662394.1

49. The optoelectronic device of claim 44, wherein the vertical cavity surface emitting laser has a power conversion efficiency of at least about 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 7.5%, or 10%.

50. A method of making an optoelectronic device comprising the steps of: (i”) providing or forming a light-emitting structure comprising: a bottom mirror structure comprising alternating layers of n-doped, and undoped or low-doped semiconductor layers on a semiconductor substrate; wherein the n-doped layers are porous and comprise a plurality of pores; and, wherein the undoped or low-doped semiconductor layers are non-porous or substantially non-porous; a layer of n-doped first semiconductor atop the bottom structure; an emissive structure comprising a multiple quantum well (MQW) atop the layer of semiconductor; a layer of a p-doped first semiconductor atop the emissive structure; and a buried tunnel junction (BTJ) present on a portion of the layer of p- doped first semiconductor, wherein the buried tunnel junction defines an aperture region and comprises: a layer of p-doped second semiconductor having a p-doping level greater than about 1 × 10¹⁸ cm^-3; a layer of an n-doped second semiconductor, having a n-doping level greater than about 1 × 10¹⁸ cm^-3, atop the layer of p-doped second semiconductor; wherein at least the layer of n-doped second semiconductor has a smaller surface area than the surface area of the layer of p-doped first semiconductor; optionally wherein the layer of p-doped second semiconductor and the layer of n-doped second semiconductor have equal areas or substantially equal areas on the layer of the p-doped first semiconductor; 70 45662394.1 an n-doped current spreading layer which encapsulates at least a portion of the layer of n-doped second semiconductor, and optionally at least a portion of the layer of p-doped second semiconductor; wherein the current spreading layer outside of the portion having the layer of n-doped second semiconductor thereon contacts the p-doped second semiconductor or the p- doped first semiconductor; and wherein the current spreading layer surface optionally comprises a region over the buried tunnel junction which is elevated and forms a step feature, which provides an optical confinement effect; (ii”) providing or forming a top distributed Bragg reflector mirror on the light- emitting structure; and (iii”) providing or forming metal contacts on the optoelectronic device.

51. The method of claim 50, wherein the top distributed Bragg reflector mirror of step (ii”) comprises alternating layers of any one of a-Si/SiO₂, TiO₂/SiO₂, Ta₂O₅/SiO₂, Nb2O5/SiO2, ZnSe/SiO2, a-Si/Al2O3, a-Si/MgF, ZnS/MgF, a-Si/CaF2, or combinations thereof.

52. The method of any one of claims 50-51, wherein the metal contacts of step (iii”) comprise one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

53. The method of any one of claims 50-52, wherein the optoelectronic device is a vertical cavity surface emitting laser (VCSEL).

54. A light-emitting structure comprising: a bottom mirror structure comprising alternating layers of n-doped and undoped or low-doped semiconductor layers on a semiconductor substrate; wherein the n-doped semiconductor layers are porous and comprise a plurality of pores; and, wherein the undoped or low-doped semiconductor layers are non-porous or substantially non-porous; a layer of an n-doped first semiconductor atop the bottom structure; 71 45662394.1 an emissive structure comprising a multiple quantum well (MQW) atop the layer of semiconductor; a layer of a p-doped first semiconductor atop the emissive structure; a layer of a p-doped second semiconductor, having a p-doping level greater than about 1 × 10¹⁸ cm^-3, atop the layer of p-doped first semiconductor; a layer of an n-doped second semiconductor, having a n-doping level greater than about 1 × 10¹⁸ cm^-3, atop the layer of p-doped second semiconductor; an n-doped current spreading layer atop the layer of n-doped second semiconductor; wherein an aperture region is present, wherein electrical conductivity of the layer of p-doped first semiconductor within the aperture region is greater than the electrical conductivity of the layer of p-doped first semiconductor outside of the aperture region; wherein the layer of p-doped first semiconductor, and optionally the p-doped second semiconductor, and optionally the n-doped semiconductor have a higher electrical resistance outside of the aperture region, as compared to within the aperture region; wherein the current spreading layer is electrically conductive within and outside the aperture; and wherein the current spreading layer optionally comprises a region on the top surface over the aperture region which is elevated and forms a step feature which provides an optical confinement effect.

55. The light-emitting structure of claim 54, wherein the semiconductor substrate is made of indium phosphide, gallium arsenide, or gallium antimonide.

56. The light-emitting structure of any one of claims 54-55, wherein the n-doped semiconductor layers in the bottom structure each have identical thicknesses; and/or the undoped or low doped semiconductor layers in the bottom structure each have identical thicknesses.

57. The light-emitting structure of claim 54, wherein the alternating layers of the bottom structure comprise a binary semiconductor material that is lattice-matched to the semiconductor substrate. 72 45662394.1

58. The light-emitting structure of claim 54, wherein the alternating layers of the bottom structure comprise a ternary semiconductor material that is lattice-matched to the semiconductor substrate.

59. The light-emitting structure of claim 54, wherein the alternating layers of the bottom structure comprise a quaternary semiconductor material that is lattice-matched to the semiconductor substrate.

60. The light-emitting structure of any one of claims 54-59, wherein the n-doped first semiconductor, the emissive structure, the p-doped first semiconductor, the p-doped second semiconductor, the n-doped second semiconductor, and the current spreading layer each independently comprise one or more materials that are lattice-matched to the semiconductor substrate.

61. The light-emitting structure of claim 60, wherein the one or more materials are lattice- matched to an indium phosphide semiconductor substrate and are selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or the one or more semiconductor materials are lattice-matched to a gallium arsenide semiconductor substrate and are selected from the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or the one or more semiconductor materials are lattice-matched to a gallium antimonide semiconductor substrate and are selected from the group consisting of GaSb, AlAsSb, and AlGaAsSb.

62. The light-emitting structure of claim 54-59, wherein the emissive structure, p-doped second semiconductor, and n-doped second semiconductor each independently comprise one or more materials that are lattice-mismatched to an indium phosphide semiconductor substrate.

63. The light-emitting structure of claim 62, wherein the one or more semiconductor materials are lattice-mismatched to an indium phosphide semiconductor substrate and are selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the one or more semiconductor materials are lattice-mismatched to a gallium arsenide semiconductor substrate and are selected from the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the one or more semiconductor materials are lattice-mismatched to gallium antimonide semiconductor substrate and are selected from the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb. 73 45662394.1

64. The light-emitting structure of any one of claims 54-63, wherein the layer of p-doped first semiconductor, and optionally the p-doped second semiconductor, and optionally the n- doped second semiconductor outside the aperture region have an electrical conductivity which is about 1-4 orders of magnitude lower, as compared to within the aperture region.

65. The light-emitting structure of any one of claims 54-64, wherein the porosity is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

66. The light-emitting structure of any one of claims 54-65, wherein a refractive index contrast (Δn) exists between the alternating layers in the bottom mirror structure which is in a range of about 0.1 to about 2 or about 0.1 to about 2.5.

67. A method of forming a light-emitting structure comprising the steps of: (a) providing or forming a structure comprising: a bottom structure comprising alternating layers of n-doped and undoped or low-doped semiconductor layers on a semiconductor substrate; a layer of n-doped first semiconductor atop the bottom structure; an emissive structure comprising a multiple quantum well (MQW) atop the layer of the first semiconductor; a layer of a p-doped first semiconductor atop the emissive structure; a layer of a p-doped second semiconductor, having a p-doping level greater than about 1 × 10¹⁸ cm^-3 atop the layer of p-doped first semiconductor; a layer of an n-doped second semiconductor, having a n-doping level greater than about 1 × 10¹⁸ cm^-3, atop the layer of p-doped second semiconductor; and an n-doped current spreading layer atop the layer of n-doped second semiconductor; (b) placing a masking material over a top surface region of the current spreading layer of the structure; (c) performing ion implantation to reduce the conductivity of at least the layer of p-doped first semiconductor, which is not covered by the masking material; (d) etching a portion of the current spreading layer, wherein the etching does not remove the current spreading layer under the masking material; (e) removing the masking material; 74 45662394.1 (f) depositing a first layer of silicon dioxide over a portion of the current spreading layer to cover at least the area where the masking material was present; (g) annealing the structure to increase the electrical conductivity of the top layer of the current spreading layer; (h) forming a mesa structure by etching the portion of the current spreading layer, the n-doped second semiconductor, the p-doped second semiconductor, the p-doped first semiconductor, and the emissive structure, which are not covered by the first layer of silicon dioxide; (i) depositing a second layer of silicon dioxide over the mesa structure, wherein at least a portion of the n-doped first semiconductor is not covered by the second layer of silicon dioxide; (j) etching the structure that is not covered by the second layer of silicon dioxide to form a trench exposing a side-wall of the alternating layers of the bottom structure; (k) selectively porosifying the n-doped semiconductor layers in the alternating layers of the bottom structure, wherein pores formed comprise air and wherein the undoped or low-doped semiconductor layers remain non-porous or substantially non-porous; (l) depositing one or more materials to cover the trench, the side-wall of the trench, and side walls of the mesa structure; (m) selectively removing the one or more materials to expose at least a portion of the mesa structure top and optionally a portion of the layer of semiconductor, if covered by the one or more materials; and (n) forming metal contacts on a portion of the mesa structure top and optionally a portion of the layer of semiconductor.

68. The method of claim 67, wherein the masking material is a dielectric material selected from the group consisting of silicon dioxide, aluminum oxide, and silicon nitride; or is an organic material (such as a photoresist); or is a metal (such as nickel); or combinations thereof.

69. The method of any one of claims 67-68, wherein the porosity formed in step (k) is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%. 75 45662394.1

70. The method of any one of claims 67-69, wherein step (k) is performed by electrochemical etching in an electrolyte solution and under an applied bias voltage.

71. The method of claim 70, wherein the electrolyte solution comprises halide ions, hydrochloric acid (HCl), sulfuric acid (H2SO4), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)₂, Ca(OH)₂, Sr(OH)₂, NH₄OH, NaCl, NaF, nitric acid (HNO₃), organic acids and their salts (such as oxalic acid and citric acid), and mixtures thereof.

72. The method of any one of claims 67-71, wherein the one or more materials are selected from the group consisting of silicon dioxide, aluminum oxide, and silicon nitride; and/or the one or more materials are organic materials selected from the group consisting of benzocyclobutene (BCB), a polyimide, and a photoresist; and combinations thereof.

73. The method of any one of claims 67-72, wherein the metal contacts comprise one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

74. An optoelectronic device comprising: a light-emitting structure according to any one of claims 54-66; a top distributed Bragg reflector mirror; and metal contacts.

75. The optoelectronic device of claim 74, wherein the top distributed Bragg reflector mirror comprises alternating layers of any one of a-Si/SiO2, TiO2/SiO2, Ta2O5/SiO2, Nb2O5/SiO2, ZnSe/SiO2, a-Si/Al2O3, a-Si/MgF, ZnS/MgF, a-Si/CaF2, or combinations thereof.

76. The optoelectronic device of any one of claims 74-75, wherein the metal contacts comprise one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

77. The optoelectronic device of any one of claims 74-76, wherein the optoelectronic device is a vertical cavity surface emitting laser (VCSEL).

78. The optoelectronic device of claim 77, wherein the vertical cavity surface emitting laser operates at room temperature (about 25 ºC) and in a continuous-wave mode.

79. The optoelectronic device of claim 77, wherein the vertical cavity surface emitting laser operates at temperatures below about 0 ºC, above about 25 ºC, or above about 85 ºC.

80. The optoelectronic device of claim 77, wherein the vertical cavity surface emitting laser operates in a pulse-mode. 76 45662394.1

81. The optoelectronic device of claim 77, wherein the vertical cavity surface emitting laser emits in the infrared and/or red wavelength region.

82. The optoelectronic device of claim 77, wherein the vertical cavity surface emitting laser emits has a power conversion efficiency of at least about 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 7.5%, or 10%.

83. A method of making an optoelectronic device comprising the steps of: (a’) providing or forming a light-emitting structure comprising: a bottom mirror structure comprising alternating layers of n-doped and undoped or low-doped semiconductor layers on a semiconductor substrate; wherein the n-doped semiconductor layers are porous and comprise a plurality of pores; and, wherein the undoped or low-doped semiconductor layers are non-porous or substantially non-porous; a layer of an n-doped first semiconductor atop the bottom structure; an emissive structure comprising a multiple quantum well (MQW) atop the layer of semiconductor; a layer of a p-doped first semiconductor atop the emissive structure; a layer of a p-doped second semiconductor, having a p-doping level greater than about 1 × 10¹⁸ cm^-3, atop the layer of p-doped first semiconductor; a layer of an n-doped second semiconductor, having a n-doping level greater than about 1 × 10¹⁸ cm^-3, atop the layer of p-doped second semiconductor; an n-doped current spreading layer atop the layer of n-doped second semiconductor; wherein an aperture region is present, wherein electrical conductivity of the layer of p-doped first semiconductor within the aperture region is greater than the electrical conductivity of the layer of p-doped first semiconductor outside of the aperture region; wherein the layer of p-doped first semiconductor, and optionally the p- doped second semiconductor, and optionally n-doped second semiconductor have a higher electrical resistance outside of the aperture region, as compared to within the aperture region; 77 45662394.1 wherein the current spreading layer is electrically conductive within and outside the aperture; and wherein the current spreading layer optionally comprises a region on the top surface over the aperture region which is elevated and forms a step feature which provides an optical confinement effect; (b’) providing or forming a top distributed Bragg reflector mirror on the light- emitting structure; and (c’) providing or forming metal contacts on the optoelectronic device.

84. The method of claim 83, wherein the top distributed Bragg reflector mirror of step (b’) comprises alternating layers of any one of a-Si/SiO₂, TiO₂/SiO₂, Ta₂O₅/SiO₂, Nb2O5/SiO2, ZnSe/SiO2, a-Si/Al2O3, a-Si/MgF, ZnS/MgF, a-Si/CaF2, or combinations thereof.

85. The method of any one of claims 83-84, wherein the metal contacts of step (c’) comprise one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

86. The method of any one of claims 83-85, wherein the optoelectronic device is a vertical cavity surface emitting laser (VCSEL). 78 45662394.1