EP4696105A1

EP4696105A1 - Interface circuit, driver and controlling method

Info

Publication number: EP4696105A1
Application number: EP23938772.3A
Authority: EP
Inventors: Shuanghong Wang; ShiYu Ding; Qian Chen; Yuli Chen; Jianfeng Zhang
Original assignee: Tridonic GmbH and Co KG
Current assignee: Tridonic GmbH and Co KG
Priority date: 2023-05-29
Filing date: 2023-05-29
Publication date: 2026-02-18
Also published as: CN121533140A; WO2024243775A1

Abstract

An interface circuit, a driver and a controlling method. The interface circuit, comprising: a first DALI (Digital Addressable Lighting Interface) interface circuit, configured to be connected with a first data bus and a controller (MCU), sending a first signal to the controller and receiving a feedback signal from the controller; and a second DALI interface circuit, configured to be connected with the first DALI interface circuit and a second data bus, signals received from the second data bus being transmitted to the first DALI interface circuit by the second DALI interface circuit, and signals received from the first data bus can be transmitted to the second DALI interface circuit.

Description

INTERFACE CIRCUIT, DRIVER AND CONTROLLING METHOD

TECHNICAL FIELD

Embodiments of the present disclosure generally relate to the field of lighting, and more particularly, to an interface circuit, a driver and a controlling method.

BACKGROUND

This section introduces aspects that may facilitate better understanding of the present disclosure. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is in the prior art or what is not in the prior art.
In standard DALI (Digital Addressable Lighting Interface) applications, power lines and DALI control lines are laid together in the same cable. DALI interface on driver PCB (printed circuit board) was also put near L line and N line with basic insulation.

SUMMARY

The inventor found that: there was no DALI interface in secondary side for customer application, DALI control signal only can transmit from primary DALI bus.
In general, embodiments of the present disclosure provide an interface circuit, a driver and a controlling method. In the embodiments, a first DALI interface is provided on driver’s primary side, a second DALI interface is provided on driver’s secondary side, DALI signals may be bidirectional transmitted between the first DALI interface and the second interface, so that the DALI signal timing requirement (for example, maximum 15μs delay of DALI signal link) may be satisfied.
In a first aspect, there is provided an interface circuit, including:
a first DALI (Digital Addressable Lighting Interface) interface circuit, configured to be connected with a first data bus and a controller (MCU) , sending a first signal to the controller and receiving a feedback signal from the controller; and
a second DALI interface circuit, configured to be connected with the first DALI interface circuit and a second data bus,
signals received from the second data bus being transmitted to the first DALI interface circuit by the second DALI interface circuit, and signals received from the first data bus can be transmitted to the second DALI interface circuit.
In at least one embodiment, the second DALI interface circuit includes:
a transmission block, which perform bidirectional transmission of signals between the first DALI interface circuit and the second DALI interface circuit.
In at least one embodiment, the transmission block includes:
a first optical coupler (U10, U94) , configured to output a first controlling signal according to signals from the first DALI interface circuit;
a first switch (M10, M93) , configured to be coupled between output terminals of the second DALI interface circuit and controlled by the first controlling signal;
a second optical coupler (U20, U92) , configured to output a second controlling signal according to signals from the second DALI interface circuit; and
a second switch (M30, M91) , configured to be coupled with the first DALI interface circuit and controlled by the second controlling signal.
In at least one embodiment, when signals from the first DALI interface circuit are high level, the first optical coupler (U10, U94) turns on, and the first switch (M10, M93) is turned off, the output terminals of the second DALI interface circuit output signals of high level;
when signals from the first DALI interface circuit are low level, the first optical coupler (U10, U94) turns off, and the first switch (M10, M93) is turned on, the output terminals of the second DALI interface circuit output signals of low level;
when signals from the second DALI interface circuit are high level, the second optical coupler (U20, U92) turns on, and the second switch (M30, M91) is turned off, the first DALI interface circuit is provided with signals of high level;
when signals from the second DALI interface circuit are low level, the second optical coupler (U20, U92) turns off, and the second switch (M30, M91) is turned on, the first DALI interface circuit is provided with signals of low level.
In at least one embodiment, the second DALI interface circuit further includes:
a high voltage protection circuit, configured to include a protection switch (M 31, M92) connected with gate pin of the second switch (M30, M91) and detects signals from the first DALI interface circuit,
when the signals from the first DALI interface circuit are high level, the protection switch (M 31, M92) turns on, and the second switch (M30, M91) is turned off.
In at least one embodiment, the second DALI interface circuit further includes:
unlock circuit, configured to turn off the first switch (M10, M93) when signals from the second DALI interface circuit are transmitted to the first DALI interface circuit, and/or to turn off the second switch (M30, M91) when signals from the first DALI interface circuit are transmitted to the second DALI interface circuit.
In at least one embodiment, the unlock circuit includes:
a first comparator (U1-a) and a third switch (M1) , wherein a gate of the third switch (M1) is coupled to an output pin of the first comparator (U1-a) , a drain of the third switch is coupled to a gate of the second switch (M10) , the first comparator (U1-a) compares a first reference voltage with a first voltage related to signals received from the second data bus; and
a second comparator (U2-a) and a fourth switch (M2) , wherein a gate of the fourth switch is coupled to an output pin of the second comparator (U2-a) , a drain of the fourth switch is coupled to a gate of the first switch (M30) , the second comparator (U2-a) compares a second reference voltage with a second voltage related to signals received from the first bus.
In at least one embodiment, the unlock circuit includes:
a first controller (U90) , configured to output a first unlock controlling signal and a second unlock controlling signal,
when the first controller (U90) detects that signals from the second DALI interface circuit are transmitted to the first DALI interface circuit, outputs the first unlock controlling signal to turn off the first switch (M93) ,
when the first controller (U90) detects that signals from the first DALI interface circuit are transmitted to the second DALI interface circuit, outputs the second unlock controlling signal to turn off the second switch (M91) .
In a second aspect, there is provided a driver, used for driving a lighting device, the driver includes the interface circuit according to any one of embodiments and a controller, the interface circuit sending a first signal to the controller and receiving a feedback signal from the controller.
In a second aspect, there is provided a controlling method for an interface circuit, the interface circuit including:
a first DALI (Digital Addressable Lighting Interface) interface circuit, configured to be connected with a first data bus and a controller (MCU) , sending a first signal to the controller and receiving a feedback signal from the controller; and
a second DALI interface circuit, configured to be connected with the first DALI interface circuit and a second data bus;
the controlling method includes:
signals received from the second data bus being transmitted to the first DALI interface circuit by the second DALI interface circuit, and signals received from the first data bus being transmitted to the second DALI interface circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features, and benefits of various embodiments of the disclosure will become more fully apparent, by way of example, from the following detailed description with reference to the accompanying drawings, in which like reference numerals or letters are used to designate like or equivalent elements. The drawings are illustrated for facilitating better understanding of the embodiments of the disclosure and not necessarily drawn to scale, in which:
Fig. 1 is a block diagram of an interface circuit in accordance with an embodiment of the present disclosure;
Fig. 2 is a circuit diagram of an interface circuit in accordance with an embodiment of the present disclosure;
Fig. 3 is a circuit diagram of an interface circuit in accordance with another embodiment of the present disclosure;
Fig. 4 shows a flowchart of a controlling method of the interface circuit.

DETAILED DESCRIPTION

The present disclosure will now be discussed with reference to several example embodiments. It should be understood that these embodiments are discussed only for the purpose of enabling those skilled persons in the art to better understand and thus implement the present disclosure, rather than suggesting any limitations on the scope of the present disclosure.
As used herein, the terms “first” and “second” refer to different elements. The singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises, ” “comprising, ” “has, ” “having, ” “includes” and/or “including” as used herein, specify the presence of stated features, elements, and/or components and the like, but do not preclude the presence or addition of one or more other features, elements, components and/or combinations thereof. The term “based on” is to be read as “based at least in part on. ” The term “one embodiment” and “an embodiment” are to be read as “at least one embodiment. ” The term “another embodiment” is to be read as “at least one other embodiment. ” Other definitions, explicit and implicit, may be included below.
First aspect of embodiments
An interface circuit is provided in a first embodiment.
Fig. 1 is a block diagram of an interface circuit in accordance with an embodiment of the present disclosure.
As shown in Fig. 1, an interface circuit 10 includes a first DALI (Digital Addressable Lighting Interface) interface circuit 11 and a second DALI interface circuit 12.
In at least one embodiment, the first DALI interface circuit 11 is configured to be connected with a first data bus DB1 and a controller 100 (for example, the controller 100 is MCU) , sending a first signal S1 to the controller 100 and receiving a feedback signal FBS from the controller 100. Signals received by the first DALI interface 11 from the first data bus DB1 may be denoted as DALI signals received from terminal DALI_in.
The second DALI interface circuit 12 is configured to be connected with the first DALI interface circuit 11 and a second data bus DB2. Signals received by the second DALI interface from second data bus DB2 may be denoted as DALI signals received from terminal pDALI_insulated.
In at least one embodiment, signals (for example, DALI signals received from terminal pDALI_insulated) received from the second data bus DB2 can be transmitted to the first DALI interface circuit 11 by the second DALI interface circuit 12. Signals (for example, DALI signals received from terminal DALI_in) received from the first data bus DB1 can be transmitted to the second DALI interface circuit 12. Therefore, DALI signals can be bidirectional transmitted between the first DALI interface and the second interface, so that the DALI signal timing requirement (for example, maximum 15μs delay of DALI signal link) may be satisfied.
In at least one embodiment, the first DALI interface 11 may be provided on driver’s primary side, the second DALI interface 12 may be provided on driver’s secondary side. Costumer may choose the first DALI interface 11 or the second DALI interface 12 for their application, thus the flexibility and convenience of the interface circuit 10 may be improved.
The first DALI interface circuit 11 may be standard DALI interface circuit, which may be referred to the related art.
As shown in Fig. 1, the second DALI interface circuit 12 may include a transmission block 121. The transmission block 121 performs bidirectional transmission of signals between the first DALI interface circuit 11 and the second DALI interface circuit 12.
As shown in Fig. 1, the second DALI interface circuit 12 may further include a high voltage protection circuit 122. The high voltage protection circuit 122 is configured to turn off the signals transmission between the first DALI interface circuit.
As shown in Fig. 1, the second DALI interface circuit 12 may further include an unlock circuit 123. The unlock circuit 123 is used for avoiding a problem that high level signal transmission failure after low level signal transmission.
Fig. 2 is a circuit diagram of an interface circuit in accordance with an embodiment of the present disclosure. Fig. 2 shows details of the interface circuit 10 of Fig. 1 in at least one embodiment.
As shown in Fig. 2, in first DALI interface circuit 11, the DALI signal can transmit from DALI_in, go through optical coupler U141 into the controller 100 (shown in Fig. 1) . Then feedback signal is sent to the first DALI interface circuit 11 through U140 to DALI bus (for example, DB1) .
As shown in Fig. 2, the second DALI interface circuit 12 includes a transmission block 121, a high voltage protection circuit 122 and an unlock circuit 123.
The transmission block 121 includes: a first optical coupler U10, a first switch M10, a second optical coupler U20 and a second switch M30.
The first optical coupler U10 is configured to output a first controlling signal CS1 according to signals from the first DALI interface circuit 11.
The first switch M10 is configured to be coupled between output terminals of the second DALI interface circuit 12 and controlled by the first controlling signal CS1.
The second optical coupler U20 is configured to output a second controlling signal CS2 according to signals from the second DALI interface circuit 12.
The second switch M30 is configured to be coupled with the first DALI interface circuit 11 and controlled by the second controlling signal CS2.
Working principle of the transmission block 121 is described as follows.
Transmission from the first DALI interface circuit 11 to the second DALI interface circuit 12:
when signals from the first DALI interface circuit 11 are high level, the first optical coupler U10 turns on, and the first switch M10 is turned off, the output terminals (for example: X4-a, X4-b, X4-c, X4-d) of the second DALI interface circuit 12 output signals with high level;
when signals from the first DALI interface circuit 11 are low level, the first optical coupler U10 turns off, and the first switch M10 is turned on, the output terminals of the second DALI interface circuit output signals with low level.
Transmission from the second DALI interface circuit 12 to the first DALI interface circuit 11:
when signals from the second DALI interface circuit 12 are high level, the second optical coupler U20 turns on, and the second switch M30 is turned off, the first DALI interface circuit 11 is provided with signals of high level;
when signals from the second DALI interface circuit 12 are low level, the second optical coupler U20 turns off, and the second switch M30 is turned on, the first DALI interface circuit 11 is provided with signals of low level.
Therefore, DALI signals can be bidirectional transmission between the first DALI interface circuit 11 and the second DALI interface circuit 12. DALI signals in terminal DALI_in and DALI signals in terminal pDALI_insulated can be synchronous. When customer chooses to use the second interface circuit 12 to receive DALI signals from the second data bus DB2, the DALI signals may be synchronously transmitted to the first interface circuit 11; when the customer chooses to use the first interface circuit 11 to receive DALI signals from the first data bus DB1, the DALI signals may be synchronously transmitted to the second interface circuit 12.
As shown in Fig. 2, the high voltage protection circuit 122 may include a protection switch M 31 being connected with gate pin of the second switch M30 and detects signals from the first DALI interface circuit 11. When the signals from the first DALI interface circuit 11 are high level, the protection switch M 31 turns on, and the second switch M30 is turned off.
As shown in Fig. 2, the unlock circuit 123 is configured to turn off the first switch M10 when signals from the second DALI interface circuit 12 are transmitted to the first DALI interface circuit 11, and/or to turn off the second switch M30 when signals from the first DALI interface circuit 12 are transmitted to the second DALI interface circuit 12.
The unlock circuit 123 may include a first block 1231 and a second block 1232.
As shown in Fig. 2, the first block 1231 may include a first comparator U1-aand a third switch M1. A gate of the third switch M1 is coupled to an output pin (for example, pin 1) of the first comparator U1-a, a drain of the third switch M1 is coupled to a gate of the second switch M10. The first comparator U1-a may compare a first reference voltage (for example, the first voltage is provided by a supply U1-c and resistor R11 and R20) with a first voltage (for example, a ‘+’ pin 3 of the first comparator U1-a is coupled to the resistor R15 and diode D13) related to signals received from the second bus.
When signals from the second DALI interface circuit 12 are transmitted to the first DALI interface circuit, the first block 1231 is used to turn off the second switch M10, so that voltage on M10 is set to high level.
For example, for the first block 1231, before signals from terminal pDALI_insulated change to low level, they are high level. When the current cross D11 and M10 leads to its voltage raise slightly (for example, slight variation) , there would be current glow into a capacitor C11, then pin 3 of U1-a is raised and pin1 of U1-a is changed to high level, M1 turns on, M10 turns off, and voltage on M10 is set to high level. At this time, C11 is charged to high level, but pin3 of U1-a is going down to low level again, unlocking operation is completed.
As shown in Fig. 2, the second block 1232 may include a second comparator U2-a and a fourth switch M2. A gate of the fourth switch M2 is coupled to an output pin (for example, pin 1) of the second comparator U2-a, a drain of the fourth switch M2 is coupled to a gate of the first switch M30. The second comparator U2-a compares a second reference voltage (for example, the second voltage is provided by a supply U2-c and resistor R18 and R19) with a second voltage (for example, the second voltage may be denoted as DALI+ as shown in Fig. 2) related to signals received from the first data bus DB1.
When signals from the first DALI interface circuit 11 are transmitted to the second DALI interface circuit 12, the second block 1232 is used to turn off the first switch M30, so that voltage on M30 is set to high level.
For example, for the second block 1232, before signals from terminal DALI_in change to low level, they are high level. When the current cross D30 and M30 lead to its voltage raise slightly (for example, slight variation) , there would be current glow into a capacitor C30, then pin 3 of U2-a is raised and pin1 of U2-a is changed to high level, M2 turns on, M30 turns off, and voltage on M30 is set to high level. At this time, C30 is charged to high level, but pin3 of U2-a is going down to low level again, unlocking operation is completed.
In the application, when low level signals are transmitted between the first DALI interface circuit 11 and the second DALI interface circuit 12, if switch M10 and M30 are both turned on, the transmitted signals are impossible to be high level if there is no unlock circuit 123. In another words, the unlock circuit 123 is used for avoiding a problem that high level signal transmission failure after low level signal transmission.
Fig. 3 is a circuit diagram of an interface circuit in accordance with another embodiment of the present disclosure. Fig. 3 shows details of the interface circuit 10 of Fig. 1 in at least another embodiment.
As shown in Fig. 3, description for the first DALI interface circuit 11 can be referred to the same description for Fig. 2.
As shown in Fig. 3, the second DALI interface circuit 12 includes a transmission block 121, a high voltage protection circuit 122 and an unlock circuit 123.
The transmission block 121 includes: a first optical coupler U94, a first switch M93, a second optical coupler U92 and a second switch M91.
The first optical coupler U94 is configured to output a first controlling signal CS1 according to signals from the first DALI interface circuit 11.
The first switch M93 is configured to be coupled between output terminals of the second DALI interface circuit 12 and controlled by the first controlling signal CS1.
The second optical coupler U92 is configured to output a second controlling signal CS2 according to signals from the second DALI interface circuit 12.
The second switch M91 is configured to be coupled with the first DALI interface circuit 11 and controlled by the second controlling signal CS2.
Working principle of the transmission block 121 in Fig. 3 is described as follows.
Transmission from the first DALI interface circuit 11 to the second DALI interface circuit 12:
when signals from the first DALI interface circuit 11 are high level, the first optical coupler U94 turns on, and the first switch M93 is turned off, the output terminals (for example: X4-a, X4-b, X4-c, X4-d) of the second DALI interface circuit 12 output signals with high level;
when signals from the first DALI interface circuit 11 are low level, the first optical coupler U94 turns off, and the first switch M93 is turned on, the output terminals of the second DALI interface circuit output signals with low level.
Transmission from the second DALI interface circuit 12 to the first DALI interface circuit 11:
when signals from the second DALI interface circuit 12 are high level, the second optical coupler U92 turns on, and the second switch M91 is turned off, the first DALI interface circuit 11 is provided with signals of high level;
when signals from the second DALI interface circuit 12 are low level, the second optical coupler U92 turns off, and the second switch M91 is turned on, the first DALI interface circuit 11 is provided with signals of low level.
Therefore, DALI signals can be bidirectional transmission between the first DALI interface circuit 11 and the second DALI interface circuit 12. DALI signals in terminal DALI_in and DALI signals in terminal pDALI_insulated can be synchronous.
As shown in Fig. 3, the high voltage protection circuit 122 may include a protection switch M31 being connected with gate pin of the second switch M91 and detects signals from the first DALI interface circuit 11. When the signals from the first DALI interface circuit 11 are high level, the protection switch M31 turns on, and the second switch M91 is turned off.
As shown in Fig. 3, the unlock circuit 123 is configured to turn off the first switch M93 when signals from the second DALI interface circuit 12 are transmitted to the first DALI interface circuit 11, and/or to turn off the second switch M91 when signals from the first DALI interface circuit 12 are transmitted to the second DALI interface circuit 12.
The unlock circuit 123 of Fig. 3 may include a first controller U90. The first controller U90 may be an MCU (Microcontroller Unit) .
The first controller U90 is configured to output a first unlock controlling signal and a second unlock controlling signal. The first unlock controlling signal and the second unlock controlling signal may be outputted from separate pins of the first controller U90.
For example, the first unlock controlling signal is outputted from pin 1 of the first controller U90, to gate of switch M94, and drain of M94 is coupled to gate of the first switch M93; the second unlock controlling signal is outputted from pin 5 of the first controller U90 to an optical coupler U142, an output pin of the optical coupler U142 is coupled to gate of switch M95, and drain of M95 is coupled to gate of the second switch M91.
As shown in Fig. 3, when the first controller U90 detects that signals from the second DALI interface circuit 12 are transmitted to the first DALI interface circuit 11, outputs the first unlock controlling signal to turn off the first switch M93. For example, when the first controller U90 detects that signals from the second DALI interface circuit 12 are transmitted to the first DALI interface circuit 11, the first controller U90 will generate high pulse in pin 1 until this signal transmitting end, and M94 turns on, M93 will turn off, the voltage on M93 is set to high level, unlocking operation is complete.
As shown in Fig. 3, when the first controller U90 detects that signals from the first DALI interface circuit are transmitted to the second DALI interface circuit, outputs the second unlock controlling signal to turn off the second switch M91. For example, when the first controller U90 detects that signals from the first DALI interface circuit 11 are transmitted to the second DALI interface circuit 12, the first controller U90 will generate high pulse in pin 5 until this signal transmitting end, and M95 turns on, M91 will turn off, the voltage on M91 is set to high level, unlocking operation is complete.
In the application, when low level signals are transmitted between the first DALI interface circuit 11 and the second DALI interface circuit 12, if switch M93 and M91 are both turned on, the transmitted signals are impossible to be high level if there is no unlock circuit 123. In another words, the unlock circuit 123 is used for avoiding a problem that high level signal transmission failure after low level signal transmission.
Other components of the interface circuit 10 are shown in Fig. 2 and Fig. 3. For their description, please refer to the related, this application will not recite description of the components.
Second aspect of embodiments
A driver is provided in the second aspect of embodiments.
In the third aspect of embodiments, the driver is used for driving a lighting device for example, the lighting device may be LED.
The driver includes the interface circuit 10 according to the first aspect of embodiments.
The interface circuit 10 may send a first signal to the controller 100 and receive a feedback signal from the controller 100.
Third aspect of embodiments
A controlling method of an interface circuit. The interface circuit is provided in the first aspect of embodiments. The same contents as those in the first aspect of embodiments are omitted.
Fig. 4 shows a flowchart of a controlling method of the interface circuit 10.
As shown in Fig. 4, the method 40 includes:
Block 41: signals received from the second data bus are transmitted to the first DALI interface circuit by the second DALI interface circuit, and signals received from the first data bus being transmitted to the second DALI interface circuit.
According to the second aspect of embodiments, DALI signals can be bidirectional transmitted between the first DALI interface and the second interface, so that the DALI signal timing requirement (for example, maximum 15μs delay of DALI signal link) may be satisfied.
Further, while operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are contained in the above discussions, these should not be construed as limitations on the scope of the present disclosure, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination.
Although the present disclosure has been described in language specific to structural features and/or methodological acts, it is to be understood that the present disclosure defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

An interface circuit, comprising:

a first DALI (Digital Addressable Lighting Interface) interface circuit, configured to be connected with a first data bus and a controller (MCU) , sending a first signal to the controller and receiving a feedback signal from the controller; and

a second DALI interface circuit, configured to be connected with the first DALI interface circuit and a second data bus,

wherein, signals received from the second data bus being transmitted to the first DALI interface circuit by the second DALI interface circuit, and signals received from the first data bus can be transmitted to the second DALI interface circuit.
The interface circuit according to claim 1, wherein,

the second DALI interface circuit comprises:

a transmission block, which perform bidirectional transmission of signals between the first DALI interface circuit and the second DALI interface circuit.
The interface circuit according to claim 2, wherein,

the transmission block comprises:

a first optical coupler (U10, U94) , configured to output a first controlling signal according to signals from the first DALI interface circuit;

a first switch (M10, M93) , configured to be coupled between output terminals of the second DALI interface circuit and controlled by the first controlling signal;

a second optical coupler (U20, U92) , configured to output a second controlling signal according to signals from the second DALI interface circuit; and

a second switch (M30, M91) , configured to be coupled with the first DALI interface circuit and controlled by the second controlling signal.
The interface circuit according to claim 3, wherein,

when signals from the first DALI interface circuit are high level, the first optical coupler (U10, U94) turns on, and the first switch (M10, M93) is turned off, the output terminals of the second DALI interface circuit output signals of high level;

when signals from the first DALI interface circuit are low level, the first optical coupler (U10, U94) turns off, and the first switch (M10, M93) is turned on, the output terminals of the second DALI interface circuit output signals of low level;

when signals from the second DALI interface circuit are high level, the second optical coupler (U20, U92) turns on, and the second switch (M30, M91) is turned off, the first DALI interface circuit is provided with signals of high level;

when signals from the second DALI interface circuit are low level, the second optical coupler (U20, U92) turns off, and the second switch (M30, M91) is turned on, the first DALI interface circuit is provided with signals of low level.
The interface circuit according to claim 3, wherein,

the second DALI interface circuit further comprises:

a high voltage protection circuit, configured to comprise a protection switch (M 31, M92) connected with gate pin of the second switch (M30, M91) and detects signals from the first DALI interface circuit,

when the signals from the first DALI interface circuit are high level, the protection switch (M 31, M92) turns on, and the second switch (M30, M91) is turned off.
The interface circuit according to claim 3, wherein,

the second DALI interface circuit further comprises:

unlock circuit, configured to turn off the first switch (M10, M93) when signals from the second DALI interface circuit are transmitted to the first DALI interface circuit, and/or to turn off the second switch (M30, M91) when signals from the first DALI interface circuit are transmitted to the second DALI interface circuit.
The interface circuit according to claim 6, wherein,

the unlock circuit comprises:

a first comparator (U1-a) and a third switch (M1) , wherein a gate of the third switch (M1) is coupled to an output pin of the first comparator (U1-a) , a drain of the third switch is coupled to a gate of the second switch (M10) , the first comparator (U1-a) compares a first reference voltage with a first voltage related to signals received from the second data bus; and

a second comparator (U2-a) and a fourth switch (M2) , wherein a gate of the fourth switch is coupled to an output pin of the second comparator (U2-a) , a drain of the fourth switch is coupled to a gate of the first switch (M30) , the second comparator (U2-a) compares a second reference voltage with a second voltage related to signals received from the first bus.
The interface circuit according to claim 6, wherein,

the unlock circuit comprises:

a first controller (U90) , configured to output a first unlock controlling signal and a second unlock controlling signal,

when the first controller (U90) detects that signals from the second DALI interface circuit are transmitted to the first DALI interface circuit, outputs the first unlock controlling signal to turn off the first switch (M93) ,

when the first controller (U90) detects that signals from the first DALI interface circuit are transmitted to the second DALI interface circuit, outputs the second unlock controlling signal to turn off the second switch (M91) .
A driver, used for driving a lighting device, the driver comprises the interface circuit according to any one of claims 1-8 and a control, wherein,

the interface circuit sending a first signal to the controller and receiving a feedback signal from the controller.
A controlling method for an interface circuit, the interface circuit comprising:

a first DALI (Digital Addressable Lighting Interface) interface circuit, configured to be connected with a first data bus and a controller (MCU) , sending a first signal to the controller and receiving a feedback signal from the controller; and

a second DALI interface circuit, configured to be connected with the first DALI interface circuit and a second data bus,

wherein, the controlling method comprises:

signals received from the second data bus being transmitted to the first DALI interface circuit by the second DALI interface circuit, and signals received from the first data bus being transmitted to the second DALI interface circuit.