EP4693264A1

EP4693264A1 - Gate drive unit and display apparatus

Info

Publication number: EP4693264A1
Application number: EP23946468.8A
Authority: EP
Inventors: Feixiang SUN; Yi Liu
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2023-07-24
Filing date: 2023-11-27
Publication date: 2026-02-11
Also published as: DE212023000449U1; WO2025020389A1; CN119360761A

Abstract

This application provides a gate driving unit and a display device, including a first frequency division control line, a second frequency division control line, and a plurality of gate driving circuits. An output module of each of the gate driving circuits is electrically connected to the first frequency division control line or the second frequency division control line, and is electrically connected a first node and a second node in the stage transmission module, so as to output a first frequency division control signal or a second frequency division control signal to a scanning output terminal of a current stage of the gate driving circuits based on signals from the first node and the second node.

Description

TECHNICAL FIELD

The present application relates to a technical field of display, and in particular to a gate driving unit and a display device.

BACKGROUND

The display panel can be converted to the low-frequency mode through the frequency conversion technique in the standby state or when using specific application software, which can reduce the power consumption of the display panel and is beneficial to improving the battery life of the display device. However, when the existing display panels enter the low-frequency mode through the full-screen low-frequency display module, which limits their usage scenarios.

SUMMARY

Embodiments of the present application provide a gate driving unit and a display device, which can facilitate driving of the display panel in a frequency division manner.
The present application provides a gate driving unit, including a first frequency division control line for transmitting a first frequency division control signal, a second frequency division control line for transmitting a second frequency division control signal, and a plurality of cascaded stages of gate driving circuits, where each of the cascaded stages of gate driving circuits includes a stage transmission module and an output module. The stage transmission module is configured to receive a previous-stage stage transmission signal, a first clock signal, and a second clock signal, and output a current-stage stage transmission signal to a next stage of the gate driving circuits. The output module is electrically connected to the first frequency division control line or the second frequency division control line, and is electrically connected to a first node and a second node in the stage transmission module, where the output module is configured to output the first frequency division control signal or the second frequency division control signal to a scanning output terminal of a current stage of the gate driving circuits based on signals from the first node and the second node.
The embodiments of the present application further provide a display device including any gate driving unit as described above and a display panel. The display panel includes a plurality of sub-pixels and a plurality of first scanning lines, the plurality of sub-pixels include a plurality of light-emitting devices and a plurality of pixel driving circuits for driving the light-emitting devices to emit light, and the pixel driving circuit includes at least one transistor, where gate control signals output by the cascaded stages of gate driving circuits are transmitted to control terminals of the transistors of the plurality of pixel driving circuits through the plurality of first scanning lines.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGs. 1A and 1B are schematic diagrams of a structure of a gate driving unit according to an embodiment of the present application.
FIGs. 2A and 2B are timing diagrams corresponding to a gate driving unit according to an embodiment of the present application.
FIGs. 3A and 3B are schematic diagrams of a structure of a display device according to an embodiment of the present application.
FIG. 4 is a schematic diagram of a structure of a pixel driving circuit according to an embodiment of the present application.
FIGs. 5A and 5B are timing diagrams of a display device according to an embodiment of the present application.

DETAILED DESCRIPTION

To make the objectives, technical solutions, and effects of the present application clearer and more definite, the present application is illustrated in detail below by referring to the accompanying drawings and illustrating the embodiments. It should be understood that the specific embodiments described here are only used to explain the present application and are not used to limit the present application.
The present application provides a gate driving unit and a display device, including a first frequency division control line, a second frequency division control line and a plurality of cascaded stages of gate driving circuits. Each of the gate driving circuits includes a stage transmission module and an output module, and the output module is electrically connected to the first frequency division control line or the second frequency division control line, and is electrically connected to a first node and a second node in the stage transmission module, so as to output a first frequency division control signal or a second frequency division control signal to a scanning output terminal of a current stage of the gate driving circuits based on signals from the first node and the second node, so that a level state of a gate control signal output by the gate driving circuit through the scanning output terminal is correspondingly controlled by a level state of the first frequency division control signal or a level state of the second frequency division control signal, thereby realizing control to the active pulse of the gate control signal. Then, when the gate driving circuit does not need to output an active pulse to enable the display panel using the gate driving circuit to realize the frequency division function, the presence or absence of the active pulse in the gate control signal can be controlled by controlling the level state of the first frequency division control signal or the second frequency division control signal, so as to control a transistor in the pixel driving circuit of the display panel using the pixel driving circuit not to be conducted, thereby preventing the corresponding sub-pixel from refreshing the display data and enabling the display panel to realize the frequency division function.
Specifically, the present application realizes the stage transmission setting through the stage transmission module included in the gate driving circuit. The gate driving circuit includes the output module, so that the output module outputs the first frequency division control signal and the second frequency division control signal through the scanning output terminal based on the signals from the first node and the second node in the stage transmission module to generate the gate control signal.
FIG. 1A to FIG. 1B are schematic diagrams of a structure of a gate driving unit according to an embodiment of the present application. The present application provides a gate driving unit 10, including a first frequency division control line FDL1, a second frequency division control line FDL2, and a plurality of cascaded stages of gate driving circuits.
The first frequency division control line FDL1 is configured to transmit a first frequency division control signal FD1.
The second frequency division control line FDL2 is configured to transmit a second frequency division control signal FD2.
The plurality of cascaded stages of gate driving circuits are configured to generate a plurality of gate control signals Scan. Optionally, each of the gate driving circuits includes a stage transmission module 11 and an output module 12.
The stage transmission module 11 is configured to receive a previous-stage stage transmission signal Cas, a first clock signal CK1 and a second clock signal CK2, and output a current-stage stage transmission signal Cas to a next stage of the gate driving circuits.
The output module 12 is electrically connected to the first frequency division control line FDL1 or the second frequency division control line FDL2, and electrically connected to a first node P and a second node Q in the stage transmission module 11. The output module 12 outputs the first frequency division control signal FD1 or the second frequency division control signal FD2 to a scanning output terminal of current stage of the gate driving circuits based on the signals from the first node P and the second node Q, so that the level state of the gate control signal Scan output by the gate driving circuit through the scanning output terminal is correspondingly controlled by the level state of the first frequency division control signal FD1 or the second frequency division control signal FD2, thereby controlling the active pulse of the gate control signal Scan.
Optionally, the (m-th)-stage stage transmission signal Cas(m) output by the m-th stage of the gate driving circuits through the stage transmission output terminal is output to the (m+A)-th stage of the gate driving circuits. The (m+A)-th stage of the gate driving circuits receives the (m-th)-stage stage transmission signal Cas(m), the first clock signal CK1 and the second clock signal CK2, and outputs the (m+A)-th stage transmission signal Cas(m+A). The m-th stage of the gate driving circuits is electrically connected to the first frequency division control line FDL1 to output the first frequency division control signal FD1 to the scanning output terminal of the m-th stage of the gate driving circuits, so that the level state of the m-th stage gate control signal Scan output by the m-th stage of the gate driving circuits through the scanning output terminal is correspondingly controlled by the level state of the first frequency division control signal FD1. The (m+A)-th stage of the gate driving circuits is electrically connected to the second frequency division control line FDL2 to output the second frequency division control signal FD2 to the scanning output terminal of the (m+A)-th stage of the gate driving circuits, so that the level state of the (m+A)-th stage gate control signal Scan(m+A) output by the (m+A)-th stage of the gate driving circuits through the scanning output terminal is correspondingly controlled by the level state of the second frequency division control signal FD2. Thus, the two cascaded stages of the gate driving circuits can each generate a corresponding gate control signal Scan based on the first frequency division control signal FD1 and the second frequency division control signal FD2, respectively. M and A satisfy: M≥1, and A≥1.
Optionally, FIG. 2A and FIG. 2B are timing diagrams corresponding to a gate driving unit according to an embodiment of the present application, and in order to enable a display panel using the gate driving unit 10 to achieve frequency division display, the first frequency division control signal FD1 is partially the same as the second frequency division control signal FD2.
Optionally, the transistor to which the gate control signal Scan generated by the gate driving unit 10 is applied is an P-type transistor, and the first frequency division control signal FD1 and the second frequency division control signal FD2 have the same period of being at the high-level state, so that the gate control signal Scan generated by the gate driving unit 10 based on the first frequency division control signal FD1 and the second frequency division control signal FD2 correspondingly has a time period of being at the high-level state, and then the transistor to which the gate control signal Scan is applied is non-conducted, so that the corresponding sub-pixel does not refresh the display data, thereby enabling the display panel to achieve the low-frequency display in the portion corresponding to the sub-pixel.
Optionally, the transistor to which the gate control signal Scan generated by the gate driving unit 10 is applied is an N-type transistor, and the first frequency division control signal FD1 and the second frequency division control signal FD2 have the same time period of being at the low-level state, so that the gate control signal Scan generated by the gate driving unit 10 based on the first frequency division control signal FD1 and the second frequency division control signal FD2 correspondingly has the low-level state, and then the transistor to which the gate control signal Scan is applied is non-conducted, so that the corresponding sub-pixel does not refresh the display data, thereby enabling the display panel to achieve the low-frequency display in the portion corresponding to the sub-pixel.
Optionally, with continued reference to FIG. 1B, the output module 12 includes a first output transistor Tso1 and a second output transistor Tso2.
A control terminal of the first output transistor Tso1 is electrically connected to the first node P, an input terminal of the first output transistor Tso1 is electrically connected to a first voltage terminal VGH, and an output terminal of the first output transistor Tso1 is electrically connected to the scanning output terminal.
A control terminal of the second output transistor Tso2 is electrically connected to the second node Q, an output terminal of the second output transistor Tso2 is electrically connected to the scanning output terminal, and an input terminal of the second output transistor Tso2 is electrically connected to the first frequency division control line FDL1 or the second frequency division control line FDL2, so that when the second output transistor Tso2 is conducted based on the signal from the second node Q, the first frequency division control signal FD1 or the second frequency division control signal FD2 is output to the scanning output terminal through the second output transistor Tso2.
Optionally, with continued reference to FIG. 1B, the stage transmission module 11 includes a first-node control module, a second-node control module, and a stage transmission output module.
The first-node control module is electrically connected to the first node P, and the first-node control module receives the first clock signal CK1 or the second clock signal CK2 to control the signal from the first node P.
Optionally, the first-node control module includes a first transistor T1 and a second transistor T2. An input terminal of the first transistor T1 is electrically connected to a second voltage terminal VGL. A control terminal of the second transistor T2 is electrically connected to the second node Q, an input terminal of the second transistor T2 is electrically connected to the control terminal of the first transistor T1, and an output terminal of the second transistor T2 is electrically connected to the output terminal of the first transistor T1. A control terminal of the first transistor T1 is electrically connected to the first clock signal line CKL1 or the second clock signal line CKL2.
The second-node control module is electrically connected to the second node Q, and the second-node control module receives the first clock signal CK1, the second clock signal CK2, and a previous-stage stage transmission signal to control a signal from the second node Q.
Optionally, the second-node control module includes a third transistor T3, a fourth transistor T4, and a fifth transistor T5. An input terminal of the third transistor T3 receives the previous-stage stage transmission signal, and an output terminal of the third transistor T3 is electrically connected to the second node Q. A control terminal of the fourth transistor T4 is electrically connected to the first node P, and an input terminal of the fourth transistor T4 is electrically connected to a first voltage terminal VGH. An input terminal of the fifth transistor T5 is electrically connected to an output terminal of the fourth transistor T4, and an output terminal of the fifth transistor T5 is electrically connected to the second node Q. A control terminal of the third transistor T3 is electrically connected to one of the first clock signal line CKL1 and the second clock signal line CKL2, and a control terminal of the fifth transistor T5 is electrically connected to the other of the first clock signal line CKL1 and the second clock signal line CKL2. Optionally, the control terminal of the third transistor T3 is electrically connected to the control terminal of the first transistor T1.
The stage transmission output module is electrically connected to the first node P, the second node Q and the stage transmission output terminal of the gate driving circuit. The stage transmission output module outputs the current-stage stage transmission signal to the next stage of the gate driving circuits through the stage transmission output terminal based on signals from the first node P and the second node Q.
Optionally, the stage transmission output module includes a first stage-transmission output transistor T6, a second stage-transmission output transistor T7, a first capacitor C1, and a second capacitor C2. A control terminal of the first stage-transmission output transistor T6 is electrically connected to the first node P, an input terminal of the first stage-transmission output transistor T6 is electrically connected to the first voltage terminal VGH, and an output terminal of the first stage-transmission output transistor T6 is electrically connected to the stage transmission output terminal. A control terminal of the second stage-transmission output transistor T7 is electrically connected to the second node Q, and an output terminal of the second stage-transmission output transistor T7 is electrically connected to the stage transmission output terminal; The first capacitor C1 is connected in series between the input terminal of the first stage-transmission output transistor T6 and the control terminal of the first stage-transmission output transistor T6. The second capacitor C2 is connected in series between the input terminal of the second stage-transmission output transistor T7 and the control terminal of the second stage-transmission output transistor T7.
Optionally, the input terminal of the second stage-transmission output transistor T7 may be electrically connected to the second voltage terminal VGL, and the input terminal of the second stage-transmission output transistor T7 may also be electrically connected to the first clock signal line CKL1 or the second clock signal line CKL2.
Optionally, the first stage-transmission output transistor T6 is a P-type transistor, and the voltage value supplied by the second voltage terminal VGL is less than the voltage value supplied by the first voltage terminal VGH.
Optionally, the transistor to which the gate control signal Scan is applied is a P-type transistor, and the active pulse of the gate control signal Scan correspondingly has a low-level state. The transistor to which the gate control signal Scan is applied is an N-type transistor, and the active pulse of the gate control signal Scan correspondingly has a high-level state.
Optionally, the stage transmission module 11 further includes a shielding module, and the shielding module includes a shielding transistor T8. A control terminal of the shielding transistor T8 is electrically connected to a third voltage terminal, an input terminal of the shielding transistor T8 is electrically connected to an output terminal of the third transistor T3 and an output terminal of the fifth transistor T5, and an output terminal of the shielding transistor T8 is electrically connected to a control terminal of the second stage-transmission output transistor T7. The second stage-transmission output transistor T7 is a P-type transistor, and the voltage value supplied by the third voltage terminal is equal to the voltage value supplied by the second voltage terminal VGL. The second stage-transmission output transistor T7 is an N-type transistor, and the voltage value supplied by the third voltage terminal is equal to the voltage value supplied by the first voltage terminal VGH.
Optionally, with continued reference to FIG. 1B, in the m-th stage of the gate driving circuits, the input terminal of the second output transistor Tso2 is electrically connected to the first frequency division control line FDL1. The first-node control module receives the first clock signal CK1, a control terminal of the first transistor T1 and a control terminal of the third transistor T3 are electrically connected to a first clock signal line CKL1 for transmitting the first clock signal CK1. A control terminal of the fifth transistor T5 and an input terminal of the second stage-transmission output transistor T7 are electrically connected to a second clock signal line CKL2 for transmitting the second clock signal CK2. for the (m+A) th stage of the gate driving circuits, the input terminal of the second output transistor Tso2 is electrically connected to the second frequency division control line FDL2. The first-node control module receives the second clock signal CK2, the control terminal of the first transistor T1 and the control terminal of the third transistor T3 are electrically connected to the second clock signal line CKL2, and the control terminal of the fifth transistor T5 and the input terminal of the second stage-transmission output transistor T7 are electrically connected to the first clock signal line CKL1, so that the (m+A)-th stage of the gate driving circuits that receives the (m-th)-stage stage transmission signal Cas(m) output by the m-th stage of the gate driving circuits and the m-th stage of the gate driving circuits can each generate a corresponding gate control signal Scan based on the second frequency division control signal FD2 and the first frequency division control signal FD1, respectively.
Optionally, with continued reference to FIG. 2A to FIG. 2B, in order to enable the two cascaded stages of the gate driving circuits to generate the corresponding gate control signals Scan based on the first frequency division control signal FD1 and the second frequency division control signal FD2, the second clock signal CK2 is partially the same as the first frequency division control signal FD1, and the first clock signal CK1 is partially the same as the second frequency division control signal FD2. That is, when the display panel to which the gate driving unit 10 is applied does not need frequency division display, the second clock signal CK2 and the first frequency division control signal FD1 are the same (i.e., both are at a low level or both are at a high level), and the first clock signal CK1 and the second frequency division control signal FD2 are the same (i.e., both are at a low level or both are at a high level). When the display panel to which the gate driving unit 10 is applied needs frequency division display, the second clock signal CK2 and the first frequency division control signal FD1 are different, the first clock signal CK1 and the second frequency division control signal FD2 are different, and the first frequency division control signal FD1 and the second frequency division control signal FD2 are the same (i.e., both are at a low level or both are at a high level).
Optionally, the m-th stage of the gate driving circuits and the (m+A)-th stage of the gate driving circuits may both be odd-numbered stages of the gate driving circuits (for example, m is an odd number, and A is an even number; or m is an even number, and A is an odd number; the m-th stage of the gate driving circuits and the (m+A)-th stage of the gate driving circuits form an interlaced stage transmission), so that the odd-numbered stages of the gate driving circuits generate corresponding gate control signals Scan based on the first frequency division control signal FD1 and the second frequency division control signal FD2. The m-th stage of the gate driving circuits and the (m+A)-th stage of the gate driving circuits may both be even-numbered stages of the gate driving circuits (for example, m is an odd number, and A is also an odd number; or m is an even number, and A is also an even number; the m-th stage of the gate driving circuits and the (m+A)-th stage of the gate driving circuits form an interlaced stage transmission), so that the even-numbered stages of the gate driving circuits generate corresponding gate control signals Scan based on the first frequency division control signal FD1 and the second frequency division control signal FD2. In addition, the m-th stage of the gate driving circuits may be one of an odd-numbered stage of the gate driving circuits and an even-numbered stage gate driving circuit, and the (m+A)-th stage of the gate driving circuits is the other of the odd-numbered stage of the gate driving circuits and the even-numbered stage of the gate driving circuits, so that the odd-numbered stage of the gate driving circuits and the even-numbered stage of the gate driving circuits generate the corresponding gate control signals Scan based on the first frequency division control signal FD1 and the second frequency division control signal FD2, respectively.
Optionally, in order to reduce the number of control signal lines used by the gate driving circuit, the first frequency division control line FDL1 may be electrically connected to the odd-numbered stages of the gate driving circuits, and the second frequency division control line FDL2 may be electrically connected to the even-numbered stages of the gate driving circuits, so that the odd-numbered stages of the gate driving circuits generate corresponding gate control signals Scan based on the first frequency division control signal FD1, and the even-numbered stages of the gate driving circuits generate corresponding gate control signals Scan based on the second frequency division control signal FD2.
Optionally, for odd-numbered stages of the gate driving circuits, the input terminal of the second output transistor Tso2 is electrically connected to the first frequency division control line FDL1. The first-node control module receives the first clock signal CK1. A control terminal of the first transistor T1 is electrically connected to a first clock signal line CKL1 for transmitting the first clock signal CK1. A control terminal of the third transistor T3 is electrically connected to the first clock signal line CKL1 for transmitting the first clock signal CK1. A control terminal of the fifth transistor T5 is electrically connected to a second clock signal line CKL2 for transmitting the second clock signal CK2. An input terminal of the second stage-transmission output transistor T7 is electrically connected to the second clock signal line CKL2. for even-numbered stages of the gate driving circuits, the input terminal of the second output transistor Tso2 is electrically connected to the second frequency division control line FDL2. The first-node control module receives the second clock signal CK2. A control terminal of the first transistor T1 is electrically connected to a second clock signal line CKL2 for transmitting the second clock signal CK2. A control terminal of the third transistor T3 is electrically connected to the second clock signal line CKL2. A control terminal of the fifth transistor T5 is electrically connected to the first clock signal line CKL1. An input terminal of the second stage-transmission output transistor T7 is electrically connected to the first clock signal line CKL1.
With continued reference to FIG. 1B and FIG. 2A, the working principle of the gate driving unit 10 will be described by taking an example in which the m-th stage of the gate driving circuits is electrically connected to the first frequency division control line FDL1, the (m+A)-th stage of the gate driving circuits is electrically connected to the second frequency division control line FDL2, each of the transistors included in the plurality of gate driving circuits is a P-type transistor, the transistors to which the gate control signals Scan are applied are P-type transistors, the plurality of gate driving circuits are transmitted in stages row by row, and the display panel to which the gate driving unit 10 is applied starts to achieve frequency division display in the (m+3)-th row.
In a first phase t1, the first frequency division control signal FD1 and the second clock signal CK2 are at a high level, the second frequency division control signal FD2 and the first clock signal CK1 are at a low level, the previous-stage stage transmission signal Cas(m-1) received by the m-th stage of the gate driving circuits is at a high level, and the (m-th)-stage stage transmission signal Cas(m) output by the m-th stage of the gate driving circuits received by the (m+1)-th stage of the gate driving circuits is at a high level.
In the m-th stage of the gate driving circuits, the first transistor T1 and the third transistor T3 are conducted based on the first clock signal CK1, the second voltage transmitted by the second voltage terminal VGL is transmitted to the first node P through the first transistor T1, the fourth transistor T4, the first stage-transmission output transistor T6, and the first output transistor Tso1 are conducted, and the first voltage transmitted by the first voltage terminal VGH is transmitted to the stage transmission output terminal through the first stage-transmission output transistor T6, so that the (m-th)-stage stage transmission signal Cas(m) output by the m-th stage of the gate driving circuits has a high-level state. The first voltage transmitted by the first voltage terminal VGH is output to the scanning output terminal through the first output transistor Tso1, so that the m-th stage gate control signal Scan(m) output by the m-th stage of the gate driving circuits has a high-level state. The previous-stage stage transmission signal Cas(m-1) received by the m-th stage of the gate driving circuits turns off the second transistor T2, the second stage-transmission output transistor T7, and the second output transistor Tso2. The fifth transistor T5 is turned off based on the second clock signal CK2.
In the (m+1)-th stage of the gate driving circuits, the first transistor T1 and the third transistor T3 are turned off based on the second clock signal CK2, the fourth transistor T4, the first stage-transmission output transistor T6, and the first output transistor Tso1 are remain turned on, the fifth transistor T5 is turned on based on the first clock signal CK1, and the first voltage transmitted by the first voltage terminal VGH is transmitted to the second node Q through the fourth transistor T4 and the fifth transistor T5. The first voltage transmitted by the first voltage terminal VGH is transmitted to the stage transmission output terminal through the first stage-transmission output transistor T6, so that the (m+1)-th stage transmission signal Cas(m+1) output by the (m+1)-th stage of the gate driving circuits has a high-level state. The first voltage transmitted by the first voltage terminal VGH is output to the scanning output terminal through the first output transistor Tso1, so that the (m+1)-th stage gate control signal Scan(m+1) output by the (m+1)-th stage of the gate driving circuits has a high-level state. The second transistor T2, the second stage-transmission output transistor T7, and the second output transistor Tso2 remain turned off.
In a second phase t2, the second clock signal CK2, the first frequency division control signal FD1 are at a low level, and the first clock signal CK1, the second frequency division control signal FD2, and the previous-stage stage transmission signal Cas(m-1) are at a high level.
In the m-th stage of the gate driving circuits, the first transistor T1 and the third transistor T3 are turned off based on the first clock signal CK1, the fourth transistor T4, the first stage-transmission output transistor T6, and the first output transistor Tso1 remain turned on, the fifth transistor T5 is turned on based on the second clock signal CK2, the first voltage transmitted by the first voltage terminal VGH is transmitted to the second node Q through the fourth transistor T4 and the fifth transistor T5, and the first voltage transmitted by the first voltage terminal VGH is transmitted to the stage transmission output terminal through the first stage-transmission output transistor T6, so that the (m-th)-stage stage transmission signal Cas(m) output by the m-th stage of the gate driving circuits has a high-level state. The first voltage transmitted by the first voltage terminal VGH is output to the scanning output terminal through the first output transistor Tso1, so that the m-th stage gate control signal Scan(m) output by the m-th stage of the gate driving circuits has a high-level state. The second transistor T2, the second stage-transmission output transistor T7, and the second output transistor Tso2 remain turned off.
The (m+1)-th stage of the gate driving circuits performs the same operations as the m-th stage of the gate driving circuits in the first phase t1.
In a third phase t3, the second clock signal CK2, the first frequency division control signal FD1 are at a high level, and the first clock signal CK1, the second frequency division control signal FD2, and the previous-stage stage transmission signal Cas(m-1) are at a low level.
In the m-th stage of the gate driving circuits, the first transistor T1 and the third transistor T3 are conducted based on the first clock signal CK1, the second voltage transmitted by the second voltage terminal VGL is transmitted to the first node P through the first transistor T1, the fourth transistor T4, the first stage-transmission output transistor T6, and the first output transistor Tso1 are conducted, and the first voltage transmitted by the first voltage terminal VGH is transmitted to the stage transmission output terminal through the first stage-transmission output transistor T6, so that the (m-th)-stage stage transmission signal Cas(m) output by the m-th stage of the gate driving circuits has a high-level state. The previous-stage stage transmission signal Cas(m-1) turns on the second transistor T2, the second stage-transmission output transistor T7, and the second output transistor Tso2, the first clock signal CK1 is transmitted to the first node P through the second transistor T2, the second clock signal CK2 is transmitted to the stage transmission output terminal through the second stage-transmission output transistor T7, and the first frequency division control signal FD1 is output to the scanning output terminal through the first output transistor Tso1, so that the m-th stage gate control signal Scan(m) output by the m-th stage of the gate driving circuits has a high-level state. The fifth transistor T5 is turned off based on the second clock signal CK2.
The (m+1)-th stage of the gate driving circuits performs the same operations as the m-th stage of the gate driving circuits in the second phase t2. The (m+2)-th stage of the gate driving circuits performs the same operations as the (m+1)-th stage of the gate driving circuits in the second phase t2.
In a fourth phase t4, the second clock signal CK2, the first frequency division control signal FD1 are at a low level, and the first clock signal CK1, the second frequency division control signal FD2, and the previous-stage stage transmission signal Cas(m-1) are at a high level.
In the m-th stage of the gate driving circuits, the first transistor T1 and the third transistor T3 are turned off based on the first clock signal CK1, the second capacitor C2 maintains the second stage-transmission output transistor T7 to be turned on, so that the transition of the second clock signal CK2 from a high level to a low level is coupled to the second node Q through the second capacitor C2, so as to further pull down the potential of the second node Q. The second transistor T2, the second stage-transmission output transistor T7, and the second output transistor Tso2 remain turned on, so that the first clock signal CK1 is transmitted to the first node P through the second transistor T2, and the first stage-transmission output transistor T6 and the first output transistor Tso1 are turned off. The second clock signal CK2 is output to the stage transmission output terminal through the second stage-transmission output transistor T7, so that the m-th-stage stage transmission signal Cas(m) output by the m-th stage of the gate driving circuits has a low-level state. The first frequency division control signal FD1 is output to the scanning output terminal through the second output transistor Tso2, so that the m-th stage gate control signal Scan(m) output by the m-th stage of the gate driving circuits has a low-level state.
The (m+1)-th stage of the gate driving circuits performs the same operations as the m-th stage of the gate driving circuits in the third phase t3. The (m+2)-th stage of the gate driving circuits performs the same operations as the (m+1)-th stage of the gate driving circuits in the third phase t3. The (m+3)-th stage of the gate driving circuits performs the same operations as the (m+2)-th stage of the gate driving circuits in the third phase t3.
In the fifth phase t5, the second clock signal CK2 and the first frequency division control signal FD1 are at a high level, the first clock signal CK1 and the second frequency division control signal FD2 are at a low level, and the previous-stage stage transmission signal Cas(m-1) is at a high level.
In the m-th stage of the gate driving circuits, the first transistor T1 and the third transistor T3 are conducted based on the first clock signal CK1, the second voltage transmitted by the second voltage terminal VGL is transmitted to the first node P through the first transistor T1, the fourth transistor T4, the first stage-transmission output transistor T6, and the first output transistor Tso1 are conducted, and the first voltage transmitted by the first voltage terminal VGH is transmitted to the stage transmission output terminal through the first stage-transmission output transistor T6, so that the (m-th)-stage stage transmission signal Cas(m) output by the m-th stage of the gate driving circuits has a high-level state. The first voltage transmitted by the first voltage terminal VGH is output to the scanning output terminal through the first output transistor Tso1, so that the m-th stage gate control signal Scan(m) output by the m-th stage of the gate driving circuits has a high-level state. The previous-stage stage transmission signal Cas(m-1) turns off the second transistor T2, the second stage-transmission output transistor T7, and the second output transistor Tso2. The fifth transistor T5 is turned off based on the second clock signal CK2.
The (m+1)-th stage of the gate driving circuits performs the same operations as the m-th stage of the gate driving circuits in the fourth phase t4. The (m+2)-th stage of the gate driving circuits performs the same operations as the (m+1)-th stage of the gate driving circuits in the fourth phase t4. The (m+3)-th stage of the gate driving circuits performs the same operations as the (m+2)-th stage of the gate driving circuits in the fourth phase t4.
In a sixth phase t6, the second clock signal CK2 and the first frequency division control signal FD1 are at a low level, and the first clock signal CK1, the second frequency division control signal FD2, and the previous-stage stage transmission signal Cas(m-1) are at a high level.
The m-th stage of the gate driving circuits performs the same operations as in the second phase t2. The (m+1)-th stage of the gate driving circuits performs the same operations as the m-th stage of the gate driving circuits in the fifth phase t5. The (m+2)-th stage of the gate driving circuits performs the same operations as the (m+1)-th stage of the gate driving circuits in the fifth phase t5. The (m+3)-th stage of the gate driving circuits performs the same operations as the (m+2)-th stage of the gate driving circuits in the fifth phase t5.
In a seventh phase t7, the second clock signal CK2, the first frequency division control signal FD1, and the second frequency division control signal FD2 are at a high level, and the first clock signal CK1 and the previous-stage stage transmission signal Cas(m-1) are at a low level.
The m-th stage of the gate driving circuits performs the same operations as in the first phase t1. The (m+1)-th stage of the gate driving circuits performs the same operations as the m-th stage of the gate driving circuits in the sixth phase t6. The (m+2)-th stage of the gate driving circuits performs the same operations as the (m+1)-th stage of the gate driving circuits in the sixth phase t6.
In the (m+3)-th stage of the gate driving circuits, the first transistor T1 and the third transistor T3 are turned off based on the second clock signal CK2, and the second capacitor C2 maintains the second stage-transmission output transistor T7 to be turned on, so that the transition of the first clock signal CK1 from high level to low level is coupled to the second node Q through the second capacitor C2, so as to further pull down the potential of the second node Q. The second transistor T2, the second stage-transmission output transistor T7, and the second output transistor Tso2 remains tured on, so that the second clock signal CK2 is transmitted to the first node P through the second transistor T2, and the first stage-transmission output transistor T6 and the first output transistor Tso1 are turned off. The first clock signal CK1 is output to the stage transmission output terminal through the second stage-transmission output transistor T7, so that the (m+3)-th-stage stage transmission signal Cas(m+3) output by the (m+3)-th stage of the gate driving circuits has a low-level state. The first frequency division control signal FD1 is output to the scanning output terminal through the second output transistor Tso2, so that the m-th stage gate control signal Scan(m+3) output by the (m+3)-th stage of the gate driving circuits has a high-level state.
Therefore, the (m+3)-th stage of the gate driving circuits can still provide the (m+3)-th-stage stage transmission signal Cas(m+3) to the next stage of the gate driving circuits, and the gate control signal Scan(m+3) output by the (m+3)-th stage of the gate driving circuits does not have an active pulse, so that the transistor electrically connected to the (m+3)-th stage of the gate driving circuits cannot be turned on, and then when the gate driving unit 10 is used in the display panel, the sub-pixel electrically connected to the (m+3)-th stage of the gate driving circuits cannot refresh the display data, so that the display panel can achieve frequency division display in the corresponding region.
In the eighth phase t8, the first frequency division control signal FD1 and the second frequency division control signal FD2 are kept at a high level, and the second clock signal CK2 and the first clock signal CK1 transition between a low-level state and a high-level state.
The a plurality of stages of the gate driving circuits (such as the (m+3)-th stage of the gate driving circuits to the (m+C)-th stage gate driving circuit) after the (m+3)-th stage of the gate driving circuits enable the output multi-stage stage transmission signals Cas(m+3) to Cas (m+C) to have active pulses in sequence based on the first frequency division control signal FD1, the second frequency division control signal FD2, the second clock signal CK2, and the first clock signal CK1. The gate control signals Scan(m+3) to Scan (m+C) output output by the a plurality of stages of the gate driving circuits (such as the (m+3)-th stage of the gate driving circuits to the (m+C)-th stage gate driving circuit) after the (m+3)-th stage of the gate driving circuits do not have active pulses. C is greater than or equal to 0.
Until at least one of the first frequency division control signal FD1 and the second frequency division control signal FD2 starts to transition from the high-level state to the low-level state, some of the plurality of stages of the gate driving circuits start to restore the output of active pulses. in the ninth phase t9 as shown in FIG. 3B, the second clock signal CK2 and the first frequency division control signal FD1 are at a high level, and the first clock signal CK1 and the second frequency division control signal FD2 are at a low level. The (m+C+1)-th stage of the gate driving circuits in the ninth phase t9 performs the same operations as the m-th stage of the gate driving circuits in the fourth phase t4, so that the (m+C+1)-th stage gate control signal Scan (m+C+1) output by the (m+C+1)-th stage of the gate driving circuits has an active pulse.
Optionally, that the previous-stage stage transmission signal is inverted can result in the case where the active pulse of the corresponding gate control signal Scan is at a high-level state.
It can be understood that in the first stage of the cascaded stages of gate driving circuits, the start signal STV may be used as a previous-stage stage transmission signal.
FIG. 3A to FIG. 3B are schematic diagrams of a structure of a display device according to an embodiment of the present application, FIG. 4 is a schematic diagram of a structure of a pixel driving circuit according to an embodiment of the present application, and FIG. 5A to FIG. 5B are timing diagrams corresponding to the display device according to an embodiment of the present application. The embodiments of the present application further provide a display device including any gate driving unit 10 as described above and a display panel.
Optionally, the display panel includes a display region and a non-display region 100a located outside the display region. The gate driving unit 10 may be located in the non-display region 100a.
The display panel includes a plurality of sub-pixels Pi and a plurality of first scanning lines SL1, the plurality of sub-pixels Pi include a plurality of light-emitting devices Di and a plurality of pixel driving circuits for driving the light-emitting devices Di to emit light, and the pixel driving circuit includes at least one transistor. The gate control signals Scan output by the plurality of gate driving circuits are transmitted to the control terminals of the transistors of the plurality of pixel driving circuits through the plurality of first scanning lines SL1, so that the display panel can control the plurality of sub-pixels Pi to realize frequency division display in a display cycle based on the gate control signals Scan.
Optionally, when the display panel implements frequency division display, a display cycle includes a write frame WF and at least one hold frame HF. In the write frame WF, the first frequency division control signal FD1 and the second frequency division control signal FD2 transition between a high-level state and a low-level state, so that the plurality of sub-pixels Pi can write display data in the write frame WF to update the image.
If the transistors to which the plurality of gate control signals Scan output by the gate driving unit 10 are applied are P-type transistors, in the blanking interval after the write frame WF or in at least one hold frame HF after the write frame WF, the first frequency division control signal FD1 and the second frequency division control signal FD2 may have a same time period of being at a high-level state, so that the sub-pixels Pi of the corresponding row do not refresh the written data. If the transistors to which the plurality of gate control signals Scan output by the gate driving unit 10 are applied are N-type transistors, in the blanking interval after the write frame WF or in at least one hold frame HF after the write frame WF, the first frequency division control signal FD1 and the second frequency division control signal FD2 may have a same time period of being at a low-level state, so that the sub-pixels Pi of the corresponding row do not refresh the written data.
Optionally, the blanking interval includes a horizontal blanking interval and a vertical blanking interval.
Optionally, the number of times that the first frequency division control signal FD1 and the second frequency division control signal FD2 maintain the same level state within each hold frame HF may be the same or different, and the moments when the first frequency division control signal FD1 and the second frequency division control signal FD2 maintain the same level state within each hold frame HF may be the same or different, so that the display panel may have different display frequencies corresponding to different rows in a display cycle, thereby realizing frequency division display at any position.
Optionally, the light-emitting device Di includes an organic light-emitting diode, a sub-millimeter light-emitting diode, a micro light-emitting diode, etc.
Optionally, a plurality of first scanning lines SL1 are arranged along the second direction y, each of the first scanning line SL1 extends along the first direction x intersecting the second direction y, and the plurality of first scanning lines SL1 are configured to transmit a plurality of gate control signals Scan.
with continued reference to FIG. 3A, the display panel includes a plurality of data lines DL electrically connected to the plurality of sub-pixels Pi, the plurality of data lines DL are arranged along the first direction x, each data line DL extends along the second direction y, and the plurality of data lines DL are configured to transmit a plurality of data signals.
With continued reference to FIG. 4, the pixel driving circuit includes a driving transistor Tdr and a data transistor Tda.
The driving transistor Tdr and the light-emitting device Di are connected in series between the first power supply line Vdd and the second power supply line Vss. The input terminal of the data transistor Tda is electrically connected to the corresponding data line DL. The output terminal of the data transistor Tda is electrically connected to the input terminal of the driving transistor Tdr.
Optionally, the control terminals of the data transistors Tda of the plurality of sub-pixels Pi may be electrically connected to the gate driving unit 10 through the first scanning line SL1, so as to control the data transistors Tda of the plurality of sub-pixels Pi to be turned on or turned off through the gate driving circuit, thereby controlling whether data is written into the control terminals of the driving transistors Tdr, so as to determine whether the sub-pixels Pi perform the operation of refreshing display data.
Optionally, with continued reference to FIG. 3A, FIG. 3B, and FIG. 4, the pixel driving circuit further includes a compensation transistor Tc, a reset transistor Ti1, an initialization transistor Ti2, a first light-emitting control transistor Ts1, and a second light-emitting control transistor Ts2.
An input terminal and an output terminal of the compensation transistor Tc are electrically connected between a control terminal of the driving transistor Tdr and an output terminal of the driving transistor Tdr, and the compensation transistor Tc is configured to enable the driving transistor Tdr to be connected in a form of a diode. Optionally, the compensation transistors Tc include an oxide transistor or a silicon transistor.
An input terminal and an output terminal of the reset transistor Ti1 are electrically connected between a first reset line and the control terminal of the driving transistor Tdr. The reset transistor Ti1 is configured to enable the first reset signal VI1 transmitted by the first reset line to be transmitted to the control terminal of the driving transistor Tdr, so as to reset the potential of the control terminal of the driving transistor Tdr. Optionally, the reset transistor Ti1 includes an oxide transistor or a silicon transistor.
An input terminal of the initial transistor Ti2 is electrically connected to the second reset line, and an output terminal of the initial transistor Ti2 is electrically connected to the light-emitting device Di. The initial transistor Ti2 is configured to transmit the second reset signal VI2 transmitted by the second reset line to the anode of the light-emitting device Di, so as to initialize the potential of the anode of the light-emitting device Di.
An input terminal and an output terminal of the first light-emitting control transistor Ts1 are electrically connected between the first power supply line Vdd and the input terminal of the driving transistor Tdr. An input terminal and an output terminal of the second light-emitting control transistor Ts2 are electrically connected between the light-emitting device Di and the output terminal of the driving transistor Tdr. The first light-emitting control transistor Ts1 and the second light-emitting control transistor Ts2 are configured to control a light-emitting moment of the light-emitting device Di.
Alternatively, the pixel driving circuit of each of the sub-pixels Pi further includes a third capacitor Cst connected in series between the first power supply line Vdd and the control terminal of the driving transistor Tdr.
Optionally, the pixel driving circuit of each of the sub-pixels Pi further includes a fourth capacitor Cboost connected in series between the control terminal of the driving transistor Tdr and the control terminal of the data transistor Tda.
Optionally, the pixel driving circuit of each of the sub-pixels Pi further includes a reset transistor Ti3, an input terminal of the reset transistor Ti3 is electrically connected to the third reset line, and an output terminal of the reset transistor Ti3 is electrically connected to the input terminal of the driving transistor Tdr. The control terminal of the reset transistor Ti3 is electrically connected to the control terminal of the initialization transistor Ti2, and the reset transistor Ti3 is configured to transmit the third reset signal VI3 transmitted by the third reset line to the input terminal of the driving transistor Tdr, so as to reset the potential of the input terminal of the driving transistor Tdr.
Optionally, the gate driving unit 10 included in the display panel may also be electrically connected to a control terminal of at least one of the compensation transistor Tc, the reset transistor Ti1, the initial transistor Ti2, the reset transistor Ti3, the first light-emitting control transistor Ts1, and the second light-emitting control transistor Ts2 of the plurality of sub-pixels Pi.
Optionally, the display panel further includes a plurality of light-emitting control lines EML, a plurality of second scanning lines SL2, a plurality of third scanning lines SL3, and a plurality of reset control lines VL. The plurality of light-emitting control lines EML, the plurality of second scanning lines SL2, the plurality of third scanning lines SL3, and the plurality of reset control lines are arranged along the second direction y, and all extend along the first direction x. The plurality of light-emitting control lines EML are configured to transmit a plurality of light-emitting control signals EMA. The plurality of second scanning lines SL2 are configured to transmit a plurality of second scanning signals Scan2. The plurality of third scanning lines SL3 are configured to transmit a plurality of third scanning signals Scan3. The plurality of reset control lines VL are configured to transmit a plurality of reset control signals EMB. The control terminals of the data transistors Tda of the sub-pixels Pi in the same row and the corresponding first scanning line SL1 are electrically connected to the gate driving unit 10. The control terminals of the compensation transistors Tc of the sub-pixels Pi in the same row are electrically connected to the corresponding second scanning line SL2. The control terminals of the reset transistors Ti1 of the sub-pixels Pi in the same row are electrically connected to the corresponding third scanning line SL3. The control terminals of the initialization transistors Ti2 of the sub-pixels Pi in the same row are electrically connected to the corresponding reset control line VL. The control terminals of the first light-emitting control transistors Ts1 and the second light-emitting control transistors Ts2 of the sub-pixels Pi in the same row are electrically connected to the corresponding light-emitting control line EML.
Taking the control terminal of the data transistor Tda being electrically connected to the gate driving unit 10 and the data transistor Tda being a P-type transistor as an example, the working principle of the frequency division display of the display panel in one display cycle are described. The write frame WF includes a first reset phase tim1, a second reset phase tim2, a data writing phase tim3, and a light-emitting phase tim4.
In the write frame WF, in order to realize that data can be normally written into the control terminals of the plurality of driving transistors Tdr included in the display panel, the first frequency division control signal FD1 transmitted by the first frequency division control line FDL1 which is electrically connected to the gate driving unit 10 has a transition between a high-level state and a low-level state, and the second frequency division control signal FD2 transmitted by the second frequency division control line FDL2 which is electrically connected to the gate driving unit 10 has a transition between a high-level state and a low-level state, so that the gate driving unit 10 can output a plurality of stages of gate control signals Scan having active pulses in the write frame WF. Thus, in the write frame WF, each row of sub-pixels Pi are respectively subjected to the first reset phase tim1, the second reset phase tim2, the data writing phase tim3, and the light-emitting phase tim4.
The working principle of various phases of the write frame WF will be illustrated by taking a row of a plurality of sub-pixels Pi as an example, as shown in FIG. 5A.
In the first reset phase tim1, the initial transistor Ti2 and the reset transistor Ti3 are turned on based on the corresponding reset control signal EMB, the compensation transistor Tc is turned on based on the corresponding second scanning signal Scan2, so that the anode of the light-emitting device Di is reset based on the second reset signal VI2, and the input terminal, the output terminal and the control terminal of the driving transistor Tdr are reset based on the third reset signal VI3.
In the second reset phase tim2, the reset transistor Ti1 is turned on based on the corresponding third scanning signal Scan3, and the compensation transistor Tc is turned on based on the corresponding second scanning signal Scan2, so that the output terminal and the control terminal of the driving transistor Tdr are reset based on the second reset signal VI2.
In the data writing phase tim3, the data transistor Tda is turned on based on the corresponding first scanning signal Scan, and the compensation transistor Tc is turned on based on the corresponding second scanning signal Scan2, so that the data signal Vdata can be written into the control terminal of the driving transistor Tdr.
In the light-emitting phase tim4, the first light-emitting control transistor Ts1 and the second light-emitting control transistor Ts1 are turned on based on a light-emitting control signal EMA, so that the driving transistor Tdr generates a driving current to drive the corresponding light-emitting device Di to emit light.
Optionally, a third reset phase tin is further included between the light-emitting phase tim4 and the data writing phase tim3. In the third reset phase tin, the initial transistor Ti2 and the reset transistor Ti3 are turned on based on the corresponding reset control signal EMB, so that the anode of the light-emitting device Di is reset based on the second reset signal VI2, and the input terminal and the output terminal of the driving transistor Tdr are reset based on the third reset signal VI3.
Optionally, the first frequency division control signal FD1 and the second frequency division control signal FD2 start to be at a high-level state at the first frequency division moment tfd1 (if the transistor to which the gate control signal Scan is applied is N-type transistor, the first frequency division control signal FD1 and the second frequency division control signal FD2 start to be in a low-level state at the first frequency division moment tfd1), start to have transitions of a high-level state and a low-level state at the second frequency division moment tfd2, respectively, and start to be at a high-level state again at the third frequency division moment tfd3 (if the transistor to which the gate control signal Scan is applied is N-type transistor, the first frequency division control signal FD1 and the second frequency division control signal FD2 start to be at a low-level state again at the third frequency division moment tfd3). The first frequency division moment tfd1 may correspond to a vertical blanking interval or a horizontal blanking interval, the second frequency division moment tfd2 may correspond to a vertical blanking interval or a horizontal blanking interval, and the third frequency division moment tfd3 may correspond to a vertical blanking interval or a horizontal blanking interval.
With continued reference to FIG. 5A and FIG. 5B, the working principle of the display panel in the hold frame HF is described by using an example in which the first frequency division moment tfd1 corresponds to the vertical blanking interval, the second frequency division moment tfd2 and the third frequency division moment tfd3 correspond to the horizontal blanking interval, and the first frequency division moment tfd1, the second frequency division moment tfd2, and the third frequency division moment tfd3 are all located within the same hold frame HF. For the convenience of description, a plurality of stages of the gate driving circuits corresponding to a time period which is located between the first frequency division moment tfd1 and the second frequency division moment tfd2 within the first hold frame HF and corresponds to the first frequency division control signal FD1 and the second frequency division control signal FD2 being at the high-level state are denoted as the first stage of the gate driving circuits to the m-th stage of the gate driving circuits. A plurality of stages of the gate driving circuits corresponding to a time period which is after the second frequency division moment tfd2 within the first hold frame HF1 and corresponds to the first frequency division control signal FD1 and the second frequency division control signal FD2 having transitions of a high-level state and a low-level state, respectively, are denoted as the (m+1)-th stage of the gate driving circuits to the (m+n)-th stage of the gate driving circuits. A plurality of stages of the gate driving circuits corresponding to a time period which is after the third frequency division moment tfd3 within the first hold frame HF1 and corresponds to the first frequency division control signal FD1 and the second frequency division control signal FD2 being at the high-level state again are denoted as the (m+n+1)-th stage of the gate driving circuits to the z-th stage of the gate driving circuits. The plurality of sub-pixels Pi in the first row to the m-th row in the display panel are electrically connected to the first stage of the gate driving circuits to the m-th stage of the gate driving circuits. The plurality of sub-pixels Pi in the (m+1)-th row to the (m+n)-th row are electrically connected to the (m+1)-th stage of the gate driving circuits to the (m+n)-th stage of the gate driving circuits. The plurality of sub-pixels Pi in the (m+n+1)-th row to the z-th row is electrically connected to the (m+n+1)-th stage of the gate driving circuits to the z-th stage of the gate driving circuits.
Then, in the first hold frame HF1, the gate control signals Scan (1) to Scan(m) generated by the first stage of the gate driving circuits to the m-th stage of the gate driving circuits do not output active pulses, and the data transistors Tda of the plurality of sub-pixels Pi in the first row to the m-th row are turned off, so that the plurality of sub-pixels Pi in the first row to the m-th row maintain the display image of the write frame WF. The gate control signals Scan (m+1) to Scan (m+n) generated by the (m+1)-th stage of the gate driving circuits to the (m+n)-th stage of the gate driving circuits output active pulses, and the plurality of sub-pixels Pi in the (m+1)-th row to the (m+n)-th row undergo various stages of the write frame WF in the first hold frame HF1, so that the plurality of sub-pixels Pi in the (m+1)-th row to the (m+n)-th row display images different from the images displayed in the write frame WF in the first hold frame HF1. The gate control signals Scan(m+n+1) to Scan(z) generated by the (m+n+1)-th stage of the gate driving circuits to the z-th stage of the gate driving circuits do not output active pulses, and the data transistors Tda of the plurality of sub-pixels Pi in the (m+n+1)-th row to the z-th row are turned off in the first hold frame HF1, so that the plurality of sub-pixels Pi in the (m+n+1)-th row to the z-th row maintain the display image of the write frame WF in the first hold frame HF1.
With continued reference to FIG. 5A, Vgdb represents the voltage difference between the gate and drain of the driving transistor Tdr when the low-frequency display region does not stop refreshing the display data in the hold frame HF in the prior art, and Scanb represents the gate control signal applied when the low-frequency display region does not stop refreshing the display data in the hold frame HF in the prior art. Vgd represents the voltage difference between the gate and drain of the driving transistor Tdr when the low-frequency display region stop refreshing the display data in the hold frame HF in the present application, and Scan represents the gate control signal applied when the low-frequency display region stops refreshing the display data in the hold frame HF in the present application. Since the voltage state of the voltage difference between the gate and drain of the driving transistor Tdr has a transient bias voltage to the driving transistor Tdr, causing that the threshold of the driving transistor Tdr is shifted. The positive voltage difference between the gate and drain of the driving transistor Tdr causes a positive shift in the threshold voltage of the driving transistor Tdr, as shown by ①, ③, ⑤, and ⑦ in FIG. 5A; The negative offset of voltage difference between the gate and drain of the driving transistor Tdr causes a negative shift in the threshold voltage of the driving transistor Tdr, as shown in ②, ④, and ⑥ in FIG. 5A. In the prior art, processes ④ and ⑥ are added to balance the influence of ② and ⑦ on the bias voltage of the driving transistor Tdr. However, in the prior art, the low-frequency display region does not stop refreshing the display data in the hold frame HF (that is, in the prior art, the gate control signals Scan (1) to Scan(m) generated by the first stage of the gate driving circuits to the m-th stage of the gate driving circuits still output active pulses, and the gate control signals Scan(m+n+1) to Scan(z) generated by the (m+n+1)-th stage of the gate driving circuits to the z-th stage of the gate driving circuits still output active pulses). Compared with the present application in which the low-frequency display region stops refreshing the display data in the hold frame HF (for example, the gate control signals Scan (1) to Scan(m) generated by the first stage of the gate driving circuits to the m-th stage of the gate driving circuits in the present application do not output active pulses, and the gate control signals Scan(m+n+1) to Scan(z) generated by the (m+n+1)-th stage of the gate driving circuits to the z-th stage of the gate driving circuits do not output active pulses), the process ⑤ is added in the prior art, and the addition of process ⑤ will weaken the effects of processes ④ and ⑥, thereby deteriorating the shift of the threshold voltage Vth and causing the deterioration of the flicker. However, the present application has no process ⑤, so the shift of the threshold voltage Vth will not be deteriorated, so the present application stops outputting the active pulse of the gate control signal Scan in the corresponding low-frequency display region, which is beneficial to improve the flicker problem.
Optionally, a state where both the first frequency division control signal FD1 and the second frequency division control signal FD2 are at a high level after the third frequency division moment tfd3 may last until within the second hold frame HF2 after the first hold frame HF1. Optionally, a state where both the first frequency division control signal FD1 and the second frequency division control signal FD2 are at a high level after the third frequency division moment tfd3 may last until within the vertical blanking interval.
Taking the case as an example, where the state where both the first frequency division control signal FD1 and the second frequency division control signal FD2 are at a high level after the third frequency division moment tfd3 can last until within the vertical blanking interval. in the second hold frame HF2, the first frequency division control signal FD1 and the second frequency division control signal FD2 will again be at a high-level state simultaneously at the fourth frequency division moment tfd4. Before the fourth frequency division moment tfd4, the plurality of stage of the gate driving circuits corresponding to the first frequency division control signal FD1 and the second frequency division control signal FD2 having transitions of high-level states and low-level states are the first stage of the gate driving circuits to the (m+n) th stage gate driving circuit. After the fourth frequency division moment tfd4, the plurality of stages of the gate driving circuits corresponding to the first frequency division control signal FD1 and the second frequency division control signal FD2 having both high-level states are the (m+n+1)-th stage of the gate driving circuits to the (z)-th stage of the gate driving circuits.
Then, in the second hold frame HF2, the plurality of sub-pixels Pi in the first row to the (m+n) th row turn on the data transistor Tda based on the active pulses of the gate control signals Scan (1) to Scan (m+n) generated by the first stage of the gate driving circuits to the (m+n)-th stage of the gate driving circuits, so that the plurality of sub-pixels Pi in the first row to the (m+n)-th row display images different from the images displayed of the write frame WF in the second hold frame HF2. The gate control signals Scan(m+n+1) to Scan(z) generated by the (m+n+1)-th stage of the gate driving circuits to the z-th stage of the gate driving circuits do not output active pulses, so that the plurality of sub-pixels Pi in the (m+n+1)-th row to the z-th row maintain the display image of the write frame WF.
Similarly, the working principle of remaining hold frames HF in the display cycle can be obtained.
Thus, in the display cycle, the plurality of sub-pixels Pi in the first row to the m-th row may be used to implement display at a first frequency, the plurality of sub-pixels Pi in the (m+1)-th row to the (m+n)-th row may be used to implement display at a second frequency, and the plurality of sub-pixels Pi of the (m+n+1)-th row to the z-th row may be used to implement display at a third frequency.
Alternatively, the first frequency may be greater than, less than, or equal to the second frequency such that the first display region and the second display region may display images at different frequencies or the same frequency in the display cycle. Alternatively, the third frequency may be equal to the first frequency or the second frequency. Alternatively, the third frequency may be different from both the first frequency and the second frequency.
Optionally, the first frequency may be 1 Hz to 360 Hz, the second frequency may be 1 Hz to 360 Hz, and the third frequency may be 1Hz to 360 Hz. Optionally, the first frequency may be 60 Hz, so that the plurality of sub-pixels Pi in the first row to the m-th row may be used to display a display image with a lower refresh frequency (for example, used to continuously display power information, time information, certain signal state information (such as WI-FI information, traffic information, Bluetooth information, etc.), bullet screen messages, etc.). The second frequency may be 120 Hz, so that the plurality of sub-pixels Pi in the (m+1)-th row to the (m+n)-th row may be used to display a display image (such as a movie image or a game image) with a relative high refresh frequency. The third frequency may be 30 Hz, so that the plurality of sub-pixels Pi in the (m+n+1)-th row to the z-th row may be used to display a display image (such as information (such as a keyboard, a handwriting box, etc.) for implementing an information input function, a text box, a comment region, etc.) which has a refresh frequency different from the refresh frequencies of the first display region and the second display region, as shown in FIG. 3B.
Z may be less than or equal to the number of rows of the sub-pixels Pi included in the display panel. In addition, (m+n) may be less than or equal to the number of rows of sub-pixels Pi included in the display panel. That is, the number of sub-display regions having different display frequencies in the display panel is greater than or equal to 2. If (m+n) is equal to the number of rows of the sub-pixels Pi included in the display panel, the display panel includes two sub-display regions with different display frequencies. If z is equal to the number of rows of sub-pixels Pi included in the display panel, the display panel includes three sub-display regions with different display frequencies; If z is less than the number of rows of sub-pixels Pi included in the display panel, and the display panel includes at least four sub-display regions with different display frequencies. It should be understood that a plurality of sub-pixels Pi included in a row may be used as a sub-display region, and a plurality of sub-pixels Pi included in successive rows may also be used as a sub-display region.
It should be understood that the number of sub-display regions of the display panel in each of display cycles may be different, and correspondingly frequency division positions may be different, so that the display panel is applicable to different application scenarios.
Specific examples have been used in the context to illustrate the principles and implementations of the present application, and the descriptions of the embodiments are only used to aid in the understanding of the methods and core ideas of the present application. Meanwhile, for technical personnel in this field, there may be changes in the specific implementation methods and disclosure scope based on the ideas of this disclosure. In summary, the content of this specification should not be understood as limiting this disclosure.

Claims

A gate driving unit, comprising a first frequency division control line for transmitting a first frequency division control signal, a second frequency division control line for transmitting a second frequency division control signal, and a plurality of cascaded stages of gate driving circuits, wherein each of the cascaded stages of gate driving circuits comprises:
a stage transmission module configured to receive a previous-stage stage transmission signal, a first clock signal, and a second clock signal, and output a current-stage stage transmission signal to a next stage of the gate driving circuits; and

an output module electrically connected to the first frequency division control line or the second frequency division control line and electrically connected to a first node and a second node in the stage transmission module, wherein the output module is configured to output the first frequency division control signal or the second frequency division control signal to a scanning output terminal of a current stage of the gate driving circuits based on signals from the first node and the second node.
The gate driving unit as claimed in claim 1, wherein the first frequency division control line is electrically connected to odd-numbered stages of the gate driving circuits, and the second frequency division control line is electrically connected to even-numbered stages of the gate driving circuits;
wherein the first frequency division control signal is partially the same as the second frequency division control signal.
The gate driving unit as claimed in claim 2, wherein the output module comprises:
a first output transistor, wherein a control terminal of the first output transistor is electrically connected to the first node, an input terminal of the first output transistor is electrically connected to a first voltage terminal, and an output terminal of the first output transistor is electrically connected to the scanning output terminal; and

a second output transistor, wherein a control terminal of the second output transistor is electrically connected to the second node, and an output terminal of the second output transistor is electrically connected to the scanning output terminal;

wherein input terminals of the second output transistors in odd-numbered stages of the gate driving circuits are electrically connected to the first frequency division control line, and input terminals of the second output transistors in even-numbered stages of the gate driving circuits are electrically connected to the second frequency division control line.
The gate driving unit as claimed in claim 2, wherein the stage transmission module comprises:
a first-node control module electrically connected to the first node, wherein the first-node control module is configured to receive the first clock signal or the second clock signal to control the signal from the first node;

a second-node control module electrically connected to the second node, wherein the second-node control module is configured to receive the first clock signal, the second clock signal, and the previous-stage stage transmission signal to control the signal from the second node; and

a stage transmission output module electrically connected to the first node, the second node, and a stage transmission output terminal of the gate driving circuit, wherein the stage transmission output module is configured to output the current-stage stage transmission signal to the next stage of the gate driving circuits through the stage transmission output terminal based on the signals of the first node and the second node.
The gate driving unit as claimed in claim 4, wherein the first-node control modules in odd-numbered stages of the gate driving circuits are configured to receive the first clock signal, and the first-node control modules in even-numbered stages of the gate driving circuits are configured to receive the second clock signal;
wherein the first clock signal is partially the same as the second frequency division control signal, and the second clock signal is partially the same as the first frequency division control signal.
The gate driving unit as claimed in claim 4, wherein the first-node control module comprises:
a first transistor, wherein an input terminal of the first transistor is electrically connected to a second voltage terminal; and

a second transistor, wherein a control terminal of the second transistor is electrically connected to the second node, an input terminal of the second transistor is electrically connected to a control terminal of the first transistor, and an output terminal of the second transistor is electrically connected to an output terminal of the first transistor;

wherein the control terminals of the first transistors in odd-numbered stages of the gate driving circuits are electrically connected to a first clock signal line for transmitting the first clock signal, and the control terminals of the first transistors in even-numbered stages of the gate driving circuits are electrically connected to a second clock signal line for transmitting the second clock signal.
The gate driving unit as claimed in claim 4, wherein the second-node control module comprises:
a third transistor, wherein an input terminal of the third transistor is configured to receive the previous-stage stage transmission signal, and an output terminal of the third transistor is electrically connected to the second node;

a fourth transistor, wherein a control terminal of the fourth transistor is electrically connected to the first node, and an input terminal of the fourth transistor is electrically connected to a first voltage terminal; and

a fifth transistor, wherein an input terminal of the fifth transistor is electrically connected to the output terminal of the fourth transistor, and an output terminal of the fifth transistor is electrically connected to the second node;

wherein control terminals of the third transistors in the odd-numbered stages of the gate driving circuits are electrically connected to a first clock signal line for transmitting the first clock signal, and control terminals of the fifth transistors in the odd-numbered stages of the gate driving circuits are electrically connected to a second clock signal line for transmitting the second clock signal; control terminals of the third transistors in even-numbered stages of the gate driving circuits are electrically connected to the second clock signal line, and control terminals of the fifth transistors in even-numbered stages of the gate driving circuits are electrically connected to the first clock signal line.
The gate driving unit as claimed in claim 7, wherein the stage transmission output module comprises:
a first stage-transmission output transistor, wherein a control terminal of the first stage-transmission output transistor is electrically connected to the first node, an input terminal of the first stage-transmission output transistor is electrically connected to the first voltage terminal, and an output terminal of the first stage-transmission output transistor is electrically connected to the stage transmission output terminal;

a second stage-transmission output transistor, wherein a control terminal of the second stage-transmission output transistor is electrically connected to the second node, and an output terminal of the second stage-transmission output transistor is electrically connected to the stage transmission output terminal;

a first capacitor connected in series between the input terminal of the first stage-transmission output transistor and the control terminal of the first stage-transmission output transistor; and

a second capacitor connected in series between the input terminal of the second stage-transmission output transistor and the control terminal of the second stage-transmission output transistor;

wherein the input terminals of the second stage-transmission output transistors in odd-numbered stages of the gate driving circuits are electrically connected to the second clock signal line, and the input terminals of the second stage-transmission output transistors in even-numbered stages of the gate driving circuits are electrically connected to the first clock signal line.
The gate driving unit as claimed in claim 8, wherein the stage transmission module further comprises:
a shielding module comprising a shielding transistor, wherein a control terminal of the shielding transistor is electrically connected to a third voltage terminal, an input terminal of the shielding transistor is electrically connected to the output terminal of the third transistor and the output terminal of the fifth transistor, and an output terminal of the shielding transistor is electrically connected to the control terminal of the second stage-transmission output transistor.
A display device, comprising:
a gate driving unit, wherein the gate driving unit comprises a first frequency division control line for transmitting a first frequency division control signal, a second frequency division control line for transmitting a second frequency division control signal, and a plurality of cascaded stages of gate driving circuits, and each of the cascaded stages of gate driving circuits comprises a stage transmission module and an output module; the stage transmission module is configured to receive a previous-stage stage transmission signal, a first clock signal, and a second clock signal, and output a current-stage stage transmission signal to a next stage of the gate driving circuits; and the output module is electrically connected to the first frequency division control line or the second frequency division control line, and is electrically connected to a first node and a second node in the stage transmission module, and the output module is configured to output the first frequency division control signal or the second frequency division control signal to a scanning output terminal of a current stage of the gate driving circuits based on signals from the first node and the second node; and

a display panel comprising a plurality of sub-pixels and a plurality of first scanning lines, wherein the plurality of sub-pixels comprise a plurality of light-emitting devices and a plurality of pixel driving circuits for driving the light-emitting devices to emit light, and each of the pixel driving circuits comprises at least one transistor;

wherein gate control signals output by the cascaded stages of gate driving circuits are transmitted to control terminals of the transistors of the plurality of pixel driving circuits through the plurality of first scanning lines.
The display device as claimed in claim 10, wherein a display cycle of the display panel comprises a write frame and at least one hold frame; within a blanking interval after a write frame of the display panel or within the at least one hold frames after the write frame, the first frequency division control signal and the second frequency division control signal have a same time period of being at a high-level state.
The display device as claimed in claim 10, wherein each of the pixel driving circuits comprises a driving transistor and a data transistor, the driving transistor and a corresponding one of the light-emitting devices are connected in series between a first power supply line and a second power supply line, an input terminal of the data transistor is electrically connected to a corresponding data line, and an output terminal of the data transistor is electrically connected to an input terminal of the driving transistor;
wherein control terminals of the data transistors of the plurality of sub-pixels are electrically connected to the gate driving unit through the first scanning lines.
The display device as claimed in claim 10, wherein the first frequency division control line is electrically connected to odd-numbered stages of the gate driving circuits, and the second frequency division control line is electrically connected to even-numbered stages of the gate driving circuits;
wherein the first frequency division control signal is partially the same as the second frequency division control signal.
The display device as claimed in claim 13, wherein the output module comprises:
a first output transistor, wherein a control terminal of the first output transistor is electrically connected to the first node, an input terminal of the first output transistor is electrically connected to a first voltage terminal, and an output terminal of the first output transistor is electrically connected to the scanning output terminal; and

a second output transistor, wherein a control terminal of the second output transistor is electrically connected to the second node, and an output terminal of the second output transistor is electrically connected to the scanning output terminal;

wherein input terminals of the second output transistors in odd-numbered stages of the gate driving circuits are electrically connected to the first frequency division control line, and input terminals of the second output transistors in even-numbered stages of the gate driving circuits are electrically connected to the second frequency division control line.
The display device as claimed in claim 13, wherein the stage transmission module comprises:
a first-node control module electrically connected to the first node, wherein the first-node control module is configured to receive the first clock signal or the second clock signal to control the signal from the first node;

a second-node control module electrically connected to the second node, wherein the second-node control module is configured to receive the first clock signal, the second clock signal and the previous-stage stage transmission signal to control the signal from the second node; and

a stage transmission output module electrically connected to the first node, the second node, and a stage transmission output terminal of the gate driving circuit, wherein the stage transmission output module is configured to output the current-stage stage transmission signal to the next stage of the gate driving circuits through the stage transmission output terminal based on the signals of the first node and the second node.
The display device as claimed in claim 15, wherein the first-node control modules in odd-numbered stages of the gate driving circuits are configured to receive the first clock signal, and the first-node control modules in even-numbered stages of the gate driving circuits are configured to receive the second clock signal;
wherein the first clock signal is partially the same as the second frequency division control signal, and the second clock signal is partially the same as the first frequency division control signal.