EP4690830A1

EP4690830A1 - High dynamic range solid-state imaging device with a signal processing circuit switchable between an active mode and an idle mode

Info

Publication number: EP4690830A1
Application number: EP24710107.4A
Authority: EP
Inventors: Erik Robert JOHANSSON
Original assignee: Sony Europe BV; Sony Semiconductor Solutions Corp
Current assignee: Sony Europe BV; Sony Semiconductor Solutions Corp
Priority date: 2023-03-31
Filing date: 2024-03-13
Publication date: 2026-02-11
Also published as: WO2024199996A1

Abstract

A solid-state imaging device includes a plurality of pixel circuits. Each pixel circuit outputs an analog pixel signal on a data signal line, wherein a voltage level of the pixel signal depends on an intensity of incident radiation detected in an exposure period. A group signal processing circuit is switchable between an active mode and an idle mode. In the active mode, the group signal processing circuit converts the pixel signal transmitted through the data signal line into a digital pixel value. In the idle mode the group signal processing circuit consumes less power than in the active mode. A group control circuit controls the group signal processing circuit to switch to the idle mode when a digital pixel value obtained in the active mode fulfills a predefined condition.

Description

HIGH DYNAMIC RANGE SOLID-STATE IMAGING DEVICE WITH A SIGNAL PROCESSING CIRCUIT SWITCHABLE BETWEEN AN ACTIVE

MODE AND AN IDLE MODE

The present disclosure relates to a high dynamic range (HDR) solid-stage imaging device having active pixel circuits outputting analog pixel signals and a group signal processing circuit for processing the analog pixel signals. In particular, the present disclosure relates to control of the group signal processing circuit.

BACKGROUND

An image sensor assembly for a solid-state imaging device includes photoelectric conversion elements that generate photocurrents proportional to the intensity of incident radiation. Active pixel circuits convert the photocurrents to analog pixel signals, wherein within a sensitivity range of the analog pixel circuit, a voltage of the analog pixel signal is a monotonically increasing function of the photocurrent. Via data signal lines, the analog pixel signals of active pixel circuits belonging to a same pixel column are sequentially transmitted to a column signal processing unit. The column signal processing unit converts the received analog pixel signals into digital pixel values. A HDR solid-state imaging device provides each active pixel circuit with different sensitivity ranges and compiles a single HDR image from two or more frames sequentially read out from the active pixel circuits.

SUMMARY

When a HDR image is obtained from n readouts, power consumption for obtaining one single HDR image is n times the power consumption of a single, non-HDR image. The present disclosure mitigates such shortcomings of the prior art. In particular, the present disclosure provides a solid-state imaging device in which a group control circuit assesses digital pixel values obtained from the analog pixel signals of the active pixel circuits in a multi -capture process. Depending on the result of the assessment, the group control circuit decides whether a further readout from a particular pixel circuit can add further information to the information already obtained. By disabling parts of the column signal processing unit during redundant pixel readout cycles, power consumption for obtaining HDR images from active pixel circuits can be reduced.

Accordingly, a solid-state imaging device includes a plurality of pixel circuits. Each pixel circuit outputs an analog pixel signal on a data signal line, wherein a voltage level of the pixel signal depends on an intensity of incident radiation detected in an exposure period. A group signal processing circuit is switchable between an active mode and an idle mode. In the active mode, the group signal processing circuit converts the pixel signal transmitted through the data signal line into a digital pixel value. In the idle mode the group signal processing circuit consumes less electrical power than in the active mode. A group control circuit controls the group signal processing circuit to switch to the idle mode when a digital pixel value obtained in the active mode fulfdls a predefined condition.

In the embodiments of the present disclosure the group control circuit can selectively disable and/or switch off at least a part of the group signal processing circuit, when a digital pixel value indicates that any further readout of the pixel circuit is redundant. The total current consumption for compiling HDR images can be reduced without compromising image quality.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the disclosure and many of the advantages associated therewith will be obtained by reference to the following detailed description in conjunction with the accompanying drawings, in which:

FIG. l is a schematic block diagram illustrating an imaging apparatus as an example for an electronic device including a solid-state imaging device with active pixel circuits, in accordance with the embodiments.

FIG. 2 is a simplified block diagram illustrating a configuration example of a HDR solid-state imaging device that switches off or disables portions of a group signal processing circuit during redundant pixel readout cycles, in accordance with an embodiment.

FIG. 3 is a schematic diagram illustrating an embodiment in which a solid-state imaging device has a two- layer structure in a stacked CIS configuration.

FIG. 4 is a simplified block diagram illustrating a configuration example of a portion of a HDR solid-state imaging device that switches off or disables portions of a group signal processing circuit during redundant pixel readout cycles, in accordance with an embodiment.

FIG. 5A is a diagram illustrating a method for omitting processing redundant readouts of active pixel circuits in response to values obtained in previous readouts, in accordance with an embodiment.

FIG. 5B is a table for explaining the method illustrated with reference to FIG. 5A.

FIG. 6 is a simplified block diagram illustrating a configuration example of a HDR solid-state imaging device that disables and/or switches off portions of a group signal processing circuit during redundant pixel readouts, in accordance with an embodiment concerning group signal processing circuits having arithmetic logic units.

FIG. 7 is a simplified circuit diagram of a gate circuit configured to temporarily disconnect a constant current source from a digital signal line for redundant pixel readouts, in accordance with an embodiment.

FIG. 8 is a simplified circuit diagram of a latch circuit and a comparator circuit configured to be temporarily disabled for redundant pixel readouts, in accordance with an embodiment.

FIG. 9 is a schematic block diagram of a group control circuit including two group memories for latching two digital pixel values per pixel circuit, in accordance with an embodiment. FIG. 10 is a simplified block diagram of an active pixel circuit and a group signal processing circuit of a solid-state imaging device, in accordance with an embodiment using arithmetic logic units in the group signal processing circuit.

FIG. 11 is a simplified time diagram illustrating input signals, internal signals, and output signals of the group signal processing circuit of FIG. 10 in accordance with an embodiment.

FIG. 12 is a simplified block diagram illustrating a configuration example of a HDR solid-state imaging device that disables and/or switches off portions of a group signal processing circuit for redundant pixel readouts, in accordance with an embodiment having group signal processing circuits without arithmetic logic units.

FIG. 13 is a simplified block diagram of an active pixel circuit and a group signal processing circuit of a solid-state imaging device, in accordance with an embodiment using a digital signal processor for controlling the group signal processing circuit.

FIG. 14 is a simplified time diagram illustrating input signals, internal signals, and output signals of the group signal processing circuit of FIG. 13 in accordance with an embodiment.

FIG. 15 is a block diagram depicting an example of a schematic configuration of a vehicle control system, in accordance with embodiments of the present disclosure

FIG. 16 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section of the vehicle control system of FIG. 15.

DETAILED DESCRIPTION

Embodiments for implementing techniques of the present disclosure will be described below in detail using the drawings. The techniques of the present disclosure are not limited to the described embodiments, and various numerical values and the like in the embodiments are illustrative only. The same elements and elements with the same functions are denoted by the same reference signs. Duplicate descriptions are omitted.

Connected electronic elements may be electrically connected through a direct and permanent low-resistive connection, e.g., through a conductive line. The terms “connected”, “electrically connected” and “signal- connected” may also include a connection through other electronic elements provided and suitable for permanent and/or temporary signal transmission and/or transmission of energy. For example, electronic elements may be electrically connected or signal-connected through resistors, capacitors, and electronic switches such as transistors or transistor circuits, e.g., FETs, transmission gates, complementary switches, an FET, and a dummy switch electrically connected in series, and others. The load path of a transistor is the controlled current path through a transistor. For example, a voltage applied to the gate of a field effect transistor (FET) controls the current flow through the load path (controlled path) between source and drain of the FET by field effect. When it is described that a transistor is connected in series with another element or is connected in parallel with another element, this connection refers to the load path of the transistor.

A digital signal alternates between at least one active level and at least one passive level. A digital signal having an active level is active. A digital signal having an inactive level is inactive. The active level can be a digital high level or a digital low level. The inactive level can be a digital low level or a digital high level.

In FIG. 1, an imaging apparatus 1 includes an optical system 91, a solid-state imaging device 90, a storage unit 92, and a control unit 93. The optical system 91 includes one or more lenses and various mechanisms such as an autofocus mechanism and a diaphragm mechanism, and guides light from an object to a light receiving surface of the solid-state imaging device 90.

The solid-state imaging device 90 includes an image sensor having a plurality of active pixel circuits. Each pixel circuit converts incident radiation into electric signals by photoelectric conversion, and outputs analog pixel signals with a voltage monotonically increasing with increasing intensity of the incident radiation. The solid-state imaging device 90 converts the analog pixel signals into digital pixel values and further includes a signal processing unit that performs predetermined signal processing on the digital pixel values to obtain image data.

The storage unit 92 stores the image data, e.g., frames output from the solid-state imaging device 90 in a storage medium. The storage medium may include a volatile storage medium and/or non-volatile storage medium. The non-volatile storage medium may be or include a flash memory or a hard disk drive. The nonvolatile storage medium may be or include a dynamic random -access memory (DRAM).

The control unit 93 controls the solid-state imaging device 90 such that the solid-state imaging device 90 performs an imaging operation. The imaging operation includes obtaining images from a scene and outputting image data including information about the images.

FIG. 2 illustrates a configuration example of a solid-state imaging device 90 in accordance with embodiments of the present technology. The solid-state imaging device 90 may include a signal processing unit 80 and an image sensor assembly 70. The image sensor assembly 70 may include a pixel array 10, a group signal processing unit 20 that includes a plurality of group signal processing circuits 200, a row decoder/driver 30, a digital readout unit 40, and a sensor controller 50.

The pixel array unit 10 includes a plurality of identical pixel circuits 100. The pixel circuits 100 may be any active pixel sensors (APC) for intensity readout with one or two photoelectric conversion and three, four or more FETs. The pixel circuits 100 convert incident radiation into a pixel internal voltage that is a monotonic function of the intensity of incident radiation detected by the pixel circuit 100 in an exposure period. A pixel circuit 100 outputs an analog pixel signal controlled by the pixel internal voltage to a data signal line 19, when it is selected in a row readout period.

The pixel circuits 100 may be arranged matrix-like in columns and rows. A subset of pixel circuits 100 assigned to the same column form a pixel column. A subset of pixel circuits 100 assigned to the same row form a pixel row.

The row decoder/driver 30 controls the pixel circuits 100 by generating pixel control signals for operating and selecting groups of pixel circuits 100. The pixel control signals control reset states, exposure time, internal temporal storage of the illumination information, and the readout of the pixel circuits 100.

The row decoder/driver 30 controls all pixel circuits 100 of a selected group of pixel circuits 100 synchronously. The selected group of pixel circuits 100 may include some pixel circuits 100 of one pixel row, all pixel circuits 100 of one pixel row, or some or all pixel circuits 100 of more than one pixel row. The following part of the description refers to “pixel rows” as examples for “groups of pixel circuits” for simplicity. The row decoder/driver 30 outputs the control signals for operating the FETs of the pixel circuits 100 on pixel control lines 13 according to driver timing signals supplied from the sensor controller 50.

The pixel circuits 100 of a pixel output group sequentially pass information about the pixel internal voltage that depends on an illumination intensity detected by the pixel circuits 100 in an exposure period to at least one data signal line (vertical signal line) 19. Each pixel output group may include some pixel circuits 100 of one pixel column, all pixel circuits 100 of one pixel column, or some or all pixel circuits 100 of more than one pixel column. The following part of the description refers to “pixel columns” as examples for “pixel output groups” for simplicity.

The pixel circuit 100 includes an amplifier transistor 102 that can be in a source follower configuration with elements of the group signal processing circuit 200. A load path of the amplifier transistor 102 is electrically connected between a pixel supply voltage VDDH and the data signal line 19. Each data signal line 19 sequentially conveys analog pixel signals from the pixel circuits 100 of one of the pixel columns to the group signal processing circuit 200.

The group signal processing circuit 200 includes a current source circuit 210 forming the load of the amplifier transistor 102 of the selected pixel circuit 100, an analog -to-digital converter 240 converting the analog pixel signals into digital pixel values and may include a digital circuit 290 preprocessing the digital pixel values.

The digital circuit 290 may include a digital pixel memory for temporarily storing the digital pixel values for each pixel column and an arithmetic logic unit (ALU) that preprocesses the stored digital pixel values. The ALU may calculate corrected pixel values from a digital pixel value obtained in a reset phase of pixel circuit 100 and a digital pixel value obtained from the same pixel circuit 100 in a data phase, wherein the data phase may follow the reset phase in the same row readout period. The ALU may perform DCDS (digital correlated double sampling) by subtracting the digital pixel value obtained in a reset phase from the digital pixel value obtained from the same pixel circuit 100 in a data phase to obtain the corrected pixel value.

In an active mode, the group signal processing circuit 200 converts an analog pixel signal to a digital pixel value and may obtain the corrected pixel values. The group signal processing circuit 200 outputs the digital pixel values or the corrected pixel values to a digital readout unit 40. The digital readout unit 40 includes a digital pixel memory for temporarily storing the digital pixel values for each pixel column. If the group signal processing circuits 200 do not include ALUs, the digital readout unit 40 may perform DCDS based on the raw digital pixel values for the reset phase and the data phase.

A group control circuit 300 receives the corrected pixel values and/or the raw digital pixel values of a pixel column. The group control circuit 300 may be integrated in the group signal processing circuits 200, e.g., may share resources of the digital circuit 290. Alternatively, the group control circuit 300 may be a function integrated in the digital readout unit 40.

Each group control circuit 300 can judge, based on the corrected pixel values already obtained from the same pixel circuit 100 for an HDR image, whether a further readout of the pixel circuit 100 is redundant with respect to the compilation of the HDR image. If the group control circuit 300 decides that another readout of the pixel circuit 100 is redundant, the group control circuit 300 switches the group signal processing circuit 200 to an idle mode for the next readout of the pixel circuit 100 in question. In the idle mode, the group signal processing circuit 200 consumes less electrical power than in the active mode.

The sensor controller 50 generates the driver timing signal and outputs the driver timing signals to the row decoder/driver 30. The sensor controller 50 generates readout control signals for controlling the group signal processing unit 20 through readout control lines 14. The readout control signals may control the analog -to-digital conversion of the analog pixel signals. The sensor controller 15 may generate a pixel data control signal that controls the readout of corrected pixel values from the digital readout unit 40 to the signal processing unit 80 and/or via a digital interface.

FIG. 3 is a diagram illustrating an example in which the solid-state imaging device 90 of FIG. 2 is formed by a stacked CMOS image sensor (CIS) having a two-layer structure with a radiation receiving chip 910 and a processing chip 920. The radiation receiving chip 910 includes at least the photoelectric conversion elements. For example, the radiation receiving chip 910 may include only the photoelectric conversion elements, or parts of the pixel circuits including the photoelectric conversion element and one or more transistors, or the complete pixel circuits, or the complete pixel circuits and elements of the group signal processing circuits 200. As illustrated on the right-hand side of FIG. 3, the solid-state imaging device 90 is formed as one sensor by bonding the radiation receiving chip 910 and the processing chip 920 while electrically bringing contact pads on the radiation receiving chip 910 in contact with corresponding contact pads on the processing chip 920.

FIG. 4 shows elements of a solid-state imaging device 90 in accordance with the present disclosure. The solid-state imaging device 90 includes a plurality of pixel circuits 100, wherein each pixel circuit 100 is configured to output an analog pixel signal VPX on a data signal line 19. A voltage level of the pixel signal VPX depends on an intensity of incident radiation detected in an exposure period. A group signal processing circuit 200 is switchable between an active mode and an idle mode. In the active mode, the group signal processing circuit 200 converts the pixel signal transmitted through the data signal line 19 into a digital pixel value. In the idle mode, the group signal processing consumes less power than in the active mode. A group control circuit 300 controls the group signal processing circuit 200 to switch to the idle mode when a digital pixel value obtained in the active mode fulfills a predefined condition.

The pixel circuits 100 may be any type of pixel circuit suitable for multi -capture HDR image sensors. In multi -capture HDR image sensors, the pixel circuits 100 are exposed and read out multiple times under different operating conditions so that a high dynamic range can be covered. Each multi-capture exposure includes several exposures using different exposure times, different optical filter configurations in the optical path, and/or different electrical pixel configurations. For each single exposure of a multi -capture exposure, the operating conditions of the pixel circuits are set to cover a partial sensitivity range of the total sensitivity range. The entirety of all partial sensitivity ranges completely covers the total sensitivity range without gaps. At least some of neighboring partial sensitivity ranges can overlap with each other. Others may connect seamlessly. The sequence in which the exposures and/or readouts for the various partial sensitivity ranges are performed is arbitrary.

Based on the results of one or more preceding readouts of a specific pixel circuit 100 in course of the same multi -capture exposure, the group control circuit 300 decides for the specific pixel circuit 100 whether a further readout of the pixel circuit for another partial sensitivity range can provide more information than the readout(s) performed so far. If a further readout for the pixel circuit 100 can add additional information, the group control circuit 300 keeps the group signal processing circuit 200 in the active mode. Otherwise, the group control circuit 300 switches the group signal processing circuit 200 to the idle mode for the specific pixel circuit for the subsequent readouts of the multi -capture exposure. Subsequent selection of the specific pixel circuit for readout does not consume electrical power or less electrical power in the group signal processing circuit 200. Power consumption can be reduced without compromising image quality.

FIG. 5A shows a combined digital output COMBOUT for a pixel circuit as a function of the incident radiation intensity RE The combined digital output COMBOUT represents the digital pixel value of the pixel circuit in the HDR image. The pixel circuit is configured to be operated with three overlapping partial sensitivity ranges SI, S2, S3 for incident light intensity

The partial sensitivity ranges SI, S2, S3 are the same for all pixel circuits 100 of a pixel array. A pixel circuit is operated in a configuration providing the most sensitive partial sensitivity range S 1 for a low-light exposure El. The pixel circuit is operated in a configuration providing the least sensitive partial sensitivity range S3 for a high-light exposure E3. The pixel circuit is operated in a configuration providing a mean sensitive partial sensitivity range S2 for a mid-light exposure E3. The mean sensitive partial sensitivity range S2 overlaps both the most sensitive partial sensitivity range SI and the least sensitive partial sensitivity range S3.

Each partial sensitivity range SI, S2, S3 has an individual subrange and one or two shared subranges. Within the individual subrange, no overlap exists with another partial sensitivity range.

The most sensitive partial sensitivity range SI has an individual subrange from RI=RI0 to RI=RI1 and a shared subrange from RI=RI1 to RI=RI2. The mean sensitive partial sensitivity range S2 has an individual subrange from RI=RI2 to RI=RI3 and shared subranges from RI=RI1 to RI=RI2 and from RI=RI3 to RI=RI4. The most sensitive partial sensitivity range has a shared subrange from RI=RI3 to RI=RI4 and an individual subrange from RI=RI4 to RI=RI5.

For the low-light exposure, the limits RI1, RI2 of the subranges of the most sensitive partial sensitivity range SI correspond to corrected pixel values equal to boundary values Al, A2. For the mid-light exposure, the limits RI1, RI2, RI3, RI4 of the subranges of the mean sensitive partial sensitivity range S2 correspond to corrected pixel values equal to equal to boundary values Bl, B2, B3, B4. For the high-light exposure, the limits RI3, RI4 of the subranges of the least sensitive partial sensitivity range S3 correspond to corrected pixel values equal to boundary values Cl, C2.

For a specific pixel circuit 100, a combined pixel output for an HDR image can be obtained from one single exposure when the detected radiation intensity falls in the individual subrange of a partial sensitivity range SI, S2, S3, or from two exposures when the detected radiation intensity falls in a shared subrange.

When the corrected pixel values of two exposures are combined, the corrected pixel values from the two concerned exposures can be weighted and the weighted corrected pixel values are added up. In the shared subranges, a scale factor for corrected pixel values obtained from an exposure Ek may monotonically decrease, e.g., linearly decrease with decreasing distance to the boundary of the exposure Ek, with k being a natural number greater 1. For example, at C1/B3 the combined corrected pixel value contains 100% of the corrected pixel value from the mid-light exposure E2 and 0% of the corrected pixel value from the highlight exposure E3. The ratio may then be scaled in a linear way to C2/B4 where the combined corrected pixel value contains 0% of the mid-light exposure E2 and 100% of the high-light exposure E3. The same principle can apply for the shared subrange from Bl/Al to B2/A2 and any other intermediate shared subrange in case of more than one mid-light exposure.

FIG. 5B shows how the combined output of a specific pixel circuit for a HDR image is obtained from the corrected pixel values for various exposures.

If, for a low-light exposure El, the corrected pixel value is < Al, the pixel circuit is operated in the individual subrange from RIO to RI1 and the combined pixel value is equal to the corrected digital value obtained from the low-light exposure El. Any further readout of the pixel circuit can be considered redundant. If, for a low-light exposure El, the corrected pixel value is >A1 and < A2, the pixel circuit is operated in the shared subrange from RI1 to RI2 and the combined pixel value can be obtained from the corrected digital values for the low-light exposure El and the mid-light exposure E2. If the mid-light exposure has already been performed, any further readout is redundant. If the mid-light exposure has not yet been performed for the HDR image, a further readout can be done.

If, for a low-light exposure El, the corrected pixel value is > A2, the pixel circuit is operated outside the most sensitive sensitivity range SI. The digital pixel value obtained in the low-light exposure El is not necessarily used for the HDR image. At least one further readout of the pixel circuit is required.

If, for a mid-light exposure E2, the corrected pixel value is >B2 and < B3, the pixel circuit is operated in the individual subrange from RI2 to RI3 and the combined pixel value can be set equal to the corrected digital value multiplied with a sensitivity ratio for the mid-light exposure E2. Any further readout of the pixel circuit can be considered redundant.

If, for a mid-light exposure E2, the corrected pixel value is >B 1 and < B2, the pixel circuit is operated in the shared subrange from RI1 to RI2, and the combined pixel value can be obtained from the corrected digital values for the low-light exposure El and the mid-light exposure E2. If the low-light exposure has already been performed, any further readout can be considered redundant. If the low-light exposure has not yet been performed for the HDR image, a further readout can be done.

If, for a mid-light exposure E2, the corrected pixel value is >B3 and < B4, the pixel circuit is operated in the shared subrange from RI3 to RI4, and the combined pixel value can be obtained from the corrected digital values for the high-light exposure E3 and the mid-light exposure E2. If the high-light exposure has already been performed for the instantaneous HDR image, any further readout for the specific pixel circuit is redundant. If the high-light exposure has not yet been performed for the HDR image, a further readout can be done.

If, for a mid-light exposure E2, the corrected pixel value is < B 1 or > B4, the pixel circuit is operated outside the mean sensitive partial sensitivity range S2. At least one further readout of the pixel circuit is required.

If, for a high-light exposure E3, the corrected pixel value is > C2, the pixel circuit is operated in the individual subrange from RI4 to RI5 and the combined pixel value can be set equal to the corrected digital value multiplied with a sensitivity ratio for the high-light exposure E2. Any further readout of the pixel circuit is redundant.

If, for a high-light exposure E3, the corrected pixel value is >C1 and < C2, the pixel circuit is operated in the shared subrange from RI3 to RI4 and the combined pixel value can be obtained from the corrected digital values for the high-light exposure E3 and the mid-light exposure E2. If the mid-light exposure has already been performed, any further readout is redundant. If the mid-light exposure has not yet been performed for the HDR image, a further readout can be done. If, for a high-light exposure E3, the corrected pixel value is < Cl, the pixel circuit is operated outside the least sensitive sensitivity range S3. At least one further readout of the pixel circuit is required.

Accordingly, the predefined condition for the group control circuit 300 to switch the group signal processing circuit 200 to the idle mode for the readout of a specific pixel circuit includes that a previous readout for the specific pixel circuit was within the limits of an individual subrange or that two previous readouts for the specific pixel circuit were within the limits of the same shared subrange.

FIG. 6 shows a solid-state imaging device 90 with a group signal processing unit 20 that includes a voltage ramp generator 25, a counter circuit 26, and plurality of group signal processing circuits 200.

The pixel circuits 100 output the analog pixel signals for a reset phase (noise signal) and a data phase (data signal) sequentially on the same data signal line 19 or simultaneously on a pair of data signal lines 19.

In the illustrated embodiment, each group signal processing circuit 200 is connected to one data signal line 19 or to one pair of data signal lines 19 and receives the analog pixel signals of the pixel circuits 100 assigned to one pixel column. Alternatively, each group signal processing circuit 200 may be connected to or connectable to more than one data signal line 19 or more than one pair of data signal lines 19 and receive the analog pixel signals of the pixel circuits 100 from more than one pixel column.

Also in the illustrated embodiment, the group signal processing unit 20 includes one voltage ramp generator 25 and one counter circuit 26. Alternatively, the group signal processing unit 20 may include more than one voltage ramp generator 25, each of them connected to one or some of the group signal processing circuits 200, and/or more than one counter circuits 26, each of them connected to one or some of the group signal processing circuits 200.

Each column signal processing circuit 200 includes a current source circuit 210, a comparator circuit 220, and a latch circuit 230, and a digital circuit 290.

The current source circuit 210 is a constant current source and complements the amplifier transistor 102 in the selected pixel circuit 100 to a source follower that outputs the analog pixel signal of a selected pixel circuit 100 to a first input of the comparator circuit 220 in a row readout period. The current source circuit 210 may sink or source a constant current.

The voltage ramp generator 25 outputs a voltage ramp signal VRMP in response to an active ramp power enable signal REN. The voltage ramp signal VRMP may decrease from a high voltage level to a low voltage level continuously or in small steps at a rate significantly lower than leading and trailing edges of a row select signal. Alternatively, the voltage ramp signal VRMP may increase from a low voltage level to a high voltage level continuously or in small steps at a rate significantly lower than leading and trailing edges of a row select signal. The voltage ramp signal VRMP is applied to the second input of the comparator circuit 220 in the row readout periods. The comparator circuit 220 outputs an active comparator output signal CO when the voltage level of a falling voltage ramp signal VRMP falls below the voltage level of the analog pixel signal applied to the first input of the comparator circuit 220, or when the voltage level of a rising voltage ramp signal VRMP exceeds the voltage level of the analog pixel signal applied to the first input of the comparator circuit 220.

The counter circuit 26 outputs a digital count value of a digital counter on a digital bus to data inputs of the latch circuits 230 in response to an active count power enable signal CEN. The active count enable CEN signal and the active ramp power enable signal REN have a predetermined temporal relationship to each other and to the start of the row readout period. The latch circuit 230 latches the instantaneous count value applied to the data inputs with a transition from an inactive comparator output signal to the active comparator output signal CO. The latched count value represents the digital pixel value of the pixel signal obtained from the pixel circuit 100 in the row readout period.

Instead of one counter circuit 26 whose counter values are applied to all latch circuits 230, the column signal processing unit 20 may include one counter circuit 26 for each latch circuit 230 or for each subset of latch circuits 230. Instead of one voltage ramp generator 25 whose voltage ramp signal is applied to all comparator circuits 220, the column signal processing unit 20 may include one voltage ramp generator 25 for each comparator circuit 220 or for each subset of comparator circuits 220.

The digital circuit 290 of a group signal processing circuit 200 receives the digital pixel values from the latch circuit 230. The digital circuit 290 may include at least one memory for a digital pixel value and may include an ALU for determining the corrected pixel values from digital pixel values obtained in the reset and data phases by DCDS.

The group control circuit 300 receives the corrected pixel values for each pixel circuit 100 and assesses whether further readouts of the specific pixel circuit are redundant in view of the compilation of an HDR image. If further readouts of the specific pixel circuit 100 are redundant in view of the currently compiled HDR image, the group control circuit 300 switches parts of the group signal processing circuit 200 to the idle mode. In the idle mode, at least one of the current source circuit 210, comparator circuit 220, and latch circuit 230 is disabled and/or turned off and consumes less electrical power.

The group control circuit 300 may be implemented as part of the digital circuit 290. The group control circuit 300 remains active in the idle mode of the group signal processing circuit 200.

FIG. 6 is related to a solid-state imaging device with a group signal processing circuit 200 that includes a current source circuit 210. The current source circuit 210 supplies a constant current to the data signal line 19 at least in a row readout period in the active mode of the group signal processing circuit 200 and does not supply a constant current in the idle mode of the group signal processing circuit 200.

Each pixel circuit 100 connected to the same data signal line 19 includes the transistor portion of a source follower that outputs the analog pixel signals in the row readout periods. The source followers share one current source circuit 210 as common source follower load in different row readout periods. In a multi-capture process in which an HDR image is obtained from multiple successive exposures, the group control circuit 300 controls the current source circuit 210 so that a constant current is not supplied to the data signal line 19 for a redundant readout of a specific pixel circuit 100, whose combined pixel value can be obtained entirely from previous readouts and/or not from the instantaneous readout. Electrical power for outputting the analog pixel signal on the data signal line 19 can be saved.

FIG. 7 shows a portion of a group signal processing circuit 200 that includes a gate circuit 211 configured to connect the current source circuit 210 with the data signal line 19 when both an output power enable signal EN output by the group control circuit 300 and a conversion power enable signal CE indicating a readout of any of the pixel circuits 100 connected to the data signal line 19 have an active level.

For the following, the output power enable signal EN and the conversion power enable signal CE are digital signals changing between a high level and a low level, and the signals are active when they have the high level. The gate circuit 211 can include an AND-gate 212 and a switch 213. The AND-gate 211 receives the signals CE and EN and outputs an active signal when both signals CE and EN are active. A controlled path of the switch 213 is between the data signal line 19 and a first electrode of the current source circuit 210. The switch 213 may include an FET which may be an nFET, a pFET, or a parallel connection of an nFET and a pFET.

Referring again to FIG. 6, the group signal processing circuit 200 may include a comparator circuit 220 configured to output an active comparator output signal CO when a voltage level of a falling ramp signal VRMP falls below a voltage level of the analog pixel signal VPX or a voltage level of a rising ramp signal exceeds a voltage level of the pixel signal in the active mode of the group signal processing circuit 200. The comparator circuit 220 is disabled in the idle mode of the group signal processing circuit 200.

The comparator circuit 220 forms a portion of an analog-to-digital converter (ADC) converting the analog pixel signals to digital pixel values. When the comparator circuit 220 is disabled, internal switches transistors of the comparator circuit 220 do not change their state and the comparator circuit 220 may output an inactive comparator output signal.

In a multi-capture process in which an HDR image is obtained from multiple successive exposures, the group control circuit 300 controls the comparator circuit 220 so that the comparator circuit 220 consumes less electrical power for a redundant readout of a specific pixel circuit, whose combined pixel value does not include information from the instantaneous readout, e.g., can be obtained entirely from previous readouts.

According to an embodiment, the comparator circuit 220 may include at least one electronic element that is connected to a positive logic supply potential VDDL in the active mode of the group signal processing circuit 200 and separated from the positive logic supply potential VDDL in the idle mode of the group signal processing circuit 200. In particular, the comparator circuit 220 may include more than one electronic element connected to the positive logic supply potential VDDL in the active mode and separated from the positive logic supply potential VDDL in the idle mode of the group signal processing circuit 200. Alternatively or in addition, the comparator circuit 220 may include one or more electronic elements connected to a reference potential VS S in the active mode and separated from the reference potential VSS in the idle mode of the group signal processing circuit 200.

In FIG. 8, the comparator circuit 220 includes a high-gain differential amplifier 225 that is electrically connected between a positive logic supply potential VDDL and a reference potential VSS in the active mode of the group signal processing circuit 200 and separated from at least one of the positive logic supply potential VDDL and the reference potential VSS in the idle mode of the group signal processing circuit 200.

A first capacitor 221 couples the analog pixel signals VPX to a first input of the high-gain differential amplifier 225. A second capacitor 222 couples the voltage ramp signal VRMP output by a digital -to-analog converter (DAC) 255 of voltage ramp generator 25 to a second input of the high-gain differential amplifier 225. A first autozero switch 223 is electrically connected between a first output and the first input of the high-gain differential amplifier 225. A second autozero switch 224 is electrically connected between a second output and the second input of the high-gain differential amplifier 225.

An electric switch 228 is electrically connected between a power supply node of the high-gain differential amplifier 225 and the positive logic supply potential VDDL. An active power enable signal EN turns on the electric switch 228 to electrically connect the high-gain differential amplifier 225 to the positive logic supply potential VDDL for the active mode. An inactive power enable signal EN turns off the electric switch 228 to disconnect the high-gain differential amplifier 225 from the positive logic supply potential VDDL for the idle mode. The electric switch 228 may include an FET which may be an nFET.

According to the illustrated embodiment, the comparator circuit 220 further includes an output gate circuit 229 configured to output an active gated comparator signal GCO when a power enable signal EN output by the group control circuit 300 and the active comparator output signal CO are active.

A global counter circuit may synchronously supply a count value to a plurality of group signal processing circuits 200, with each group signal processing circuit 200 being assigned to another group of pixel circuits, e.g., to another pixel column. The gated comparator signal GCO is used to latch a count value for the respective pixel group (pixel column) in the latch circuit 230. By gating the comparator output signal with the power enable signal EN of the group control circuit 300, the group latch circuit 230 remains inactive and does not consume power for a latch process when the group signal processing circuit 200 is in the idle mode.

FIG. 9 shows a group control circuit 300 including an arithmetic logic unit 310. The arithmetic logic unit 310 can be configured to obtain a corrected digital pixel value by subtracting a digital pixel value obtained from one of the pixel circuits 100 in a reset phase from a digital pixel value obtained from the same pixel circuit 100 in a data phase.

In particular, the arithmetic logic unit 310 may perform a digital correlated data sampling (DCDS): The digital pixel value for the reset phase is obtained from the unexposed pixel circuit (dark pixel) and contains information about the noise generated in the pixel circuit (noise signal). The digital pixel value for the data phase is obtained from one of the readouts of the multi -capture exposure pixel and contains both image data and noise. Subtracting the digital pixel value obtained from the noise signal from the digital pixel value obtained in the data phase can remove a low-frequency portion of the noise from the image data.

By using an arithmetic logic unit 310 provided for DCDS, the group control circuit 300 can be implemented with low additional effort. Alternatively, the group control circuit 300 may include an additional arithmetic logic unit that operates independently from the arithmetic logic unit for DCDS.

The arithmetic logic unit 310 is further configured to compare the corrected digital pixel values obtained in an ongoing readout for a multi-capture exposure with at least one of a set of predefined threshold values defining limits of partial sensitivity ranges and control the power enable signal EN in response to results of the comparisons.

For each pixel circuit 100, a combined pixel output for an HDR image can be obtained from one single exposure when the detected radiation intensity falls in an individual subrange of a partial sensitivity range or from two exposures when the detected radiation intensity falls in a shared subrange. An individual subrange of a partial sensitivity range is covered only by the conditions of one of the exposures. A shared subrange of two a partial sensitivity ranges is covered by the conditions of two of the exposures, irrelevant of the number of mid-light exposures.

The arithmetic logic unit 310 includes a flag unit 311 and controls the flag unit 323 to output an inactive output power enable signal EN when a latest corrected digital pixel value obtained in an ongoing readout for a multi -capture exposure is within an individual subrange of one of the partial sensitivity ranges.

Any further readout from the specific pixel circuit is redundant for the compilation of the HDR image from the ongoing multi-capture readout. For the specific pixel circuit, the combined pixel output for the HDR image is obtained only from the instantaneous corrected pixel value, since the detected radiation intensity falls only in one individual subrange of a partial sensitivity range.

In addition, the arithmetic logic unit 310 may control the flag unit 311 to output an inactive output power enable signal EN when a latest corrected digital pixel value obtained in an ongoing readout for a multicapture exposure is within a predefined shared subrange of two of the partial sensitivity ranges, and wherein a corrected digital pixel value previously obtained in the ongoing readout for a multi -capture exposure was within the same predefined shared subrange. For each pixel circuit 100, a combined pixel output for an HDR image can be obtained from two exposure when the detected radiation intensity falls in a shared subrange of two neighboring partial sensitivity ranges.

The group control circuit 300 may include a first group memory 321 and a second group memory 322. The arithmetic logic unit 310 is configured to store in each of the first and second group memories 321, 322 corrected pixel values used for compiling an HDR image from the multi-capture exposure and tags identifying partial sensitivity ranges of exposures from which the corrected pixel values are obtained.

The two group memories allow a combined readout of both corrected pixel values for the case the pixel value of a HDR pixel is compiled from the corrected pixel values obtained from two exposures.

In the following, a method of operating the group control circuit 300 of FIG. 9 is described with reference to the boundary values Al, A2, Bl, B2, B3, B4, Cl, C2 of FIG. 5B. One row readout period may include the successive readout of two, three or more different analog pixel signals for data phases obtained in a multi-capture exposure and the conversion of one or two of them into digital pixel values and corrected pixel values. The flag unit 311 may be initialized at the beginning of each row readout period. For example, a memory select value stored in the flag unit 311 is set to “1” and the enable signal EN is set active. The tag areas in the first and second group memories 321, 322 may be marked as invalid.

If the ALU 310 receives a corrected pixel value DCDS obtained in a low-light exposure at a first input and a global DCMP bus applies the boundary value A2 to a second input of the ALU 310. The global tag signal TAG applies an identifier for the low-light exposure to inputs of the first and second group memories 321, 322.

The ALU 310 compares the corrected pixel value DCDS with the boundary value A2. If DCDS < A2, the ALU 310 controls the flag unit 311 to output a store tag pulse. The corrected pixel value DCDS and the identifier for the low-light exposure are stored in the first group memory 321, e.g., when the low-light exposure El was the first exposure. The memory identifier msO, msl is set to “2”.

Then the global DCMP bus applies the boundary value Al to the second input of the ALU 310. The ALU 310 compares the corrected pixel value DCDS with the boundary value Al. If DCDS < Al, the ALU 310 controls the flag unit 311 to output an inactive enable signal EN and set the memory identifier msO, msl to “0”. In this case, the corrected pixel value DCDS falls within the individual subrange of the most sensitive partial sensitivity range S 1.

If the ALU 310 receives a corrected pixel value DCDS obtained in a mid-light exposure at the first input, a first local flag IfO and a second local flag Ifl are set equal 0.

The global DCMP bus applies the boundary value B4 to the second input of the ALU 310. The global tag signal TAG applies an identifier for the mid-light exposure to inputs of the first and second group memories 321, 322. The ALU 310 compares the corrected pixel value DCDS with the boundary value B4. If DCDS < B4, the ALU 310 sets the first local flag IfO equal “1”.

The global DCMP bus applies the boundary value B 1 to the second input of the ALU 310. If DCDS > B 1 and the first local flag IfO is equal 1, i.e., Bl < DCDS < B4, the ALU 310 controls the flag unit 311 to output a store tag pulse to store the corrected pixel value DCDS and the identifier for the mid-light exposure in the first group memory 321. The memory identifier msO, msl is set to “2”.

The global DCMP bus applies the boundary value B3 to the second input of the ALU 310. The ALU 310 compares the corrected pixel value DCDS with the boundary value B3. If DCDS < B3, the ALU 310 sets the second local flag Ifl equal “1”.

The global DCMP bus applies the boundary value B2 to the second input of the ALU 310. If DCDS > B2 and the second local flag Ifl is equal 1, i.e., B2 < DCDS < B3, the ALU 310 controls the flag unit 311 to output an inactive enable signal EN and set the memory identifier msO, msl to “0”. In this case, the corrected pixel value DCDS falls within the individual subrange of a mean sensitive partial sensitivity range S2.

If the ALU 310 receives a corrected pixel value DCDS obtained in a high-light exposure at the first input, a global DCMP bus applies the boundary value Cl to the second input of the ALU 310. The global tag signal TAG applies an identifier for the high-light exposure to inputs of the first and second group memories 321, 322.

The ALU 310 compares the corrected pixel value DCDS with the boundary value CL If DCDS > 12, the ALU 310 controls the flag unit 311 to output a store tag pulse to store the corrected pixel value DCDS and the identifier for the high-light exposure in the first group memory 321. The memory identifier msO, msl is set to “2”.

Then the global DCMP bus applies the boundary value C2 to the second input of the ALU 310. The ALU 310 compares the corrected pixel value DCDS with the boundary value C2. If DCDS > C2, the ALU 310 controls the flag unit 311 to output an inactive enable signal EN and set the memory identifier msO, ms 1 to “0”. In this case, the corrected pixel value DCDS falls within the individual subrange of the least sensitive partial sensitivity range S3

The results of the exposures El, E2, E3 can be passed to the ALU 310 in any arbitrary sequence. The first group memory 321 (M0) stores the corrected pixel value of the first exposure whose sensitivity range matches the intensity of the incident radiation. In addition, the first group memory 321 stores a tag identifying the concerned exposure. If the intensity of the incident radiation falls into the individual subrange, the further readout of the concerned pixel circuit can be suspended. Otherwise, the memory pointer is changed to point to the second group memory 322 and the operation proceeds with evaluating the corrected pixel value of the next exposure until the next match. Then the second group memory 322 (Ml) stores the corrected pixel value of the next exposure whose sensitivity range matches the intensity of the incident radiation. In addition, the second group memory 322 stores a tag identifying the next matching exposure. Then the further readout of the concerned pixel circuit can be suspended.

The idea is to go through the exposures El, E2, E3 as the results of the exposures are passed to the ALU 310. When the ALU 310 receives the corrected pixel values in the order El, E2, and E3, the corrected pixel value DCDS for the low-light exposure El and the tag for El are stored in the first group memory 321 (MO) if the sensitivity range for the low-light exposure matches the intensity of the incident radiation. If the corrected pixel value DCDS value is within the range where only the low-light exposure El is needed, readout of the pixel column will stop (MO = (El, El_tag), Ml = (?, invalid tag)). If the corrected pixel value DCDS falls outside the range for the low-light exposure El, the processing continuous with the corrected pixel value DCDS of the next exposure without updating the memory pointer so the next matching exposure will overwrite MO. If the corrected pixel value DCDS falls within the range where the corrected pixel values DCDS for both the low-light exposure El and the mid-light exposure E2 are needed, the memory pointer is set to the second group memory 322 (Ml).

When all corrected pixel values DCDS for the fitting sensitivity range are obtained, the content MO of the first group memory 321 and the content Ml of the second group memory 322 are either (MO = (Ex, Ex_tag), Ml= (Ey, Ey_tag) when the detected radiation intensity falls in a shared subrange or MO = (Ex, Ex_tag), Ml= (?, invalid) when the detected radiation intensity falls in an individual subrange. This holds for any order of the readouts for the exposures El, E2, E3.

When a row readout of the current pixel row has been completed and the corrected pixel values DCDS for the suitable exposure or exposures El, E2, E3 have been stored in the first and second group memories 321, 322, the column memory will be read to the digital core row-by-row for further processing. From the tags in MO and Ml the digital processor gets the information which exposure the corresponding values originate from. This information is used in by the HDR combination algorithm to produce the combined pixel HDR values.]

If the pixel value for the HDR image is obtained from two corrected digital values, both corrected pixel values are available in the first and second group memories 321, 322 together with identifiers for the sensitivity range.

FIG. 10 illustrates a solid-state imaging device 90 combining some of the elements described with reference to FIG. 1 to FIG. 9. For completeness, FIG. 10 also shows an example of a basic design of an active pixel circuit 100.

The illustrated pixel circuit 100 includes a photoelectric conversion element 101 that photoelectrically converts incident electromagnetic radiation into electric charges. The amount of electric charge generated in the photoelectric conversion element 101 corresponds to the intensity of the incident electromagnetic radiation. The photoelectric conversion element 101 may include or consist of a photodiode which converts electromagnetic radiation incident on a detection surface into a detector current by means of the photoelectric effect. The electromagnetic radiation may include visible light, infrared radiation and/or ultraviolet radiation. The amplitude of the detector current corresponds to the intensity of the incident electromagnetic radiation, wherein in the intensity range of interest the detector current increases approximately linearly with increasing intensity of the detected electromagnetic radiation.

A floating diffusion FD stores charge supplied from the photoelectric conversion element 101 in a transfer period. A floating diffusion voltage vfd of the floating diffusion FD depends on the state of the pixel circuit 100: In a reset phase, the floating diffusion voltage vfd is a function of the pixel dark current. In a data phase, the floating diffusion voltage vfd is a function of the brightness (illumination intensity) sampled by the pixel circuit 100.

A load path of a transfer transistor 103 is electrically connected between a cathode of the photoelectric conversion element 101 and the floating diffusion region FD. The transfer transistor 103 serves as transfer element for transferring charge from the photoelectric conversion element 101 to the floating diffusion region FD in a transfer period. The floating diffusion region FD serves as temporary local charge storage. A transfer signal tg is supplied to the gate (transfer gate) of the transfer transistor 103 through a transfer control line. The transfer signal tg changes between an active signal level (“active transfer signal”) and an inactive signal level (“inactive transfer signal”). In response to an active transfer signal tg, the transfer transistor 103 transfers electrons photoelectrically converted by the photoelectric conversion element 101 to the floating diffusion region FD. In the illustrated embodiment, the active signal level is the high level.

A load path of a reset transistor 104 is electrically connected between the positive pixel supply voltage VDDH and the floating diffusion region FD. The reset transistor 104 serves as a reset element that resets the floating diffusion potential vfd of the floating diffusion region FD. A pixel reset signal rst is supplied to the gate of the reset transistor 104 through a reset control line. The pixel reset signal rst changes between an active signal level (“active pixel reset signal”) and an inactive signal level (“inactive pixel reset signal”). In the illustrated embodiment, the active signal level is the high level. An active pixel reset signal rst sets the floating diffusion potential vfd equal to or approximately equal to a pixel reset voltage. The pixel reset voltage may be a fixed voltage, e.g., the positive pixel supply voltage VDDH, or may be adaptive and controlled by a threshold drift compensation circuit.

An amplifier transistor 102 is in a source follower configuration, with the controlled load path electrically connected between the positive pixel supply potential VDDH and the data signal line 19. The floating diffusion region FD is connected to the gate of the amplifier transistor 102. A potential at the gate of the amplifier transistor 102 is equal to the floating diffusion voltage vfd. The floating diffusion region FD functions as the input node of the amplifier transistor 102.

A select transistor 109 controls a sequential readout of all pixel circuits 100 connected to the same data signal line 19. Load paths of the amplifier transistor 102 and the select transistor 109 are electrically connected in series between the positive pixel supply voltage VDDH and the data signal line 19. The select transistor 109 electrically couples the amplifier transistor 102 to the data signal line 19. In particular, the select transistor 109 connects the controlled load path between source and drain of the amplifier transistor 102 to the data signal line 19 when the pixel circuit 100 is selected and disconnects the amplifier transistor

102 from the data signal line 19 when the pixel circuit 100 is not selected.

A row select signal sei for a pixel row is supplied to the gate of the select transistor 109 through a select control line. The row select signal sei changes between an active signal level (“active select signal”) and an inactive signal level (“active select signal”). In the illustrated embodiment, the active signal level is the high level.

An active pixel circuit 100 for HDR may include more than one photoelectric conversion element, more than one transfer gate, and/or additional transistors for controlling the capacitance of the floating diffusion, by way of example.

FIG. 11 shows some of the signals indicated in FIG. 10 for a multi -capture readout based on one single exposure. The reset phase is indicated by the period t2. The data phase is indicated by period t4. A multicapture exposure may include one exposure period in which several voltage signals are generated that are sequentially readout during one consecutive row readout period. The timing is shown for the first exposure, and it will be repeated for the other exposures. Depending on the HDR scheme exposures might come from different rows, so <i> might change.

FIG. 12 is related to an embodiment with a digital signal processor 80 integrating a portion of the functionality of a group control circuit 300 for temporarily switching off portions of the group signal processing circuits 200.

The solid-state imaging device 90 includes a group control circuit 300 that includes a control memory unit 350. The control memory unit 350 receives a control information from a digital signal processor 80 of the solid-state imaging device 90 or via a digital interface of the solid-state imaging device 90 and controls the group signal processing circuit 200 to switch to the idle mode in response to the control information.

For example, the group control circuit 300 can be configured to control a power enable signal EN in response to the control information, wherein the group signal processing circuit 200 is configured to change between the active mode and the idle mode in response to the power enable signal EN.

The digital signal processor 80 is configured to compare the corrected digital pixel values obtained in an ongoing readout for a multi-capture exposure with at least one of a set of predefined threshold values defining limits of partial sensitivity ranges and control the power enable signal EN in response to results of the comparisons. For example, the digital signal processor 80 may apply a method as described with reference to FIG. 5B and FIG. 9

FIG. 13 shows a solid-state imaging device 90 with the functionality of a group control circuit 300 distributed between a digital signal processor 80 and control memory units 350, wherein each control memory unit 350 controls one of the group signal processing circuits 200. The control memory units 350 may be 1 -bit memories for storing 1 bit. A program module or a hardware component, e.g., an ASIC of the digital signal processor controls the control memory units 350 so that only one or two analog-to-digital conversions are carried out per pixel circuit. At least portions of the column signal processing circuit 200 are turned off and/or disabled when sufficient corrected pixel values are read out from the concerned pixel circuit.

The digital signal processor 80 continuously receives the corrected pixel values, checks whether the corrected pixel values are suitable for the capture conditions under which the corrected pixel values are obtained. If no further corrected pixel values are needed to compile a HDR image from the various captures, the digital signal processor 80 sets the control memory unit 350 to output an inactive power enable signal EN switching off at least portions of the group signal processing unit 200. When the readout switches to the next pixel row, the control memory unit 350 is reset to output an active power enable signal EN that turns on the group signal processing unit 200.

FIG. 14 shows some of the signals indicated in FIG. 13 for a multi -capture readout based on one single exposure. The reset phase is indicated by the period t2. The data phase is indicated by period t4.

FIG. 15 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a system to which the technology according to an embodiment of the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in FIG. 15, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound/image output section 12052, and a vehiclemounted network interface 12053 are illustrated as a functional configuration of the integrated control unit 12050.

The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. The outside-vehicle information detecting unit 12030 can be connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 imaging an image of the outside of the vehicle and receives the imaged image. Based on the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section 12031 may be or may include a solid-state imaging device with a group control circuit according to the embodiments of the present disclosure. The light received by the imaging section 12031 may be visible light or may be invisible light such as infrared rays or the like.

The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle and may be or may include a solid-state imaging device with a group control circuit according to the embodiments of the present disclosure. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that includes the solid-stage imaging device and that is focused on the driver. Based on detection information input from the driver state detecting section 12041 , the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver or may determine whether the driver is dozing.

The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in- vehicle information detecting unit 12040 and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

In addition, the microcomputer 12051 can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle which information is obtained by the outsidevehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

The sound/image output section 12052 transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of FIG. 15, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display or a head-up display.

FIG. 16 is a diagram depicting an example of the installation position of the imaging section 12031, wherein the imaging section 12031 may include imaging sections 12101, 12102, 12103, 12104, and 12105.

The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, side-view mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side view mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper, or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally, FIG. 16 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the side view mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, imaging element having pixels for phase difference detection or may include a ToF module including a solid-state imaging device with a group control circuit according to the embodiments of the present disclosure.

For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100 on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km/hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound/image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed to be superimposed on the recognized pedestrian. The sound/image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying a solid-state imaging device with a group control circuit according to the embodiments of the present disclosure, power consumption can be reduced.

Additionally, embodiments of the present technology are not limited to the above-described embodiments, but various changes can be made within the scope of the present technology without departing from the gist of the present technology. The image sensor with pixel circuits according to the present disclosure may be any device used for analyzing and/or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, a solid-state imaging device with a group control circuit according to the embodiments may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like.

Specifically, in the field of image reproduction, the solid-state imaging device with a group control circuit according to the embodiments may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, the solid-state imaging device with a group control circuit according to the embodiments may be integrated in an in-vehicle sensorthat captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like.

In the field of home appliances, the image sensor with pixel circuits according to the embodiments may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly, the image sensor with pixel circuits according to the embodiments may be integrated in home appliances such as TV receivers, refrigerators, and air conditioners and/or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the image sensor with pixel circuits according to the embodiments may be integrated in any type of sensor, e.g., a solid-state image device, provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light.

In the field of security, the image sensor with pixel circuits according to the embodiments can be integrated in a device provided for use in security, such as a monitoring camera for crime prevention or a camera for person authentication use. Furthermore, in the field of beauty, an image sensor with pixel circuits according to the embodiments can be used in a device provided for use in beauty, such as a skin measuring instrument that captures skin or a microscope that captures a probe. In the field of sports, an image sensor with pixel circuits according to the embodiments can be integrated in a device provided for use in sports, such as an action camera or a wearable camera for sport use or the like. Furthermore, in the field of agriculture, the image sensor with pixel circuits can be used in a device provided for use in agriculture, such as a camera for monitoring the condition of fields and crops.

The present technology can also be configured as described below:

[1] A solid-state imaging device (90), including: a plurality of pixel circuits (100), each pixel circuit (100) configured to output an analog pixel signal on a data signal line (19), wherein a voltage level of the pixel signal depends on an intensity of incident radiation detected in an exposure period; a group signal processing circuit (200) switchable between an active mode and an idle mode, wherein the group signal processing circuit (200) is configured to convert the pixel signal transmitted through the data signal line (19) into a digital pixel value in the active mode and to consume less power in the idle mode than in the active mode; and a group control circuit (300) configured to control the group signal processing circuit (200) to switch to the idle mode when a digital pixel value obtained in the active mode fulfills a predefined condition.

[2] The solid-state imaging device (90) according to [1], wherein the group signal processing circuit (200) includes a current source circuit (210) configured to supply a constant current to the data signal line (19) at least in a row readout period in the active mode of the group signal processing circuit (200) and to not supply a constant current in the idle mode of the group signal processing circuit (200).

[3] The solid-state imaging device (90) according to [2], further including: a gate circuit (211) configured to connect the current source circuit (210) with the data signal line (19) when an output power enable signal EN output by the group control circuit (300) and a conversion power enable signal CE indicating a readout of any of the pixel circuits (100) connected to the data signal line (19) have an active level.

[4] The solid-state imaging device (90) according to any of [1] to [3], wherein the group signal processing circuit (200) includes a comparator circuit (220) configured to output an active comparator output signal when a voltage level of a falling ramp signal VRMP falls below a voltage level of the pixel signal VPX or a voltage level of a rising ramp signal exceeds a voltage level of the pixel signal in the active mode of the group signal processing circuit (200), wherein the comparator circuit (220) is disabled in the idle mode of the group signal processing circuit (200).

[5] The solid-state imaging device according to [4], wherein the comparator circuit (220) includes at least one electronic element connected to a positive logic supply potential VDDL in the active mode of the group signal processing circuit (200) and separated from the positive logic supply potential VDDL in the idle mode of the group signal processing circuit (200).

[6] The solid-state imaging device (90) according to any of [4] to [5], wherein the comparator circuit (220) includes a high-gain differential amplifier (225) electrically connected between a positive logic supply potential VDDL and a reference potential VSS in the active mode of the group signal processing circuit (200) and separated from at least one of the positive logic supply potential VDDL and the reference potential VSS in the idle mode of the group signal processing circuit (200).

[7] The solid-state imaging device (90) according to any of [4] to [6], wherein the comparator circuit (220) includes at least one output gate circuit (229) configured to output an active gated comparator signal GCO when a power enable signal EN output by the group control circuit (300) and the active comparator output signal CO are active.

[8] The solid-state imaging device (90) according to any of [1] to [7], wherein the group control circuit (300) includes an arithmetic logic unit (310) configured to obtain a corrected digital pixel value by subtracting a digital pixel value obtained from one of the pixel circuits (100) in a reset phase from a digital pixel value obtained from the same pixel circuit (100) in a data phase.

[9] The solid-state imaging device according to [8], wherein the arithmetic logic unit (310) is configured to compare the corrected digital pixel values obtained in an ongoing readout for a multi -capture exposure with at least one of a set of predefined threshold values defining limits of partial sensitivity ranges and control the power enable signal EN in response to results of the comparisons.

[10] The solid-state imaging device according to [9], wherein the arithmetic logic unit (310) includes a flag unit (311) and is configured to control the flag unit (323) to output an inactive output power enable signal EN when a latest corrected digital pixel value obtained in an ongoing readout for a multi -capture exposure is within an individual subrange of one of the partial sensitivity ranges.

[11] The solid-state imaging device according to [10], wherein the arithmetic logic unit (310) is configured to control the flag unit (311) to output an inactive output power enable signal EN when a latest corrected digital pixel value obtained in an ongoing readout for a multi -capture exposure is within a predefined shared subrange of two of the partial sensitivity ranges, and wherein a corrected digital pixel value previously obtained in the ongoing readout for a multi-capture exposure was within the same predefined shared subrange.

[12] The solid-state imaging device (90) according to any of [9] to [11], wherein the group control circuit (300) includes a first group memory (321) and a second group memory (322), and wherein the arithmetic logic unit (310) is configured to store in each of the first and second group memories (321, 322) corrected pixel values used for compiling an HDR image from the multi -capture exposure and tags identifying partial sensitivity ranges of exposures from which the corrected pixel values are obtained.

[13] The solid-state imaging device (90) according to any of [1] to [12], wherein the group control circuit (300) includes a control memory unit (350) configured to receive a control information from a digital signal processor (80) of the solid-state imaging device (90) or via a digital interface of the solid-state imaging device (90), and to control the group signal processing circuit (200) to switch to the idle mode in response to the control information.

[14] The solid-state imaging device according to [13], wherein the group control circuit (300) is configured to control a power enable signal EN in response to the control information, and wherein the group signal processing circuit (200) is configured to change between the active mode and the idle mode in response to the power enable signal EN.

[15] The solid-state imaging device (90) according to any of [13] to [14], wherein the digital signal processor (80) is configured to compare the corrected digital pixel values obtained in an ongoing readout for a multi-capture exposure with at least one of a set of predefined threshold values defining limits of partial sensitivity ranges and control the power enable signal EN in response to results of the comparisons.

Claims

1. A solid-state imaging device, comprising: a plurality of pixel circuits, each pixel circuit configured to output an analog pixel signal on a data signal line, wherein a voltage level of the pixel signal depends on an intensity of incident radiation detected in an exposure period; a group signal processing circuit switchable between an active mode and an idle mode, wherein the group signal processing circuit is configured to convert the pixel signal transmitted through the data signal line into a digital pixel value in the active mode and to consume less power in the idle mode than in the active mode; and a group control circuit configured to control the group signal processing circuit to switch to the idle mode when a digital pixel value obtained in the active mode fulfills a predefined condition.

2. The solid-state imaging device according to claim 1, wherein the group signal processing circuit comprises a current source circuit configured to supply a constant current to the data signal line at least in a row readout period in the active mode of the group signal processing circuit and to not supply a constant current in the idle mode of the group signal processing circuit.

3. The solid-state imaging device according to claim 2, further comprising: a gate circuit configured to connect the current source circuit with the data signal line when an output power enable signal EN output by the group control circuit and a conversion power enable signal CE indicating a readout of any of the pixel circuits connected to the data signal line have an active level.

4. The solid-state imaging device according to claim 1, wherein the group signal processing circuit comprises a comparator circuit configured to output an active comparator output signal when a voltage level of a falling ramp signal VRMP falls below a voltage level of the pixel signal VPX or a voltage level of a rising ramp signal exceeds a voltage level of the pixel signal in the active mode of the group signal processing circuit, wherein the comparator circuit is disabled in the idle mode of the group signal processing circuit.

5. The solid-state imaging device according to claim 4, wherein the comparator circuit comprises at least one electronic element connected to a positive logic supply potential VDDL in the active mode of the group signal processing circuit and separated from the positive logic supply potential VDDL in the idle mode of the group signal processing circuit.

6. The solid-state imaging device according to claim 4, wherein the comparator circuit comprises a high-gain differential amplifier electrically connected between a positive logic supply potential VDDL and a reference potential VSS in the active mode of the group signal processing circuit and separated from at least one of the positive logic supply potential VDDL and the reference potential VSS in the idle mode of the group signal processing circuit.

7. The solid-state imaging device according to claim 4, wherein the comparator circuit comprises at least one output gate circuit configured to output an active gated comparator signal GCO when a power enable signal EN output by the group control circuit and the active comparator output signal CO are active.

8. The solid-state imaging device according to claim 1, wherein the group control circuit comprises an arithmetic logic unit configured to obtain a corrected digital pixel value by subtracting a digital pixel value obtained from one of the pixel circuits in a reset phase from a digital pixel value obtained from the same pixel circuit in a data phase.

9. The solid-state imaging device according to claim 8, wherein the arithmetic logic unit is configured to compare the corrected digital pixel values obtained in an ongoing readout for a multi-capture exposure with at least one of a set of predefined threshold values defining limits of partial sensitivity ranges and control the power enable signal EN in response to results of the comparisons.

10. The solid-state imaging device according to claim 9, wherein the arithmetic logic unit comprises a flag unit and is configured to control the flag unit to output an inactive output power enable signal EN when a latest corrected digital pixel value obtained in an ongoing readout for a multi -capture exposure is within an individual subrange of one of the partial sensitivity ranges.

11. The solid-state imaging device according to claim 10, wherein the arithmetic logic unit is configured to control the flag unit to output an inactive output power enable signal EN when a latest corrected digital pixel value obtained in an ongoing readout for a multi-capture exposure is within a predefined shared subrange of two of the partial sensitivity ranges, and wherein a corrected digital pixel value previously obtained in the ongoing readout for a multi-capture exposure was within the same predefined shared subrange.

12. The solid-state imaging device according to claim 9, wherein the group control circuit comprises a first group memory and a second group memory, and wherein the arithmetic logic unit is configured to store in each of the first and second group memories corrected pixel values used for compiling an HDR image from the multi-capture exposure and tags identifying partial sensitivity ranges of exposures from which the corrected pixel values are obtained.

13. The solid-state imaging device according to claim 1, wherein the group control circuit comprises a control memory unit configured to receive a control information from a digital signal processor of the solid-state imaging device or via a digital interface of the solid-state imaging device, and to control the group signal processing circuit to switch to the idle mode in response to the control information.

14. The solid-state imaging device according to claim 13, wherein the group control circuit is configured to control a power enable signal EN in response to the control information, and wherein the group signal processing circuit is configured to change between the active mode and the idle mode in response to the power enable signal EN.

15. The solid-state imaging device according to claim 13, wherein the digital signal processor is configured to compare the corrected digital pixel values obtained in an ongoing readout for a multi-capture exposure with at least one of a set of predefined threshold values defining limits of partial sensitivity ranges and control the power enable signal EN in response to results of the comparisons.