EP4690478A1 - Management of non-linearities in a multi-stage adc - Google Patents

Abstract

An analog-to-digital converter (ADC) is disclosed, wherein the ADC is configured to output a digital representation of an ADC input. The ADC comprises a first stage for providing a first digital output based on a first stage input signal and a second stage for providing a second digital output based on a second stage input signal, wherein the first digital output corresponds to a first digital value part for the digital representation and the second digital output corresponds to a second digital value part for the digital representation. The first stage is a successive approximation register (SAR) ADC stage, which comprises a feedback digital-to-analog converter (DAC) configured to provide a feedback analog representation of the first digital output for convergence of the first digital output, and a feedforward DAC configured to provide a feedforward analog representation of the first digital output for generation of the second stage input signal. The first stage further comprises mapping circuitry configured to provide a representation of the first digital output to the feedforward DAC, wherein the mapping circuitry comprises dynamic element matching (DEM) circuitry configured to apply time-varying element permutation. A corresponding time-interleaved (Tl) ADC is also disclosed, as well as an integrated circuit, and an electronic apparatus.

Description

MANAGEMENT OF NON-LINEARITIES IN A MULTI-STAGE ADC

TECHNICAL FIELD

The present disclosure relates generally to the field of analog-to-digital conversion. More particularly, it relates to management of non-linearities a multi-stage analog-to-digital converter (ADC).

BACKGROUND

Multi-stage ADCs are well known and typically demonstrate benefits related to power efficiency and conversion rate.

A general problem with ADCs (also applicable for multi-stage ADCs) is non-linear behavior.

Therefore, there is a need for approaches to handle (e.g., avoid or mitigate) non-linear behavior in a multi-stage ADC.

SUMMARY

It should be emphasized that the term "comprises/comprising" (replaceable by "includes/including") when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Generally, when an arrangement is referred to herein, it is to be understood as a physical product; e.g., an apparatus. The physical product may comprise one or more parts, such as controlling circuitry in the form of one or more controllers, one or more processors, or the like.

It is an object of some embodiments to solve or mitigate, alleviate, or eliminate at least some of the above or other disadvantages.

A first aspect is an analog-to-digital converter (ADC) configured to output a digital representation of an ADC input. The ADC comprises a first stage for providing a first digital output based on a first stage input signal and a second stage for providing a second digital output based on a second stage input signal, wherein the first digital output corresponds to a first digital value part for the digital representation and the second digital output corresponds to a second digital value part for the digital representation. The first stage is a successive approximation register (SAR) ADC stage, which comprises a feedback digital-to-analog converter (DAC) configured to provide a feedback analog representation of the first digital output for convergence of the first digital output, and a feedforward DAC configured to provide a feedforward analog representation of the first digital output for generation of the second stage input signal. The first stage further comprises mapping circuitry configured to provide a representation of the first digital output to the feedforward DAC, wherein the mapping circuitry comprises dynamic element matching (DEM) circuitry configured to apply time-varying element permutation.

In some embodiments, the feedforward DAC is thermometer coded and the mapping circuitry further comprises a thermometer encoder configured to encode at least some elements of the first digital output into a corresponding thermometer codeword.

In some embodiments, the mapping circuitry is configured to provide the thermometer codeword to the DEM circuitry.

In some embodiments, the mapping circuitry is configured to provide remaining, non-encoded, elements of the first digital output directly to the DEM circuitry.

In some embodiments, the time-varying permutation is pseudo-randomly changing over time.

In some embodiments, the DEM circuitry is configured to receive a control signal indicative of an initial element permutation.

In some embodiments, the DEM circuitry comprises one or more shift registers configured to provide the time-varying element permutation.

In some embodiments, the feedback DAC is smaller than the feedforward DAC.

In some embodiments, the first stage further comprises a feedback DAC amplifier that is configured to provide the first stage input signal - correspondingly amplified - to the feedback DAC and/or a feedforward DAC amplifier that is configured to provide the first stage input signal - correspondingly amplified - to the feedforward DAC.

In some embodiments, the feedback DAC amplifier and/or the feedforward DAC amplifier is/are configured to amplify the first stage input signal in correspondence with a difference in range between the feedback DAC and the feedforward DAC.

A second aspect is a time-interleaved (Tl) ADC comprising two or more constituent ADCs, wherein each of the two or more constituent ADCs comprises an ADC according to the first aspect.

In some embodiments, at least two of the two or more constituent ADCs apply different timevarying element permutations.

A third aspect is an integrated circuit comprising the ADC of the first aspect, and/or the Tl ADC of the second aspect.

A fourth aspect is an electronic apparatus comprising the ADC of the first aspect, and/or the Tl ADC of the second aspect, and/or the integrated circuit of the third aspect.

In some embodiments, the electronic apparatus is a signal receiver.

In some embodiments, the electronic apparatus is a communication apparatus.

In some embodiments, the communication apparatus is a wireless communication device for a cellular communications system.

In some embodiments, the communication apparatus is a base station for a cellular communications system.

In some embodiments, any of the above aspects may additionally have features identical with or corresponding to any of the various features as explained above for any of the other aspects.

An advantage of some embodiments is that approaches are provided for handling (e.g., avoiding or mitigating) non-linear behavior in a multi-stage ADC.

An advantage of some embodiments is that approaches are provided for handling (e.g., avoiding or mitigating) impairments due to mismatch between DAC weights in an ADC stage. An advantage of some embodiments is that non-linear behavior is reduced compared to other approaches; or is completely eliminated.

An advantage of some embodiments is that the ADC accuracy is increased compared to other approaches.

An advantage of some embodiments is that management of non-linearities is enabled without adversely affecting each decision cycle of the SAR ADC stage.

An advantage of some embodiments is that management of non-linearities is enabled without negatively affecting the operational (e.g., conversion) speed of the ADC.

An advantage of some embodiments is that management of non-linearities is enabled without negatively affecting the physical area of the ADC.

BRIEF DESCRIPTION OF THE DRAWINGS

Further objects, features and advantages will appear from the following detailed description of embodiments, with reference being made to the accompanying drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the example embodiments.

Figure 1A is schematic drawing illustrating an example multi-stage ADC according to some embodiments;

Figure IB is a schematic drawing illustrating an example SAR ADC stage according to some embodiments;

Figure 2A is a schematic drawing illustrating an example DEM arrangement according to some embodiments;

Figure 2B is a schematic block diagram illustrating an example DEM implementation according to some embodiments;

Figure 3 is a schematic drawing illustrating an example SAR ADC stage according to some embodiments;

Figure 4 is a flowchart illustrating example operation steps of a SAR ADC stage according to some embodiments; Figure 5 is a schematic drawing illustrating an example Tl ADC according to some embodiments; and

Figure 6 is a schematic block diagram illustrating an example apparatus according to some embodiments.

DETAILED DESCRIPTION

As already mentioned above, it should be emphasized that the term "comprises/comprising" (replaceable by "includes/including") when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Embodiments of the present disclosure will be described and exemplified more fully hereinafter with reference to the accompanying drawings. The solutions disclosed herein can, however, be realized in many different forms and should not be construed as being limited to the embodiments set forth herein.

As already mentioned, multi-stage ADCs are well known and typically demonstrate benefits related to power efficiency and conversion rate. For example, a two-stage ADC architecture is described in Tripathi and Murmann, "A 160 MS/s, 11.1 mW, Single-Channel Pipelined SAR ADC with 68.3 dB SNDR," Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014, pp. 1-4.

The first stage of that two-stage ADC architecture employs a fast asynchronous SAR loop around a first digital-to-analog converter (DAC1). The first stage also employs a second digital-to-analog converter (DAC2), the low-noise residue of which is passed to the second stage via a residue amplifier. Thereby, the noise-limited path of the two-stage ADC is separated from the highspeed path.

In the following, approaches will be described and exemplified for a multi-stage ADC (a.k.a. a pipeline ADC) with path separation in at least one of the ADC stages. The multi-stage ADC approaches are for handling non-linear behavior. According to some embodiments, non-linear behavior may be mitigated, or completely avoided. Using path separation in at least one of the ADC stages enables application of dynamic element matching (DEM) for management of non-linearities (e.g., mitigating non-linear behavior of the ADC stage with path separation). Use of DEM to manage non-linearities is typically not suitable for a conventional SAR ADC (i.e., a SAR ADC without path separation), since doing so would have a large impact on speed and area of critical parts of the SAR ADC.

The non-linear behavior may have any origin. For example, a portion of the non-linear behavior may be due to mismatch between DAC weights in an ADC stage that applies path separation.

Figure 1A schematically illustrates an example multi-stage ADC 100 according to some embodiments. The ADC 100 comprises a plurality of (two or more) ADC stages, each of which is illustrated as a successive approximation register (SAR) ADC; SARI 110, SAR2 120, SAR3 130.

The ADC 100 is configured to output a digital representation u_0Ut 199 of an ADC input 101. The first stage 110 provides a first digital output d_± 118 based on a first stage input signal v_inl 101, the second stage 120 provides a second digital output d₂ 128 based on a second stage input signal v_in2 102, and so on. The first digital output d_± 118 corresponds to a first digital value part 171 for the digital representation 199, the second digital output d₂ 128 corresponds to a second digital value part 172 for the digital representation 199, and so on. The digital representation 199 is provided by combining the digital value parts as illustrated by 190 (e.g., adding the digital value parts, as properly scaled).

As illustrated by 111, the first stage 110 determines a difference 117 between the first stage input signal v_inl 101 and a digital-to-analog converter (DAC) result v_dl 119. A comparator (CMP) 112 is used to sequentially make decisions based on the difference 117. The decisions are represented in a register (REG) 113, which is configured to provide the first digital output d_r 118. The output 118 of the register 113 is also used as DAC input, and the DAC result 119 is provided by application of DAC weights to the output 118 of the register 113, as illustrated by the weighting (Wl) 114.

Generally, it should be understood that using the output 118 of the register 113 as DAC input may involve some further processing (not shown); e.g., depending on the DAC implementation and/or the nature (e.g., alphabet size and/or meaning of different element values) of the elements of the digital output 118. For example, to control various switches in the DAC, the elements (e.g., bits) of the digital output 118 may need to be translated to corresponding switch control signals (compare with 718', 728' of Figure 3). For example, an element of the digital output 118 may be translated to switch control signals c, d, d_n.

The first digital value part u_± 171 for the digital representation 199 is provided by application of digital weights w_± to the first digital output d_± 118, as illustrated by the weighting (EW1) 115. The digital weights are ideally representing the DAC weights exactly (possibly with a scaling factor; More generally, the digital weights may be seen as estimates of the DAC weights w_t. In practice typically differs (at least slightly) from a₁w₁; e.g., due to mismatches introduced in manufacturing.

The difference 117 is denoted as the residue v_rl of the first stage 110, and is provided as the second stage input signal v_ln2 102 after amplification by A in a residue amplifier 116. Generally, the terms residue and residual signal will be used interchangeably herein.

As illustrated by 121, the second stage 120 determines a difference 127 between the second stage input signal v_ln2 102 and a digital-to-analog converter (DAC) result v_d2 129. A comparator (CMP) 122 is used to sequentially make decisions based on the difference 127. The decisions are represented in a register (REG) 123, which is configured to provide the second digital output d₂ 128. The output 128 of the register 123 is also used as DAC input, and the DAC result 129 is provided by application of DAC weights w₂ to the output 128 of the register 123, as illustrated by the weighting (W2) 124.

The second digital value part it₂ 172 for the digital representation 199 is provided by application of digital weights w₂ to the second digital output d₂ 128, as illustrated by the weighting (EW2) 125. Thereafter, the second digital value part u₂ 172 is scaled by an amplification inverse 1/^4 before combining to provide the digital representation 199, as illustrated by the scaling (SC) 125'. The digital weights w₂ are ideally representing the DAC weights w₂ exactly (possibly with a scaling factor; i.e., w₂ = cr₂w₂. More generally, the digital weights w₂ may be seen as estimates of the DAC weights w₂. The amplification inverse 1/^4 is ideally represents an inverse of the amplification A exactly. More generally, the amplification inverse 1/^4 may be seen as the inverse of an estimate of the amplification A. The difference 127 is denoted as the residue v_r2 of the second stage 120, and may be provided as a third stage input signal after amplification in a residue amplifier 126. The amplification in residue amplifier 126 may be equal to the amplification by A in the residue amplifier 116, or may differ therefrom.

To exemplify further, for an input sample v_inl 101 the first stage (SARI) 110 sequentially takes decisions using the comparator 112, and each decision is added to the register 113, which already comprises the result of previous decisions for the input sample. The output 118 of the register 113 d_± = [d_1/0, d_1#1, ... drives a DAC that generates a signal 119 that converges towards the input voltage of the sample (within a certain level of accuracy defined by the number N_bl of decision cycles and the DAC weights 114 = [w_{1 0}, w_{1 1(} ... w_{1 Wfei i}]). The difference 117 between the input signal 101 and the DAC signal 119 is referred to as the residue v_rl and is fed to the comparator 112 for the subsequent decision.

The first stage 110 outputs a decision vector d₁, wherein each element d_{l k} may be represented in any suitable way; depending on the function of the comparator 112. For example, a binary comparator 112 may detect the sign of the residue 117 and each decision element may be ternary {1,0, —1], where the values may represent positive sign, default value when no decision has been made, and negative sign, respectively. The first digital value part u_± may be formed as

When the N_bl cycles have been completed, the residue v_rl is amplified in the residue amplifier 116 with gain A. The amplified residue 102 serves as input sample v_ln2 to the subsequent stage (SAR2) 120, which continues the conversion by performing N_b2 further decision cycles on the input sample v_ln2 using DAC weights 124 w₂ = [w_{2 0}, w_{2 1}, ... w₂ jv_b ], and may provide the second digital value part u₂. To account forthe residue amplification, u₂ is scaled by 1//1 before being combined with u_lt to yield the ADC output u_0Ut = u_± + u jA.

Even though each stage of the multi-stage ADC 100 is a SAR ADC, it should be noted that the approaches described herein are not limited to such multi-stage ADCs. Rather, the approaches described herein are applicable for any multi-stage ADC (which has at least two ADC stages) wherein at least one ADC stage (the "first stage") with one or more subsequent ADC stage(s) is a SAR ADC. The "second stage" may, or may not, be a SAR ADC. For simplicity, the description herein focuses on the example where the ADC stage that occurs first in the signal flow of the multi-stage ADC (e.g., the stage 110) is a SAR ADC with path separation (i.e., the example when the "first stage" is the ADC stage that occurs first in the signal flow of the multi-stage ADC). However, it should be noted that the "first stage" may be any ADC stage of a multi-stage ADC (e.g., the stage 120), except the ADC stage that occurs last in the signal flow of the multi-stage ADC. Typically, the "second stage" is the ADC stage of the multistage ADC that is directly subsequent to the "first stage".

Figure IB schematically illustrates an example successive approximation register (SAR) ADC stage according to some embodiments. The illustration refers to the first stage (SARI) 110 of Figure 1A, but is should be understood that the principles illustrated by Figure IB may be applied for any be any suitable ADC stage of a multi-stage ADC.

Similarly to what has been described in connection with Figure 1A, it is illustrated by 111 that the ADC stage 110 determines a difference 117 between the stage input signal v_ln 101 and a digital-to-analog converter (DAC) result v_Sdl 119. A comparator (CMP) 112 is used to sequentially make decisions based on the difference 117. The decisions are represented in a register (REG) 113, which is configured to provide a digital output d_± 118. The output 118 of the register 113 is also used as DAC input, and the DAC result 119 is provided by application of DAC weights w_si to the output 118 of the register 113, as illustrated by the weighting (Wls) 114.

The application of digital weights to the digital output d_± 118 is also illustrated by the weighting (EW1) 115'.

The DAC 141 comprising the weighting (Wls) 114 may be denoted as a feedback digital-to- analog converter configured to provide a feedback analog representation (the DAC result 119) of the digital output d_r 118 for convergence (during SAR execution) of the digital output d_r 118.

The difference 117 that is provided to the comparator 112 may be denoted as a feedback DAC residue v_Srl. In contrast to the illustration of Figure 1A, the feedback DAC residue v_Srl 117 is not provided as input signal for the subsequent stage. Instead, another DAC 142 is used for this purpose. As illustrated by 148, the DAC 142 determines a difference 147 between the stage input signal v_ln 101 and a DAC result v_Ldl 149. The DAC result v_Ldl 149 is provided by application of DAC weights w_L1 to the DAC input, as illustrated by the weighting (W1L) 144. The DAC input 160 is a representation of the output 118 of the register 113; after processing by mapping circuitry (MAP) 143.

The mapping circuitry 143 comprises dynamic element matching (DEM) circuitry 150, wherein the DEM circuitry 150 is configured to apply time-varying element permutation on elements of the first digital output 118, or on elements of a digital representation derived from the first digital output 118 (e.g., thermometer codewords). The mapping circuitry 143 is configured to provide the output of the DEM circuitry 150 as the DAC input 160, either directly, or after further processing by the mapping circuitry 143.

Thus, the first stage 110 comprises mapping circuitry 143 configured to provide a representation 160 of the first digital output 118 to the feedforward DAC 142, wherein the mapping circuitry comprises DEM circuitry 150 configured to apply time-varying element permutation.

The digital weights w_± used in EW1 115' typically represent the weights w_L1 of the LDAC 142. For example, the digital weights used in EW1 115' may be the ideal - or expected - values of the weights used in WIL 144. The term "ideal values" may refer to the perspective of the elements in the digital output 118. Using ideal weights in 115' is preferable since the DEM circuitry 150 provides averaging of the weights in 144 (from the perspective of the elements in the digital output 118). Put differently, application of the DEM circuitry 150 entails that the effective weights per element in 118 will have ideal relations.

The DAC 142 comprising the weighting (WIL) 144 may be denoted as a feedforward digita l-to- analog converter configured to provide a feedforward analog representation (the DAC result v_Ldl 149) of the digital output d_± 118 for generation of the input signal for a subsequent stage. To this end, the difference 147 may be denoted as a feedforward residue v_Lrl, and may be provided as input signal for a subsequent stage after amplification in a residue amplifier 116.

The use of two different DACs 141, 142 enables path separation, in that the determination of residue v_Lrl 147 for propagation between stages (which is typically noise sensitive) is separated from the determination of residue v_Srl 117 for convergence of the digital output d₁ 118 (which is typically time critical).

It is typically beneficial to let the feedback DAC 141 be a relatively small DAC (SDAC; e.g., to enable high-speed operation) and to let the feedforward DAC 142 be a relatively large DAC (LDAC; e.g., to enable high accuracy). For example, the feedback DAC 141 may be smaller than the feedforward DAC 142.

The terms "small DAC" and "large DAC" may refer to the physical sizes of the DACs and/or to the capacitance values of the DACs. For example, if the DACs are capacitive DACs, the large DAC would typically have larger capacitors than the small DAC; which typically leads to that large DAC has a larger physical size than the small DAC.

The SDAC-LDAC technique has several potential benefits. For example, a fast, less accurate, lower power DAC (the SDAC) can be used for output decisions without adversely affecting linearity and noise of subsequent ADC stage(s). Alternatively or additionally, any errors introduced by the SDAC leads only to an increase in the residues. Yet alternatively or additionally, since there is no comparator loading the LDAC path, there is no comparator kick- back affecting the integrity of the feedforward residue. Yet alternatively or additionally, the signal levels in SDAC and the LDAC can be decoupled such that, for example, the SDAC can operate with higher signal levels than the LDAC to lower the impact from comparator offset, kickback, and noise while introducing moderate errors due to non-linear distortion (e.g., in 145).

Furthermore, using the SDAC-LDAC technique allows for introduction of a logic layer (compare with 143 of Figure IB) when propagating d_± from the SDAC to the LDAC. Using dynamic element matching (DEM) approaches in relation to this logic layer enables handling (e.g., reduction and/or mitigation) of non-linear behavior of the ADC. Generally, the DEM circuitry may be seen as translating the non-linear behavior to noise by randomization.

For example, the DEM circuitry 150 may address non-linear behavior due to mismatch between weights in the LDAC 144.

Since the DEM is not applied within the feedback DAC loop, the conversion speed of the ADC is not negatively affected. Furthermore, the circuit layout design is more flexible than if the DEM was applied within the feedback DAC loop, e.g., enabling avoidance of parasitic load (and, hence, increased delay) in the decision loop.

The LDAC and/or the SDAC may be implemented as a C-DAC that allows it to double as a sample and hold capacitance as well as a DAC with an output being a superposition of the input sample and the DAC output effectively leading to a subtraction. The illustration of Figure IB can be seen as a functional representation, which is not necessarily an accurate circuit representation. Furthermore, it should be recognized that while the DACs operate based on the decisions by SAR, the inner workings of the DACs may involve other control signals (e.g., switch control signals as mentioned above) and/or clock signals; depending on the actual implementation of the DAC.

Also illustrated in Figure IB are optional amplifiers 145, 146. None, either, or both, of the optional amplifiers 145, 146 may be present according to various embodiments. The amplifiers 145, 146 may be seen as representing/modelling gain differences in the respective SDAC and LDAC paths. Alternatively or additionally, at least one of the amplifiers 145, 146 may represent an actual amplifier or buffer (e.g., differentiating signal levels between the SDAC and LDAC signal paths). Yet alternatively or additionally, at least one of the amplifiers 145, 146 may represent an effective gain when a signal is sampled onto the respective DAC.

The amplifier 145 is configured to provide the stage input signal 101 - correspondingly amplified by g_s - to the feedback DAC 141 (e.g., to improve the signal-to-noise ratio for the feedback DAC 141), and may be denoted as a feedback DAC amplifier. The amplifier 146 is configured to provide the stage input signal 101 - correspondingly amplified by g_L - to the feedforward DAC 142, and may be denoted as a feedforward DAC amplifier.

Typically, linearity requirements may be less strict for the feedback DAC amplifier 145 than for the feedforward DAC amplifier 146.

Generally, the amplification g_s, g_L of the optional amplifiers 145, 146 may be any suitable amplification.

For example, the feedback DAC amplifier 145 and/or the feedforward DAC amplifier 146 may be configured to amplify the stage input signal 101 in correspondence with a difference in range between the feedback DAC 141 and the feedforward DAC 142. If the full-scale ranges of the SDAC and the LDAC are R_{FS S} and R_FS,_L (respectively), the amplifications may, for example, be related as g_L/g_s = R_FS,_L/R_FS,s-

Alternatively or additionally, the feedback DAC amplifier 145 (regardless of whether or not a feedforward DAC amplifier 146 is applied) may be configured to enable the feedback DAC 141 to operate with a full-scale range which is larger than (e.g., 1.5 times) that of the feedforward DAC 142; i.e., g_s > g_L.

It should be noted that the number of weights in the SDAC 141 and the LDAC 142 (i.e., the number of elements in w_si and w_L1) may be the same, or may be different. For example, the weight for the least significant bit, LSB, may be omitted in the SDAC 141 (since a LSB switch is typically not needed in the SDAC 141 when the residue 117 is not used for a subsequent ADC stage).

Figure 2A schematically illustrates an example DEM arrangement 200 according to some embodiments. The DEM arrangement 200 is configured to receive a digital input 218 (compare with 118 of Figure IB) and provide an analog output 249 (compare with 149 of Figure IB). The digital input 218 may have any suitable format (e.g., with elements comprising binary, or ternary, symbol values). For simplicity, binary symbol values (i.e., bits) will be assumed in the following.

The digital input 218 is provided to a thermometer encoder (TH ENC) 242 for conversion to an encoded representation 219 of the digital input 218. A thermometer code is characterized in that all symbol positions are associated with the same symbol weight. Thereby, the value of a binary thermometer codeword corresponds to the number of "1" in the codeword. According to a typical example, the binary thermometer codeword that corresponds to the value x comprises "1" for the x least significant bits and "0" for the remaining L — x most significant bits, where L is the codeword length.

As illustrated by 243, the encoded representation 219 undergoes dynamic element matching (DEM) to provide a representation 260 (compare with 160 of Figure IB) of the first digital output 118 based on the encoded representation 219. The dynamic element matching (DEM) implements a time-varying element permutation. Thus, the representation 260 is an element- permuted version of the encoded representation 219. The time-variation may be implemented in any suitable way. For example, the permutation may be based on a control signal 201, which causes the time-variation.

The elements of the representation 260 undergo respective weighting, as represented by weighting blocks 244-1, 244-2, 244-3, ..., 244-M, before being combined (e.g., added) to provide the analog output 249, as illustrated by 245. For example, the weighting blocks 244-1, 244-2, 244-3, ..., 244-M may implement the same weight (e.g., a unit weight).

The weighting blocks 244-1, 244-2, 244-3, ..., 244-M and the combiner 245 may be comprised in a DAC; e.g., the LDAC 142 of Figure IB (wherein the weighting blocks 244-1, 244-2, 244-3, ..., 244-M and the combiner 245 would implement the weighting (W1L) 144). Thus, the feedforward DAC 142 may be thermometer coded.

It should be noted that the encoder 242 may be generalized to implement any suitable encoding. Typically, all permutations generated by the DEM 243 for a given input 218 should be equally valid representations of the input 218, and the nominal weights in the weighting blocks 244-i should be the same, which suggests that a thermometer code is used. However, using a different set of weights in the weighting blocks 244-i, wherein the weights are nominally not equal (but nominally known), a mapping function with the input 218 (compare with the encoder 242 combined with the DEM 243) may be configured to generate permutations that are equally - or close to equally - valid representations of the input 218.

For example, if a DAC has binary weights [8 4 2 1], those weights may be split in half (decomposition) to get twice the number of weights using the same total "size" as for a thermometer code (i.e., the "size" 8+4+2+1=15). Thus, the weights would become [44 2 2 1 1 0.5 0.5], To generate the value "4", there are multiple permutations available (e.g. 4, 2+2, 2+1+1, 2+1+0.5+0.5) and randomization between available permutations may be applied. This would yield DEM-like benefits, but since the number of available permutations are more restricted, the decorrelation properties will typically not be as good as the approach based on DEM and thermometer encoding.

Thus, a suitable encoding typically implements redundancy in that there are multiple representations for at least some values of the input 218, wherein the set of multiple representations for a value of the input 218 leads to a DAC output that - on average - is closer, or equal, to the desired (nominal) DAC output. Using a thermometer code together with DEM results in convergence to the desired (nominal) DAC output. Other coding schemes that are usable together with DEM may, or may not, have this property. For example, with the weight decomposition approach exemplified above, the desired (nominal) DAC output might not be reached.

The thermometer encoder 242 and the DEM 243 may, for example, be comprised in the mapping circuitry 143 of Figure IB (wherein the DEM 243 would be implemented by the DEM circuitry 150).

In some embodiments, the digital input 218 is equal to the first digital output 118 of Figure IB. In other embodiments, the digital input 218 comprises a subset of the elements of the first digital output 118 of Figure IB (e.g., to avoid extensively long thermometer codewords 219). The subset may be any suitable subset. For example, the subset may correspond to the most significant bits, or the most significant bit together with a suitable selection of other bits of the first digital output 118. Put differently, the DEM is not applied to the entirety of the DAC in some embodiments, but rather to a subset of the weights (e.g., those representing the more significant bits). The weights representing the more significant bits typically exhibit larger absolute errors compared to the weights representing the lesser significant bits.

Thus, the thermometer encoder 242 may be configured to encode at least some elements of the first digital output 118 into a corresponding thermometer codeword 219, and the mapping circuitry 143 may be configured to provide the thermometer codeword 219 to the DEM circuitry 150, 243. The mapping circuitry 143 may also be configured to provide any remaining, nonencoded, elements of the first digital output 118 directly to the respective DAC weights.

Figure 2A may be seen as exemplifying an approach where the LDAC, comprising a set of unit cells 244-1, 244-2, 244-3, ..., 244-M having the same nominal weight, receives a thermometer codeword c_th 219, where each bit in c_th is mapped to a respective DAC unit cell by the DEM 243. The unit cell outputs are combined to form the composite DAC signal 249.

An input signal b 218 (which may be a signal with binary elements) is encoded using the thermometer code to provide the thermometer codeword c_th 219. The encoding is typically static, such that a specific value of the input b is always mapped to a same specific thermometer codeword c_th.

The DEM 243 randomly maps the elements (e.g., bits, or other symbol values) in c_th to the elements (e.g., bits, or other symbol values) in c_dem . The mapping can be memoryless in the sense that it does not depend on previous inputs to the DEM, nor on previous outputs from the DEM. For example, the DEM 243 may be driven by a (pseudo-)random number generator to generate a new mapping for every sample.

Dynamic element matching (DEM) is a technique for de-correlation of the DAC input signal from distortion caused by DAC cell mismatch so as to avoid harmonic distortion; typically at the expense of increased noise level.

The net result of applying DEM as illustrated in Figure 2A is typically an error spectrum that is substantially flat. Some schemes yield a spectrally shaped error spectrum (e.g., with higher levels of noise in frequency regions that are more easily filtered out). DEM approaches (e.g., data-weighted averaging, DWA) are primarily applied in conjunction with use of oversampling (delta-sigma) converters, where the spectral shaping can be favorably exploited as it pushes the errors up in spectrum similar to the noise shaping of delta-sigma converters.

Generally, the dynamic element matching (DEM) 150, 243 may be implemented in any suitable way to achieve a time-varying element permutation.

In some embodiments, the time-varying permutation may be pseudo-randomly changing over time. Alternatively or additionally, an initial element permutation (e.g., based on a seed value or similar) may be used as a starting point for the time-varying permutation.

A control signal (compare with 201 of Figure 2A) may be used to provide parameter(s) controlling the time-varying element permutation. For example, the control signal may provide the seed value, or another indication of the initial element permutation. Alternatively or additionally, the control signal may provide a time-varying parameter indicating the element permutation to be applied.

For example, DEM may be implemented using one or more shift registers configured to provide the time-varying element permutation. A possible DEM implementation approach is outlined in Figure 2B, which illustrates a portion of a switched-element DAC (e.g., compare with 142 of Figure IB). The switched-element DAC comprises a set of M unit cells uc_m, each comprising a unary circuit element (such as a unit capacitor) and a switching arrangement coupled to the unary circuit element. In Figure 2B, these are combined in the blocks labeled "uw," for unit weight (compare with 244-m of Figure 2A). For example, the unit weight ("uw") in Figure 2B may comprise a unit weight cell and a switching arrangement configured to selectively connect the unit capacitor to one of a plurality (e.g., four) of circuit nodes.

In the example of Figure 2B there are two control inputs for each unit cell, labeled c_uc and d_uc. These two control inputs might control the switching arrangement to selectively connect one end of the unit capacitor to one of a positive reference voltage, a negative reference voltage, or a neutral reference voltage, for example. More generally, there can be more or fewer control lines, and these control lines can be configured to switch a unary circuit element into one of multiple states.

The control inputs c_uc and d_uc for each unit cell are independent of the control inputs for the other unit cells. The control inputs for each unit cell can be configured to be connected to switch control signals associated with any one of the decision bits from the SAR register (compare with 118 of Figure IB). In this example, there are two switch control signals for each of N decision bits. These switch control bits are shown in Figure 2B as c[0:Nb-l] and d[0:Nb-l],

Each unit cell u_Cm shown in Figure 2B may contain the unit weight uw, a multiplexer (mux) for switch control signal selection, and a unit cell register (reg) holding a setting (sei [ .] ) for the mux. The select lines (sei) for each mux select a pair of switch control signals from among the pairs of switch control signals c[0:Nb-l] and d[0:Nb-l], Thus, the switch control signals, (c[0:Nb-l] and d[0:Nb-l] in this example), are connected to all unit cells, to allow any given set of unit cells to "subscribe" to the pair of switch control signals for any given one of the N decision bits.

Each of the cell registers (reg) may contain the element of 118 that the cell belongs to. Hence, at some point in time, ucl may have its register set to belong to a specific element of 118, and when the circular shift register is shifted one step, ucO will have its register set to belong to that specific element of 118, and so on. In some embodiments, the cell registers may be initialized such that the number of unit cells that belong to each respective element of 118 corresponds to thermometer encoding. For example, if the elements of 118 are denoted [bO bl b2 ...], the following trivial mapping pattern may be used for initializing the registers: [bO bl bl b2 b2 b2 b2 ...], and that pattern may be rotated/shifted based on r_clk.

It will be appreciated that the combination of multiplexers and unit weights shown in Figure 2B would, given complete independence between the "sei" lines controlling the multiplexers, provide complete flexibility in mapping the switch control signal pairs to individual unit weights. Thus, this arrangement would allow any arbitrary mapping, at any time. Typically, this would require that every signal select line is separately routed to a control point (e.g., a microprocessor and/or digital logic controlling the circuit operation). This complicated routing may be simplified by arranging the unit cell registers so that they form a circular shift register that preferably aligns with the physical circuit layout such that adjacent unit cells in Figure 2B are also adjacent in the circuit layout. This is illustrated in Figure 2B, which shows that the select lines output from each register are connected not only to the respective mux, but also to the input of the immediately adjacent register.

So, upon being clocked by the common clock signal r_clk, the select line data stored in each unit cell register is shifted to the next unit cell register. This forms a compact DEM solution that makes it possible to integrate the DEM functionality tightly as part of the LDAC, thereby avoiding a huge number of control signals that would otherwise have to be routed from a control point outside of the SAR ADC.

At an initialization stage, the unit cell registers may each be individually initialized with bit association values, i.e., pre-loaded with output values for the "sei" lines (an initial element permutation). Alternatively, unit cell register data may be pre-loaded into the registers in serial fashion, by opening up the circular shift register and shifting in settings from the outside, at a single entry point to the circular shift register.

Thus, the DEM technique exemplified in Figure 2B is based on that a bit weight to unit cell association pattern is preloaded before starting the ADC. Each unit cell has its own register storing what bit weight said unit cell belongs to. The registers of the unit cells form a shift register that is randomly shifted such that each unit cell over time will be associated with different bit weights. There may be a randomization block (which may be preloaded with an initial seed before starting the ADC) determining when to shift and when to not shift for each of the samples to be converted.

While DEM is located outside the decision loop according to the approaches exemplified herein, and therefore will not delay every decision cycle, processing delay in the DEM will typically delay settling of the LDAC residue and thereby the point in time when the subsequent stage may commence conversion. To that end, the DEM approach may increase the overall conversion time of the multi-stage ADC somewhat, i.e., the time before a new input sample can be processed. Therefore, the DEM technique exemplified in Figure 2B is particularly suitable, since its operation is comparatively fast and may be implemented with a comparatively small area.

It should be noted that the DEM implementation approach of Figure 2B does not take the thermometer codeword (compare with 219 of Figure 2A) as input. Instead, the encoding may be seen as integrated in the DEM of Figure 2B.

Figure 3 schematically illustrates an example SAR ADC stage 730 according to some embodiments. For example, the SAR ADC stage 730 may correspond to the SAR stage 110 of Figure IB.

The example SAR ADC stage 730 uses single-ended signal representation, while other implementations may apply differential signal representation.

The SAR ADC stage 730 is configured to receive a first stage input signal 701 (compare with 101 of Figure IB) and to provide a residual signal 727 (compare with 147 of Figure IB) to a residue amplifier 716 (compare with 116 of Figure IB).

To this end, the SAR ADC stage 730 comprises a feedback DAC in the form of an SDAC 711 (compare with 141 of Figure IB), a feedforward DAC in the form of an LDAC 712 (compare with 142 of Figure IB), and a processing block (C/R/L) 713.

The SDAC 711 is configured to determine a feedback residual signal 717 (compare with 117 of Figure IB) based on the first stage input signal 701 and an input 718' derived from a first digital output 718 (compare with 118 of Figure IB) of the processing block 713. The LDAC 712 is configured to determine the feedforward residual signal 727 (compare with 147 of Figure IB) based on the first stage input signal 701 and an input 728' derived from a representation 728 (compare with 160 of Figure IB) of the first digital output 718 of the processing block 713.

The SDAC 711 is controllable via reference signal inputs vrefS_p 705, vrefS_cm 706, and vrefS_m 707, and the LDAC 712 is controllable via reference signal inputs vrefL_p 702, vrefL_cm 703, and vrefL_m 704. The full-scale range of the SDAC 711 is defined by vrefS_p 705 and vrefS_m 707 and the full-scale range of the LDAC 712 is defined by vrefL_p 702 and vrefL_m 704. The reference signal inputs vrefS_cm 706 and vrefL_cm 703 are common-mode voltages; typically selected - respectively - as the mean value of vrefS_p 705 and vrefS_m 707, and as the mean value of vrefL_p 702 and vrefL_m 704. In some DAC implementations, the reference signal inputs 706, 703 are omitted.

In the example illustrated in Figure 3, the feedback DAC 711 is exemplified as a capacitive DAC with binary weighted capacitors C, 2C, 4C, ..., 2^Nbl~²C using top-plate sampling. The feedforward DAC is exemplified as a capacitive DAC with 2^Nbl — 1 unit capacitors C using bottom-plate sampling.

The processing block 713 typically comprises a comparator 792 (CMP; compare with 112 of Figure IB), a register 793 (REG; compare with 113 of Figure IB), and mapping circuitry 743 including DEM 795 (compare with 143, 150 of Figure IB).

As illustrated in Figure 3, the mapping circuitry 743 may comprise an encoder 794 (e.g., a thermometer encoder; compare with 242 of Figure 2A) for providing an input to the DEM 795 based on (at least some elements of) the first digital output 718. Alternatively or additionally, the mapping circuitry 743 may comprise additional logic (LOG) 796 for processing the output of the DEM 795 before providing it for the input 728' of the LDAC 712. For example, the output of the DEM circuitry 795 may be gated until a number of decisions have been made via the SDAC 711, or until a certain time has passed. Thus, the logic 796 may initially output a default state to the LDAC 712, and may later (e.g., after a predefined number of decision cycles) forward the output of the DEM circuitry 795 to the LDAC 712. One or more portions of the processing block 713 (e.g., the register 793 and the additional logic 796) may be operated based on a clock signal 790.

The LDAC 712 may be configured to convert Nbl bits into the residue 727; using 2^Nbl — 1 unit cells that are controlled by switch control signals 728' (e.g., c, d and d_n) derived from thermometer coded bits, and with a length of N_dem, where N_dem corresponds to the number of elements output from the DEM.

In a typical example, the switch control signals 728' for each weight is composed of c, d, and d_n. When c is active (e.g., high or 1) the bottom side of the associated capacitor is connected to reference signal input vrefL_cm, when d is active (e.g., high or 1) the bottom side of the associated capacitor is connected to reference signal input vrefL_p, and when d_n is active (e.g., high or 1) the bottom side of the associated capacitor is connected to reference signal input vrefL_m. In a DAC with differential signal representation there are two single-ended DAC sections where one of the sections have d and d_n interchanged (compared to the other section).

The switch control signals 728' for each weight in the LDAC 712 may be set to {c,d,d_n}={l,0,0} before there is a decision for the weight (i.e., the LDAC 712 will produce a zero output contribution 727 for said weight in a differential signal representation). When a decision has been made for a weight, the switch control signals 728' is set to {c,d,d_n}={0,l,0} or {c,d,d_n}={0,0,l} depending on the decision, where d_n corresponds to the inverse of d once a decision has been made.

The SDAC 711 may convert one less bit (final decision is not used) into the residue 717 since the residue 717 is only used within the decision loop of the SDAC. Thus, the SDAC 711 may be configured to convert Nbl — 1 bits into the residue 717; using 2^WZ,1_1 — 1 unit cells that are grouped into binary weighted sections (e.g., compare with the capacitors in 711 of Figure 3).

The operation of the ADC stage 730 may be exemplified as follows. First, the input signal 701 is sampled onto both the SDAC 711 and the LDAC 712, with LDAC input values s=l, c=0, d=0, d_n=0 and SDAC input values s=l and vrefS_cm 706 connected. The switch control signal s may be comprised in the input signals 718' and 728', and controls the sampling switches, where s=l means that the sampling switches are closed and s=0 means that the sampling switches are open.

Thus, the conversion starts with a sampling phase with s=l. In the LDAC, all capacitors are connected to the input signal 701 on one (the bottom) terminal and to vrefL_cm 703 on the other (the top) terminal. In the SDAC, all capacitors are connected to the input signal 701 on one (the top) terminal and to vrefS_cm 706 on the other (the bottom) terminal. Thereby, the input signal 701 is sampled on the capacitor bank of both SDAC and LDAC, and the input voltage is stored on the capacitors.

Then, the settings are changed to s=0 and (optionally) c=l. In the LDAC, the switches are controlled to let vrefL_cm 703 be connected to the bottom terminal of all capacitors, and a representation of the input signal 701 (in terms of the voltage stored on the capacitors) will appear at 727. No switching other than opening of the sampling switch is required in the SDAC since a representation of the input signal 701 is already present at 717 due to the top-plate sampling. The comparator 792 is triggered for a first decision based on 717, which will switch the MSB capacitor of the SDAC 711 to vrefS_p 705 or vrefS_m 707. When the comparator 792 takes a decision and changes the state of the switches in the SDAC, the voltage at 717 will shift up or down depending on the decision.

The second decision controls the MSB-1 capacitor, and so on as the successive approximation process continues in the SDAC 711. The decisions are propagated to the mapping circuitry 743 after completion (or sequentially during the conversion), and the DEM 795 randomizes the thermometer coded bits.

The additional logic 796 controls the LDAC unit cells - after decisions are completed, or sequentially during the conversion - where each unit cell is set to c=0, and either d=l or d_n=l (depending on thermometer code). The final setting of the switches in the LDAC (before residue amplification in 716) may be to let the bottom terminal of each capacitor be connected to either vrefL_p 702 or vrefL_m 704 (depending on the DEM output).

In one example, the LDAC is idle until all bits are converted in the SDAC. For example, the following three states may be executed: (1) Sampling of input signal 701 by s=l, c=0, d=0, d_n=0, (2) Conversion in SDAC and LDAC idle by s=0, c=l, d=0, d_n=0, and (3) Residue generation in LDAC via data propagation from DEM by s=0, c=0, and - for each unit cell - {d,d_n}={l,0} or {d,d_n}={0,l}. Figure 4 illustrates example operation steps 400 of a SAR ADC stage according to some embodiments. For example, the operation steps 400 may refer to a scenario where the N_C1 first decisions from the SDAC are randomized by DEM, and the subsequent N_c2 decisions have a static association to unit cells in the LDAC. If N_c2 is zero, all decisions of the SDAC are randomized by DEM. Increasing the value of N_c2 generally leads to decreased processing delay for LDAC settling, while decreasing the value of N_c2 generally leads to improved management of non-linearities due to more extensive averaging.

In step 410, the input signal is sampled onto the SDAC and the LDAC. In step 420, initial control for LDAC is provided via DEM (e.g., as exemplified in connection with Figure 3). In step 430, the SDAC runs some decision cycles; more particularly N_C1 decision cycles. In step 440, updated control for LDAC is provided via DEM based on the N_C1 decisions (e.g., as exemplified in connection with Figure 3). In step 450, the DEM is bypassed for the remaining N_c2 decision cycles; to reduce the processing delay. In step 460, the SDAC runs the remaining decision cycles; more particularly N_c2 decision cycles. If N_c2 is zero, steps 450 and 460 are omitted.

Figure 5 schematically illustrates an example time-interleaved (Tl) ADC according to some embodiments, wherein the Tl ADC is configured to convert an input signal 510 to the digital domain.

The Tl ADC comprises a plurality N_ch of constituent ADCs (subADC) 510, 520, 530 (e.g., each corresponding to a channel). The subADCs may sequentially sample and convert the input signal 501, e.g., triggered by respective clock phases <p_t 505, 506, 507.

Each of the constituent ADCs 510, 520, 530 comprises an ADC as described above (e.g., the multi-stage ADC 100 of Figure 1A, where at least one stage corresponds to 110 of Figure IB and/or to 730 of Figure 3). Thus, each of the constituent ADCs 510, 520, 530 comprises a respective DEM 511, 521, 531 applying respective time-varying element permutations (PERM_1, PERM_2, ..., PERM_K) 512, 522, 532.

According to some embodiments, at least two (e.g., all) of the constituent ADCs apply different time-varying element permutations 512, 522, 532. For example, the different time-varying element permutations may be implemented by loading (possibly identical) DEMs with different initial element permutation. For example, the initial element permutation may be loaded responsive to provision of different seed values (or other different indications of the initial element permutation) via respective control signals 502, 503, 504 (compare with 201 of Figure 2A).

De-correlation is achieved with respect to the bit weight mismatches (due to DEM application), as well as with respect to element permutation (due to application of different time-varying element permutations), which may generally flatten the noise spectrum.

The approach exemplified in Figure 5 may have the benefit of increased randomization for timeinterleaving ADC (compared to a Tl ADC without DEM) and/or increased randomization due to the time-interleaving (compared to a single-pipeline ADC with DEM).

Figure 6 schematically illustrates an example electronic apparatus (APP) 600 according to some embodiments. For example, the apparatus 600 may be a communication apparatus (e.g., a wireless communication device for a cellular communications system, or a base station for a cellular communications system). Alternatively or additionally, the apparatus 600 may be a signal receiver.

The apparatus 600 comprises a multi-stage ADC 630 (compare with 100 of Figure 1A), wherein at least one ADC stage (compare with 110 of Figure IB and 730 of Figure 3) comprises DEM circuitry.

In some embodiments, the apparatus 600 comprises a Tl ADC 625 (compare with Figure 5), wherein the Tl ADC 625 comprises a plurality of multi-stage ADCs 630 with DEM circuitry.

In some embodiments, the ADC 630 and/orthe Tl ADC 625 is/are implemented on an integrated circuit (IC) 620.

The described embodiments and their equivalents may be realized in hardware. The embodiments may be performed by general purpose circuitry. Examples of general purpose circuitry include digital signal processors (DSP), central processing units (CPU), co-processor units, field programmable gate arrays (FPGA) and other programmable hardware. Alternatively or additionally, the embodiments may be performed by specialized circuitry, such as application specific integrated circuits (ASIC) or application-specific circuitry within an integrated circuit. The general purpose circuitry and/or the specialized circuitry may, for example, be associated with or comprised in an electronic apparatus such as a communication apparatus. Thus, embodiments may appear within an electronic apparatus (such as a communication apparatus) comprising arrangements, circuitry, and/or logic according to any of the embodiments described herein.

Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and/or is implied from the context in which it is used.

Reference has been made herein to various embodiments. However, a person skilled in the art would recognize numerous variations to the described embodiments that would still fall within the scope of the claims.

For example, the partition of functional blocks into particular units is by no means intended as limiting. Contrarily, these partitions are merely examples. Functional blocks described herein as one unit may be split into two or more units. Furthermore, functional blocks described herein as being implemented as two or more units may be merged into fewer (e.g. a single) unit.

Any feature of any of the embodiments disclosed herein may be applied to any other embodiment, wherever suitable. Likewise, any advantage of any of the embodiments may apply to any other embodiments, and vice versa.

Hence, it should be understood that the details of the described embodiments are merely examples brought forward for illustrative purposes, and that all variations that fall within the scope of the claims are intended to be embraced therein.

Claims

1. An analog-to-digital converter, ADC, (630) configured to output a digital representation (199) of an ADC input, the ADC comprising: a first stage (110, 730) for providing a first digital output (118, 718) based on a first stage input signal (101, 701) and a second stage (120) for providing a second digital output (128) based on a second stage input signal (102), wherein the first digital output corresponds to a first digital value part for the digital representation and the second digital output corresponds to a second digital value part for the digital representation, wherein the first stage is a successive approximation register, SAR, ADC stage, which comprises a feedback digital-to-analog converter, DAC, (141, 711) configured to provide a feedback analog representation of the first digital output for convergence of the first digital output, and a feedforward DAC (142, 712) configured to provide a feedforward analog representation of the first digital output for generation of the second stage input signal, and wherein the first stage further comprises mapping circuitry (143, 794, 795, 796) configured to provide a representation (160, 728) of the first digital output (118, 718) to the feedforward DAC, wherein the mapping circuitry comprises dynamic element matching, DEM, circuitry (150, 243, 795, 511, 521, 531) configured to apply time-varying element permutation.

2. The ADC of claim 1, wherein the feedforward DAC is thermometer coded and the mapping circuitry further comprises a thermometer encoder (242, 794) configured to encode at least some elements of the first digital output into a corresponding thermometer codeword.

3. The ADC of claim 2, wherein the mapping circuitry is configured to provide the thermometer codeword to the DEM circuitry.

4. The ADC of any of claims 2 through 3, wherein the mapping circuitry is configured to provide remaining, non-encoded, elements of the first digital output directly to the DEM circuitry.

5. The ADC of any of claims 1 through 4, wherein the time-varying permutation is pseudo- randomly changing over time.

6. The ADC of any of claims 1 through 5, wherein the DEM circuitry is configured to receive a control signal (502, 503, 504) indicative of an initial element permutation.

7. The ADC of any of claims 1 through 6, wherein the DEM circuitry comprises one or more shift registers configured to provide the time-varying element permutation.

8. The ADC of any of claims 1 through 7, wherein the feedback DAC is smaller than the feedforward DAC.

9. The ADC of any of claims 1 through 8, wherein the first stage further comprises a feedback

DAC amplifier (145) that is configured to provide the first stage input signal - correspondingly amplified - to the feedback DAC and/or a feedforward DAC amplifier (146) that is configured to provide the first stage input signal - correspondingly amplified - to the feedforward DAC.

10. The ADC of claim 9, wherein the feedback DAC amplifier and/or the feedforward DAC amplifier is/are configured to amplify the first stage input signal in correspondence with a difference in range between the feedback DAC and the feedforward DAC.

11. A time-interleaved, Tl, analog-to-digital converter, ADC, (625) comprising two or more constituent ADCs (510, 520, 530), wherein each of the two or more constituent ADCs comprises an ADC according to any of claims 1 through 10.

12. The Tl ADC of claim 10, wherein at least two of the two or more constituent ADCs apply different time-varying element permutations (512, 522, 532).

13. An integrated circuit (620) comprising the ADC (630) of any of claims 1 through 10, and/or the Tl ADC (625) of any of claims 11 through 12.

14. An electronic apparatus (600) comprising the ADC (630) of any of claims 1 through 10, and/or the Tl ADC (625) of any of claims 11 through 12, and/or the integrated circuit (620) of claim 13.

15. The electronic apparatus (600) of claim 19, wherein the electronic apparatus is a signal receiver.

16. The electronic apparatus (600) of claim 19, wherein the electronic apparatus is a communication apparatus.

17. The electronic apparatus (600) of claim 19, wherein the communication apparatus is a wireless communication device for a cellular communications system.

18. The electronic apparatus (600) of claim 19, wherein the communication apparatus is a base station for a cellular communications system.