EP4690276A1 - Method for manufacturing a single heterojunction semiconductor device and such a single heterojunction semiconductor device - Google Patents

Method for manufacturing a single heterojunction semiconductor device and such a single heterojunction semiconductor device

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Publication number
EP4690276A1
EP4690276A1 EP24718296.7A EP24718296A EP4690276A1 EP 4690276 A1 EP4690276 A1 EP 4690276A1 EP 24718296 A EP24718296 A EP 24718296A EP 4690276 A1 EP4690276 A1 EP 4690276A1
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EP
European Patent Office
Prior art keywords
layer
germanium
silicon
epitaxial
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP24718296.7A
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German (de)
French (fr)
Inventor
Giordano SCAPPUCCI
Alberto Tosato
Maximilian Florian RUSS
Lucas Erik Adriaan STEHOUWER
Sammak AMIR
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Technische Universiteit Delft
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Technische Universiteit Delft
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Publication date
Application filed by Technische Universiteit Delft filed Critical Technische Universiteit Delft
Publication of EP4690276A1 publication Critical patent/EP4690276A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/383—Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects
    • H10D48/3835—Semiconductor qubit devices comprising a plurality of quantum mechanically interacting semiconductor quantum dots, e.g. Loss-DiVincenzo spin qubits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
    • H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
    • H10F30/28—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices being characterised by field-effect operation, e.g. junction field-effect phototransistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/12—Active materials
    • H10F77/122—Active materials comprising only Group IV materials
    • H10F77/1223—Active materials comprising only Group IV materials characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3211—Silicon, silicon germanium or germanium

Definitions

  • the invention relates to a method for manufacturing a single heterojunction semiconductor device. Moreover, the invention relates to a single heterojunction semiconductor device.
  • heterostructure devices based on semiconductor layer structures are known in which an interface is formed between two semiconductor layers with different band structure for each of the layers.
  • heterostructure devices comprise a gate electrode near the interface to create a conductive channel therein by means of an electrical field on the gate electrode.
  • Heterostructure semiconductor devices can be used for example in fast field effect transistor devices, active optical devices, photo detector devices, photovoltaic cells, fast diodes, and gate defined semiconductor quantum dot devices for e.g. spinqubit applications.
  • Heterostructure semiconductor devices can be created from silicon, germanium and silicon-germanium alloy (SiGe alloy) based materials. This compatibility allows to use microelectronics processing technology to create small scale heterostructure devices and integrate these in large numbers into a single chip.
  • Si and Ge based heterostructure devices are typically Si or Ge Metal Oxide Semiconductor (Si-MOS, Ge-MOS) and strained Si or strained Ge layers on strain- relaxed SiGe buffer layers (sSi/SiGe, sGe/SiGe) grown on silicon substrate.
  • Si-MOS Si Metal Oxide Semiconductor
  • Ge-MOS Ge Metal Oxide Semiconductor
  • strained Si or strained Ge layers on strain- relaxed SiGe buffer layers sSi/SiGe, sGe/SiGe
  • a requirement for heterostructure devices is that the crystalline layers that form the conductive channel at their interface should be lattice-matched to the underlying substrate to avoid defects that could result in leakage, recombination of the charge carriers, and would compromise the uniformity of the electrical potential landscape in the channel. This requirement is difficult to meet and adversely limits further progress of the technology.
  • a conductive channel for electron or hole gas can be created at the semiconductor/dielectric interface, but since the interface contains structural defects between the crystalline silicon or germanium and the amorphous dielectric, scattering for electron/holes transport and deformation of the intended potential as defined from the top gate stack for quantum dots can arise.
  • a semiconductor layer stack is to be grown coherently on a SIGe substrate (layer) to avoid lattice defects.
  • a SiGe substrate layer is grown on a stack of an intermediate (graded) SiGe buffer layer arranged on Si substrate.
  • Such a SiGe substrate layer typically contains lattice defects arising from plastic deformation of the SiGe buffer layer, which at the interface with the strained Si or strained Ge cause imperfections that lead to loss of charge carriers from the conductive channel, strain fluctuations within the channel, scattering for electron/holes transport and deformation of the intended potential as defined from the top gate stack for quantum dots.
  • the conductive channel is capped by an epitaxial SiGe barrier and upon the application of an electric field charge carriers can be accumulated in a quantum well at the interface.
  • Charge carriers trapped in the above described defects or unstable charge configurations close to the defect typically cause poor yield of heterostructure devices and decoherence effects for qubits in the quantum well, due to charge noise in the system, and also cause deformation of the intended potential defined from the top gate stack for quantum dots formation.
  • a method for manufacturing a semiconductor device comprising: providing a monocrystalline germanium substrate, creating a layer stack comprising a germanium layer, a silicon-germanium alloy layer and a gate layer structure on a surface of the monocrystalline germanium substrate, the creation comprising: creating the germanium layer enriched in 70 Geas a surface layer on the monocrystalline germanium substrate as a monocrystalline germanium layer that is epitaxial with respect to the crystal lattice of the germanium substrate; creating on the epitaxial germanium layer the silicon-germanium alloy layer as a monocrystalline layer that is epitaxial and elastically strained under tensile stress with respect to the crystal lattice of the monocrystalline germanium substrate; creating on the silicon-germanium layer the gate layer structure; wherein a heterostructure comprising a lattice matched interface is formed between the silicon-germanium alloy layer and the epitaxial germanium layer for a conductive channel for hole carriers, the channel extending vertically in at least the epitaxial germanium
  • a tensile strain is present in the silicon-germanium alloy layer and a band alignment is present at the single heterojunction between the tensile-strained SiGe barrier and the Ge substrate that confines a conductive electron or hole channel in the monocrystalline Ge substrate.
  • the entire layer stack of the heterostructure device exhibits a single in-plane lattice parameter that is the same as for the Ge substrate (i.e., lattice- matched), which causes that the number of lattice defects is significantly reduced. Accordingly, the quality of the conductive channel and its uniformity is improved and leakage and/or recombination of charge carriers at the interface is reduced. In particular in heterostructures for quantum dot applications, device yield is improved and qubit decoherence is reduced.
  • the tensile strain in the SiGe alloy layer will result in a change of the band structure of the SiGe alloy and of the optical properties thereof, such as photon adsorption.
  • the strained SiGe alloy layer becomes an optically active medium in the proximity of the conductive channel where a quantum dot device, in particular a qubit quantum dot, is defined.
  • [0014] comprises: preceding the creation of the epitaxial silicon-germanium alloy layer, creating an isotopically purified germanium layer enriched in 70 Ge as a surface layer on the monocrystalline germanium substrate; wherein the isotopically purified germanium layer is grown as an epitaxial layer with respect to the crystal lattice of the germanium substrate, and the silicon-germanium alloy layer is disposed on the isotopically purified germanium layer and is epitaxial with respect to the crystal lattice of the germanium layer.
  • the hyperfine interaction with nuclear spins of atoms at the interface is strongly reduced by the removal of isotopes with an odd number of nucleons (protons and neutrons).
  • Having a 70 Ge layer below the SiGe alloy layer and on top of the Ge substrate thus makes the operation of the heterostructure device less susceptible for magnetic and electrical environmental disturbances.
  • the epitaxial silicon-germanium alloy layer consists of isotopically purified silicon enriched in 28 Si and isotopically purified germanium enriched in 70 Ge.
  • a semiconductor device comprising: a layer stack comprising a monocrystalline germanium substrate, a silicon-germanium alloy layer and a gate layer structure the silicon-germanium alloy layer being disposed on the monocrystalline germanium substrate, and the gate layer structure being disposed on the silicon-germanium alloy layer, at a side of the silicon-germanium alloy layer facing away from the germanium substrate, wherein the silicon-germanium alloy layer is a monocrystalline layer and epitaxial with respect to the monocrystalline germanium substrate and is disposed on a surface layer of the monocrystalline germanium substrate consisting of a germanium layer enriched in 70 Ge isotope, the germanium layer being epitaxial with respect to the crystal lattice of the germanium substrate and the epitaxial silicon-germanium alloy layer being epitaxial and elastically strained under tensile stress with respect to the crystal lattice of the epitaxial germanium layer, a heterostructure comprising a lattice matched interface present between the silicon-
  • the silicon-germanium alloy layer is epitaxial on the germanium surface, the crystal lattice of the silicon-germanium alloy layer is comparatively elongated along the interface to match the crystal lattice of the germanium layer, which is substantially undisturbed.
  • a tensile strain is present in the silicon-germanium alloy layer and a band alignment is present at the single heterojunction between the tensile- strained SiGe barrier and the Ge substrate that confines a conductive electron or hole channel in the monocrystalline Ge substrate.
  • the germanium layer consists of at least 97%at 70 Ge isotope.
  • the reduction of 73 Ge atoms in the isotopically purified Ge layer at the interface is considered beneficial in this respect.
  • the amount of 73 Ge is reduced to 0.08at% or less in the purified germanium layer.
  • the monocrystalline germanium substrate consists of germanium enriched in 70 Ge.
  • the epitaxial silicon-germanium alloy layer consists of isotopically purified silicon enriched in 28 Si and isotopically purified germanium enriched in 70 Ge.
  • the removal of isotopes with an odd number of nucleons provides that the hyperfine interaction with nuclear spins of atoms at the interface is strongly reduced.
  • the epitaxial silicon-germanium alloy layer (SiGe alloy layer) consists of SixGe-i-x alloy, with a composition selected from a range 0.05 ⁇ x ⁇ 0.60.
  • the crystal lattice parameter can be adapted relative to the crystal lattice parameter of germanium. This allows to modify the tensile strain in the epitaxial silicon-germanium alloy layer.
  • the silicon-germanium alloy has a composition Sio.2Geo.8-
  • the epitaxial silicon-germanium alloy layer has a thickness between about 5 nm and about 150 nm.
  • the thickness of the silicon-germanium alloy layer is limited to be below a critical thickness for initiating plastic deformation in the silicon-germanium alloy layer, to avoid that lattice defects in the silicon-germanium alloy layer are generated.
  • the thickness of the strained SiGe layer is chosen preferably as thick as possible since a thicker layer provides better shielding from defects at the interface between the gate-stack (gate electrode and gate dielectric layers) and the semiconductor heterostructure and above.
  • the isotopically purified germanium layer has a thickness between about 5 nm and about 1000 nm.
  • a minimum thickness of the 70 Ge layer is driven by a desired minimum amount of nuclear spin shielding from the germanium substrate, whereas its maximum thickness is restricted by practical reasons.
  • a semiconductor device as described above, wherein a thin capping layer of silicon or germanium is disposed between the epitaxial silicon-germanium alloy layer and the gate layer structure. Also, a capping layer comprising both Si and Ge may be formed.
  • the capping layer is partially or completely oxidized resulting in one selected from a silicon dioxide layer, a germanium oxide or a combination of Si and Ge oxides depending on the composition of the thin capping layer created.
  • the silicon dioxide layer or the germanium oxide layer as isotopically purified are substantially depleted of 29 Si or 73 Ge.
  • the gate layer structure comprises a gate electrode layer and a dielectric layer, the dielectric layer disposed between the gate electrode layer and the epitaxial silicon-germanium alloy layer.
  • the dielectric layer comprises a dielectric selected from AI2O3, HfO2, SiO2, or a combination of two or more thereof, stacked on top of each other.
  • the gate electrode may comprise Ti, Pt, Pd, TIN, Al, Ag, Cu, or any combination thereof.
  • Figure 1 schematically shows a cross-section of a semiconductor device according to an embodiment
  • Figure 2A, 2B schematically show a diagram of band structure at the interface between the Ge layer and the SiGe alloy layer and a diagram of charge carrier density as function of gate voltage.
  • Figure 3 schematically shows a cross-section of a semiconductor device according to an embodiment
  • Figure 4 schematically shows a cross-section of a semiconductor device according to an embodiment.
  • Figure 1 schematically shows a cross-section of a semiconductor device 10 according to an embodiment.
  • the semiconductor device 10 comprises a germanium substrate 100, a silicongermanium alloy layer 110 and a gate structure 120 arranged in a layer stack.
  • the silicon-germanium alloy layer 110 is disposed on a surface of the germanium substrate 100.
  • the gate structure which comprises a dielectric layer 121 and a gate electrode 122, is disposed on a surface of the silicon-germanium alloy layer that faces away from the germanium substrate.
  • the dielectric layer 121 of the gate structure is disposed between the silicon-germanium alloy layer 110 and the gate electrode 122.
  • the germanium substrate 100 is a monocrystalline substrate.
  • the silicon- germanium alloy layer is grown epitaxially on the surface of the monocrystalline substrate, creating an interface.
  • the epitaxy of the SiGe layer and the Ge substrate defines that the interface is coherent in which the crystal lattice of the silicon-germanium alloy layer has a predetermined orientation relative to an orientation of the crystal lattice of the monocrystalline germanium substrate such that the silicon-germanium alloy layer crystal lattice and the crystal lattice of the monocrystalline germanium substrate match without dislocations, disorder or stacking faults.
  • the monocrystalline Ge substrate may be either a (100) or (111 ) substrate but is not limited thereto.
  • the crystal lattice of the SiGe alloy layer is elongated along the interface with the Ge substrate, relative to the crystal lattice of the Ge substrate, which causes a tensile strain in the SiGe alloy layer which modifies the band structure of the SiGe alloy layer.
  • the layer stack 100, 110, 120 forms a heterostructure comprising a lattice matched interface 140 between the silicon-germanium alloy layer and the germanium substrate.
  • a conductive channel 141 for charge carriers can be formed by an electrical potential on the gate electrode.
  • the conductive channel extends vertically predominantly in the Ge substrate. This will be illustrated in more detail with reference to figures 2A and 2B.
  • the lateral dimension of the conductive channel can be controlled.
  • the SiGe alloy layer is epitaxially grown on the monocrystalline Ge substrate by any known layer creation process such as chemical vapour deposition or molecular beam epitaxy.
  • the SiGe alloy has a composition Si x Gei- x , with the Si amount 0.05 ⁇ x ⁇ 0.60.
  • the crystal lattice parameter of the alloy can be modified as known to the skilled in the art. This allows to change the elastic strain of the SiGe alloy layer and the band offset at the interface with the Ge substrate.
  • the SiGe alloy layer has a thickness in a range between about 5 nm and about 150 nm. Due to the elastic strain in the layer, the thickness of the SiGe alloy layer is limited to a value below a critical thickness for initiating plastic deformation, i.e., for creating lattice defects in the SiGe alloy layer.
  • the gate structure is created by any one of chemical vapor deposition, atomic layer deposition, physical vapor deposition and evaporation, as known by the skilled in the art.
  • a thin capping layer 123 is present between the SiGe alloy layer 110 and the gate structure 120.
  • the thin capping layer may comprise a silicon layer, a germanium layer. Or a capping layer comprising both Si and Ge may be formed.
  • the Si or Ge capping layer may be isotopically purified silicon enriched in 28 Si and isotopically purified germanium enriched in 70 Ge (or depleted in amount of 73 Ge).
  • the capping layer may have a thickness of at least an atomic layer upto a few nanometers, for example 5nm.
  • the capping layer may comprise silicon oxide, germanium oxide or a a combination thereof.
  • the capping layer has a thickness between 1 atomic layer and a few nanometers (e.g., about 5 nm).
  • Figures 2A, 2B schematically show an example of a band structure diagram at the interface 140 between the Ge substrate or layer 100 and the SiGe alloy layer 110 and a diagram of charge carrier density as function of gate voltage, respectively.
  • the interface 140 is indicated between the SiGe alloy layer 110 and the Ge substrate 100.
  • the heavy holes band is indicated by the solid HH line
  • the light hole band is indicated by the dash-dotted line LH.
  • the Fermi level for holes is indicated by dashed line F.
  • the heavy holes band and light holes band near the Ge/SiGe interface 140 will be mixed due to the abrupt character of the interface 140.
  • holes Charge carriers
  • the active layer 142 where the charge carriers reside, extends from the interface 140 into the region of the Ge substrate where the energy level of the heavy holes band is above the hole Fermi energy level.
  • Figure 2B illustrates the carrier densities in the active layer 142 and in the SiGe alloy layer 110 at the interface with the dielectric layer 121 .
  • an gate voltage negative direction
  • holes accumulate in the active layer 142.
  • the holes density (solid line 143) increases linearly until states in the triangular well that forms in the SiGe alloy layer at the interface with the dielectric layer 121 become energetically available (dash-dotted line 144). After reaching a voltage where these states become available the holes density in the active layer saturates.
  • Figure 3 schematically shows a cross-section of a semiconductor device 20 according to an embodiment.
  • the semiconductor device 20 according to this embodiment is similar to the semiconductor device 10 as described above with reference to figure 1. Below the differences with the semiconductor device 10 are described in detail.
  • the semiconductor device 20 comprises a germanium substrate 100, a germanium layer 105, a silicon-germanium alloy layer 110 and a gate structure 120 arranged in a layer stack.
  • the epitaxial germanium layer 105 consists of isotopically purified germanium and comprises predominantly 70 Ge isotope. In an embodiment, the epitaxial germanium layer comprises at least 97 at% 70 Ge.
  • the epitaxial germanium layer 105 Since the crystal lattice and thermal expansion coefficients of the epitaxial germanium layer 105 are the same as those of the monocrystalline Ge substrate 100, the epitaxial germanium layer 105 is substantially strain free with respect to the substrate 100.
  • the epitaxial germanium layer 105 is grown by an epitaxial formation process, for example by molecular beam epitaxy, chemical vapour deposition or atomic layer deposition, each using a precursor comprising 70 Ge.
  • the epitaxial germanium layer has a thickness between about 5 nm and about 1000 nm.
  • the layer 105 may be adapted to have sufficient thickness for shielding qubits from hyperfine interaction with nuclear spins arising from the monocrystalline substrate.
  • a monocrystalline germanium substrate is used consisting of isotopically purified Ge, predominantly 70 Ge.
  • the isotopically purified germanium layer 105 or the germanium substrate comprises at least 97 at% 70 Ge.
  • Figure 4 schematically shows a cross-section of a semiconductor device 30 according to an embodiment.
  • the semiconductor device 30 according to this embodiment is similar to the semiconductor device 20 as described above with reference to figure 3. Below the differences with the semiconductor device 20 are described in detail.
  • an epitaxial germanium layer 105 is disposed on the monocrystalline germanium substrate 100 .
  • the epitaxial germanium layer consists of isotopically purified germanium and comprises predominantly 70 Ge isotope. In an embodiment, the epitaxial germanium layer comprises at least 97 at% 70 Ge.
  • An isotopically purified silicon-germanium alloy layer 115 is disposed on a surface of the epitaxial germanium layer 105 that faces away from the germanium substrate 100.
  • the isotopically purified silicon-germanium alloy layer 115 is grown epitaxially on the surface of the epitaxial germanium layer, creating an heterostructure interface 160 at said surface.
  • a location of the conductive channel 161 for charge carriers is indicated in the epitaxial germanium layer 105.
  • the isotopically purified silicon-germanium alloy layer 115 comprises predominantly 28 Si and 70 Ge isotopes, with the Si amount consisting at least 97at% 28 Si, and the Ge amount consisting of at least 97at% 70 Ge.
  • the amount of Si and Ge atoms with an odd number of nucleons at the interface 160 is reduced which has the effect that in case spin-qubits are present at the interface 160 the hyperfine interaction of spin-qubits with nuclear spins of Si and/or Ge and also qubit decoherence is reduced.
  • the epitaxial silicon-germanium alloy layer 115 is grown by an epitaxial formation process, for example by molecular beam epitaxy, chemical vapour deposition or atomic layer deposition using a precursor(s) comprising 28 Si and 70 Ge.
  • the isotopically purified SiGe alloy has a composition Si x Gei. x , with the Si amount 0.05 ⁇ x ⁇ 0.60.
  • the isotopically purified SiGe alloy layer 115 has a thickness in a range between about 5 nm and about 150 nm.
  • the silicon-germanium alloy layer comprises a double layer consisting an isotopically purified SiGe alloy first layer, enriched in 28 Si and 70 Ge, and an not purified SiGe alloy second layer.
  • the isotopically purified SiGe alloy first layer is disposed between the isotopically purified germanium layer and the not purified SiGe alloy second layer.
  • the isotopically purified germanium layer, the isotopically purified SiGe alloy first layer as well as the not purified SiGe alloy second layer are epitaxial with respect to each other and to the monocrystalline germanium substrate.
  • the electron and hole channels formed in the heterojunction semiconductor described above may be used to form electronic devices monolithically integrated and connected to a quantum dot device, in particular a quantum dot qubit device.
  • the electron and hole channels formed in the heterojunction semiconductor described above may host superconducting pairing correlation when electrically contacted (proximitized) by a parent superconductor and form hybrid superconductor-semiconductor devices. Furthermore, this proximitized channel may link qubits at a distance.
  • the single heterojunction device described above may be used as a base layer for solar cells.
  • the isotopically purified 70 Ge and 28 Si 70 Ge layers may have larger thermal conductivity than non-purified Ge and SiGe layers at the operating temperature of qubits (in the order of milliKelvins), which is advantageous for their operation since heating which causes qubit decoherence is reduced by better thermal conduction in isotopically purified Ge and SiGe layers.
  • the semiconductor device can advantageously be applied in cryo-CMOS applications.
  • the semiconductor device 10, 20, 30 as described above can be applied in a field effect transistor, controlled by a gate voltage applied on the gate electrode 122.
  • a field effect transistor can be configured to terahertz switching frequencies.
  • the semiconductor device can be applied as a photovoltaic device converting solar energy into electric energy.
  • the semiconductor device can be used in space based solar cell applications, because in comparison to silicon based photovoltaic devices, the application of germanium substrates provides an improved resistance to damage from cosmic radiation which results in a longer life-time.
  • the semiconductor device can be used as an active optical device in optoelectronic applications.
  • the semiconductor device can be used in photo detector devices, and fast (high speed) diodes.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method for manufacturing a semiconductor device includes: providing a monocrystalline germanium substrate, and creating a layer stack including a germanium layer, a silicon-germanium alloy layer and a gate layer structure on a surface of the monocrystalline germanium substrate. The creation of the layer stack includes: creating the germanium layer enriched in 70Ge as a surface layer on the monocrystalline germanium substrate as a monocrystalline germanium layer that is epitaxial with respect to the crystal lattice of the germanium substrate; creating the silicon-germanium alloy layer between the surface of the epitaxial germanium layer and the gate layer structure, wherein the silicon-germanium alloy layer is a monocrystalline layer grown as epitaxial layer with respect to the crystal lattice of the monocrystalline germanium substrate.

Description

Method for manufacturing a single heterojunction semiconductor device and such a single heterojunction semiconductor device.
FIELD OF THE INVENTION
[0001] The invention relates to a method for manufacturing a single heterojunction semiconductor device. Moreover, the invention relates to a single heterojunction semiconductor device.
BACKGROUND OF THE INVENTION
[0002] From the prior art, heterostructure devices based on semiconductor layer structures are known in which an interface is formed between two semiconductor layers with different band structure for each of the layers.
[0003] Typically such heterostructure devices comprise a gate electrode near the interface to create a conductive channel therein by means of an electrical field on the gate electrode. Heterostructure semiconductor devices can be used for example in fast field effect transistor devices, active optical devices, photo detector devices, photovoltaic cells, fast diodes, and gate defined semiconductor quantum dot devices for e.g. spinqubit applications.
[0004] Heterostructure semiconductor devices can be created from silicon, germanium and silicon-germanium alloy (SiGe alloy) based materials. This compatibility allows to use microelectronics processing technology to create small scale heterostructure devices and integrate these in large numbers into a single chip.
[0005] Si and Ge based heterostructure devices are typically Si or Ge Metal Oxide Semiconductor (Si-MOS, Ge-MOS) and strained Si or strained Ge layers on strain- relaxed SiGe buffer layers (sSi/SiGe, sGe/SiGe) grown on silicon substrate.
[0006] A requirement for heterostructure devices is that the crystalline layers that form the conductive channel at their interface should be lattice-matched to the underlying substrate to avoid defects that could result in leakage, recombination of the charge carriers, and would compromise the uniformity of the electrical potential landscape in the channel. This requirement is difficult to meet and adversely limits further progress of the technology.
[0007] In Si-MOS or Ge-MOS devices a conductive channel for electron or hole gas can be created at the semiconductor/dielectric interface, but since the interface contains structural defects between the crystalline silicon or germanium and the amorphous dielectric, scattering for electron/holes transport and deformation of the intended potential as defined from the top gate stack for quantum dots can arise.
[0008] In strained Si or strained Ge layers, a semiconductor layer stack is to be grown coherently on a SIGe substrate (layer) to avoid lattice defects. In practice a SiGe substrate layer is grown on a stack of an intermediate (graded) SiGe buffer layer arranged on Si substrate. However, such a SiGe substrate layer typically contains lattice defects arising from plastic deformation of the SiGe buffer layer, which at the interface with the strained Si or strained Ge cause imperfections that lead to loss of charge carriers from the conductive channel, strain fluctuations within the channel, scattering for electron/holes transport and deformation of the intended potential as defined from the top gate stack for quantum dots.
[0009] In case the heterostructure device is to be used for quantum dot applications, the conductive channel is capped by an epitaxial SiGe barrier and upon the application of an electric field charge carriers can be accumulated in a quantum well at the interface. Charge carriers trapped in the above described defects or unstable charge configurations close to the defect typically cause poor yield of heterostructure devices and decoherence effects for qubits in the quantum well, due to charge noise in the system, and also cause deformation of the intended potential defined from the top gate stack for quantum dots formation.
[0010] It is an object of the invention to provide a method for manufacturing a single heterojunction semiconductor device that overcomes or mitigates the disadvantages of the prior art. Accordingly, the invention provides a single heterojunction semiconductor device.
SUMMARY OF THE INVENTION
According to the invention there is provided a method for manufacturing a semiconductor device comprising: providing a monocrystalline germanium substrate, creating a layer stack comprising a germanium layer, a silicon-germanium alloy layer and a gate layer structure on a surface of the monocrystalline germanium substrate, the creation comprising: creating the germanium layer enriched in 70Geas a surface layer on the monocrystalline germanium substrate as a monocrystalline germanium layer that is epitaxial with respect to the crystal lattice of the germanium substrate; creating on the epitaxial germanium layer the silicon-germanium alloy layer as a monocrystalline layer that is epitaxial and elastically strained under tensile stress with respect to the crystal lattice of the monocrystalline germanium substrate; creating on the silicon-germanium layer the gate layer structure; wherein a heterostructure comprising a lattice matched interface is formed between the silicon-germanium alloy layer and the epitaxial germanium layer for a conductive channel for hole carriers, the channel extending vertically in at least the epitaxial germanium layer enriched in 70Ge during exposure to an electrical potential on the gate layer structure [0011] Importantly, due to the epitaxial growth of the silicon-germanium alloy layer on the germanium substrate’s surface, the crystal lattice of the silicon-germanium alloy layer is comparatively elongated along the interface to match the crystal lattice of the germanium layer, which is substantially undisturbed. As a result thereof, a tensile strain is present in the silicon-germanium alloy layer and a band alignment is present at the single heterojunction between the tensile-strained SiGe barrier and the Ge substrate that confines a conductive electron or hole channel in the monocrystalline Ge substrate.
[0012] Advantageously, due to the epitaxy of the strained silicon-germanium alloy layer on the germanium substrate, the entire layer stack of the heterostructure device exhibits a single in-plane lattice parameter that is the same as for the Ge substrate (i.e., lattice- matched), which causes that the number of lattice defects is significantly reduced. Accordingly, the quality of the conductive channel and its uniformity is improved and leakage and/or recombination of charge carriers at the interface is reduced. In particular in heterostructures for quantum dot applications, device yield is improved and qubit decoherence is reduced.
[0013] Additionally, the tensile strain in the SiGe alloy layer will result in a change of the band structure of the SiGe alloy and of the optical properties thereof, such as photon adsorption. As a result, the strained SiGe alloy layer becomes an optically active medium in the proximity of the conductive channel where a quantum dot device, in particular a qubit quantum dot, is defined.
[0014] According to the invention as described above comprises: preceding the creation of the epitaxial silicon-germanium alloy layer, creating an isotopically purified germanium layer enriched in 70Ge as a surface layer on the monocrystalline germanium substrate; wherein the isotopically purified germanium layer is grown as an epitaxial layer with respect to the crystal lattice of the germanium substrate, and the silicon-germanium alloy layer is disposed on the isotopically purified germanium layer and is epitaxial with respect to the crystal lattice of the germanium layer.
Advantageously, by providing the isotopically purified germanium layer the hyperfine interaction with nuclear spins of atoms at the interface is strongly reduced by the removal of isotopes with an odd number of nucleons (protons and neutrons). Having a 70Ge layer below the SiGe alloy layer and on top of the Ge substrate thus makes the operation of the heterostructure device less susceptible for magnetic and electrical environmental disturbances.
[0015] According to an embodiment, there is provided a method as described above wherein the epitaxial silicon-germanium alloy layer consists of isotopically purified silicon enriched in 28Si and isotopically purified germanium enriched in 70Ge.
[0016] By providing the isotopically purified silicon-germanium alloy layer the hyperfine interaction with nuclear spins of atoms at the interface is strongly reduced by the removal of isotopes with an odd number of nucleons (protons and neutrons), making the operation of the heterostructure device less susceptible for magnetic and electrical environmental disturbances.
[0017] According to the invention there is provided a semiconductor device comprising: a layer stack comprising a monocrystalline germanium substrate, a silicon-germanium alloy layer and a gate layer structure the silicon-germanium alloy layer being disposed on the monocrystalline germanium substrate, and the gate layer structure being disposed on the silicon-germanium alloy layer, at a side of the silicon-germanium alloy layer facing away from the germanium substrate, wherein the silicon-germanium alloy layer is a monocrystalline layer and epitaxial with respect to the monocrystalline germanium substrate and is disposed on a surface layer of the monocrystalline germanium substrate consisting of a germanium layer enriched in 70Ge isotope, the germanium layer being epitaxial with respect to the crystal lattice of the germanium substrate and the epitaxial silicon-germanium alloy layer being epitaxial and elastically strained under tensile stress with respect to the crystal lattice of the epitaxial germanium layer, a heterostructure comprising a lattice matched interface present between the silicon- germanium alloy layer and the epitaxial germanium layer for a conductive channel for hole carriers, the channel extending vertically in at least the epitaxial germanium layer enriched in 70Ge during exposure to an electrical potential on the gate layer structure. [0018] Since the silicon-germanium alloy layer is epitaxial on the germanium surface, the crystal lattice of the silicon-germanium alloy layer is comparatively elongated along the interface to match the crystal lattice of the germanium layer, which is substantially undisturbed. As a result thereof, a tensile strain is present in the silicon-germanium alloy layer and a band alignment is present at the single heterojunction between the tensile- strained SiGe barrier and the Ge substrate that confines a conductive electron or hole channel in the monocrystalline Ge substrate. [0019] According to an embodiment, there is provided a semiconductor device as described above, wherein the germanium layer consists of at least 97%at 70Ge isotope. [0020] In particular, the reduction of 73Ge atoms in the isotopically purified Ge layer at the interface is considered beneficial in this respect. In an embodiment the amount of 73Ge is reduced to 0.08at% or less in the purified germanium layer.
[0021] In an alternative embodiment, there is provided a semiconductor device as described above, wherein the monocrystalline germanium substrate consists of germanium enriched in 70Ge.
[0022] According to an embodiment, there is provided a semiconductor device as described above, wherein the epitaxial silicon-germanium alloy layer consists of isotopically purified silicon enriched in 28Si and isotopically purified germanium enriched in 70Ge.
[0023] Advantageously, the removal of isotopes with an odd number of nucleons (in particular 29Si and 73Ge) provides that the hyperfine interaction with nuclear spins of atoms at the interface is strongly reduced.
[0024] According to an embodiment, there is provided a semiconductor device as described above wherein the epitaxial silicon-germanium alloy layer (SiGe alloy layer) consists of SixGe-i-x alloy, with a composition selected from a range 0.05 < x < 0.60.
[0025] Advantageously, by adjusting the composition of the silicon-germanium alloy the crystal lattice parameter can be adapted relative to the crystal lattice parameter of germanium. This allows to modify the tensile strain in the epitaxial silicon-germanium alloy layer. In an embodiment, the silicon-germanium alloy has a composition Sio.2Geo.8- [0026] According to an embodiment, there is provided a semiconductor device as described above, wherein the epitaxial silicon-germanium alloy layer has a thickness between about 5 nm and about 150 nm.
The thickness of the silicon-germanium alloy layer is limited to be below a critical thickness for initiating plastic deformation in the silicon-germanium alloy layer, to avoid that lattice defects in the silicon-germanium alloy layer are generated.
However, the thickness of the strained SiGe layer is chosen preferably as thick as possible since a thicker layer provides better shielding from defects at the interface between the gate-stack (gate electrode and gate dielectric layers) and the semiconductor heterostructure and above.
[0027] According to an embodiment, there is provided a semiconductor device as described above, wherein the isotopically purified germanium layer has a thickness between about 5 nm and about 1000 nm. A minimum thickness of the 70Ge layer is driven by a desired minimum amount of nuclear spin shielding from the germanium substrate, whereas its maximum thickness is restricted by practical reasons.
[0028] According to an embodiment, there is provided a semiconductor device as described above, wherein a thin capping layer of silicon or germanium is disposed between the epitaxial silicon-germanium alloy layer and the gate layer structure. Also, a capping layer comprising both Si and Ge may be formed.
[0029] In a further embodiment, such Si or Ge capping layer comprise isotopically purified silicon enriched in 28Si and isotopically purified germanium enriched in 70Ge. [0030] The capping layer may have a thickness of at least an atomic layer upto a few nanometers, for example about 5 nm.
[0031] In a further embodiment, the capping layer is partially or completely oxidized resulting in one selected from a silicon dioxide layer, a germanium oxide or a combination of Si and Ge oxides depending on the composition of the thin capping layer created. In a further embodiment, the silicon dioxide layer or the germanium oxide layer as isotopically purified are substantially depleted of 29Si or 73Ge.
[0032] According to an embodiment, there is provided a semiconductor device as described above, wherein the gate layer structure comprises a gate electrode layer and a dielectric layer, the dielectric layer disposed between the gate electrode layer and the epitaxial silicon-germanium alloy layer.
In a preferred embodiment, the dielectric layer comprises a dielectric selected from AI2O3, HfO2, SiO2, or a combination of two or more thereof, stacked on top of each other. The gate electrode may comprise Ti, Pt, Pd, TIN, Al, Ag, Cu, or any combination thereof.
DESCRIPTION OF THE DRAWINGS
[0033] The invention will be explained in more detail below with reference to drawings in which illustrative embodiments thereof are shown. The drawings are meant for illustrative purposes only, and do not serve as restriction of the scope or the protection as laid down by the appended claims.
[0034] Figure 1 schematically shows a cross-section of a semiconductor device according to an embodiment;
[0035] Figure 2A, 2B schematically show a diagram of band structure at the interface between the Ge layer and the SiGe alloy layer and a diagram of charge carrier density as function of gate voltage. [0036] Figure 3 schematically shows a cross-section of a semiconductor device according to an embodiment;
[0037] Figure 4 schematically shows a cross-section of a semiconductor device according to an embodiment.
[0038] In the drawings, identical or similar elements are indicated by the same reference sign or number.
DESCRIPTION OF EMBODIMENTS
[0039] Figure 1 schematically shows a cross-section of a semiconductor device 10 according to an embodiment.
[0040] The semiconductor device 10 comprises a germanium substrate 100, a silicongermanium alloy layer 110 and a gate structure 120 arranged in a layer stack. The silicon-germanium alloy layer 110 is disposed on a surface of the germanium substrate 100. The gate structure which comprises a dielectric layer 121 and a gate electrode 122, is disposed on a surface of the silicon-germanium alloy layer that faces away from the germanium substrate. The dielectric layer 121 of the gate structure is disposed between the silicon-germanium alloy layer 110 and the gate electrode 122.
[0041] The germanium substrate 100 is a monocrystalline substrate. The silicon- germanium alloy layer is grown epitaxially on the surface of the monocrystalline substrate, creating an interface. The epitaxy of the SiGe layer and the Ge substrate defines that the interface is coherent in which the crystal lattice of the silicon-germanium alloy layer has a predetermined orientation relative to an orientation of the crystal lattice of the monocrystalline germanium substrate such that the silicon-germanium alloy layer crystal lattice and the crystal lattice of the monocrystalline germanium substrate match without dislocations, disorder or stacking faults.
In this respect the monocrystalline Ge substrate may be either a (100) or (111 ) substrate but is not limited thereto.
[0042] Due to the epitaxial lattice match, in this case, the crystal lattice of the SiGe alloy layer is elongated along the interface with the Ge substrate, relative to the crystal lattice of the Ge substrate, which causes a tensile strain in the SiGe alloy layer which modifies the band structure of the SiGe alloy layer.
[0043] In this manner the layer stack 100, 110, 120 forms a heterostructure comprising a lattice matched interface 140 between the silicon-germanium alloy layer and the germanium substrate. At the interface 140, a conductive channel 141 for charge carriers can be formed by an electrical potential on the gate electrode. The conductive channel extends vertically predominantly in the Ge substrate. This will be illustrated in more detail with reference to figures 2A and 2B.
[0044] The skilled in the art will appreciate that depending on the layout of the gate electrode structure and the applied gate voltage during operation, the lateral dimension of the conductive channel can be controlled.
[0045] The SiGe alloy layer is epitaxially grown on the monocrystalline Ge substrate by any known layer creation process such as chemical vapour deposition or molecular beam epitaxy.
[0046] The SiGe alloy has a composition SixGei-x, with the Si amount 0.05 < x < 0.60. [0047] By adapting the composition of the alloy, the crystal lattice parameter of the alloy can be modified as known to the skilled in the art. This allows to change the elastic strain of the SiGe alloy layer and the band offset at the interface with the Ge substrate. In an embodiment, the SiGe alloy has the composition Sio.2Geo.8 (x=0.2).
[0048] The SiGe alloy layer has a thickness in a range between about 5 nm and about 150 nm. Due to the elastic strain in the layer, the thickness of the SiGe alloy layer is limited to a value below a critical thickness for initiating plastic deformation, i.e., for creating lattice defects in the SiGe alloy layer.
[0049] The gate structure is created by any one of chemical vapor deposition, atomic layer deposition, physical vapor deposition and evaporation, as known by the skilled in the art.
[0050] In a further embodiment, a thin capping layer 123 is present between the SiGe alloy layer 110 and the gate structure 120. The thin capping layer may comprise a silicon layer, a germanium layer. Or a capping layer comprising both Si and Ge may be formed. The Si or Ge capping layer may be isotopically purified silicon enriched in 28Si and isotopically purified germanium enriched in 70Ge (or depleted in amount of 73Ge). The capping layer may have a thickness of at least an atomic layer upto a few nanometers, for example 5nm. In a further embodiment the capping layer may comprise silicon oxide, germanium oxide or a a combination thereof.
Typically, the capping layer has a thickness between 1 atomic layer and a few nanometers (e.g., about 5 nm).
[0051] Figures 2A, 2B schematically show an example of a band structure diagram at the interface 140 between the Ge substrate or layer 100 and the SiGe alloy layer 110 and a diagram of charge carrier density as function of gate voltage, respectively.
[0052] In Figure 2A, a band alignment of the SiGe/Ge heterojunction at gate voltage = -0.65 V is shown in direction z perpendicular to the interface 140. The interface 140 is indicated between the SiGe alloy layer 110 and the Ge substrate 100. The heavy holes band is indicated by the solid HH line, the light hole band is indicated by the dash-dotted line LH. The Fermi level for holes is indicated by dashed line F. The heavy holes band and light holes band near the Ge/SiGe interface 140 will be mixed due to the abrupt character of the interface 140. Upon applying an electric field, holes (charge carriers) will accumulate in an active layer 142 close to the interface 140. The active layer 142 where the charge carriers reside, extends from the interface 140 into the region of the Ge substrate where the energy level of the heavy holes band is above the hole Fermi energy level.
[0053] Figure 2B illustrates the carrier densities in the active layer 142 and in the SiGe alloy layer 110 at the interface with the dielectric layer 121 . Upon applying an gate voltage (negative direction) holes accumulate in the active layer 142. The holes density (solid line 143) increases linearly until states in the triangular well that forms in the SiGe alloy layer at the interface with the dielectric layer 121 become energetically available (dash-dotted line 144). After reaching a voltage where these states become available the holes density in the active layer saturates.
[0054] Figure 3 schematically shows a cross-section of a semiconductor device 20 according to an embodiment.
[0055] The semiconductor device 20 according to this embodiment is similar to the semiconductor device 10 as described above with reference to figure 1. Below the differences with the semiconductor device 10 are described in detail.
[0056] The semiconductor device 20 comprises a germanium substrate 100, a germanium layer 105, a silicon-germanium alloy layer 110 and a gate structure 120 arranged in a layer stack.
[0057] On the monocrystalline germanium substrate 100 an epitaxial germanium layer 105 is disposed. The epitaxial germanium layer consists of isotopically purified germanium and comprises predominantly 70Ge isotope. In an embodiment, the epitaxial germanium layer comprises at least 97 at% 70Ge.
[0058] Since the crystal lattice and thermal expansion coefficients of the epitaxial germanium layer 105 are the same as those of the monocrystalline Ge substrate 100, the epitaxial germanium layer 105 is substantially strain free with respect to the substrate 100.
[0059] The silicon-germanium alloy layer 110 is grown epitaxially on the surface of the epitaxial germanium layer, creating a heterostructure with lattice matched layers and heterogenous interface 150 therein. A location of the conductive channel 151 for charge carriers is indicated in the germanium layer 105. The silicon-germanium alloy layer 110 is disposed on a surface of the epitaxial germanium layer 105 that faces away from the germanium substrate 100.
[0060] The SiGe alloy layer 110 is under tensile stress relative to the epitaxial germanium layer 105 and the monocrystalline germanium substrate 100, similar as described above.
[0061] By isotopically purification to 70Ge, the amount of Ge atoms with an odd number of nucleons is reduced which has the effect that in case spin-qubits are present at the interface 150 the hyperfine interaction of spin-qubits with nuclear spins of Ge and also qubit decoherence is reduced.
[0062] The epitaxial germanium layer 105 is grown by an epitaxial formation process, for example by molecular beam epitaxy, chemical vapour deposition or atomic layer deposition, each using a precursor comprising 70Ge.
[0063] The epitaxial germanium layer has a thickness between about 5 nm and about 1000 nm. The layer 105 may be adapted to have sufficient thickness for shielding qubits from hyperfine interaction with nuclear spins arising from the monocrystalline substrate. [0064] In an alternative embodiment, instead of applying an isotopically purified epitaxial germanium layer 105, a monocrystalline germanium substrate is used consisting of isotopically purified Ge, predominantly 70Ge. In an embodiment, the isotopically purified germanium layer 105 or the germanium substrate comprises at least 97 at% 70Ge.
[0065] Figure 4 schematically shows a cross-section of a semiconductor device 30 according to an embodiment.
[0066] The semiconductor device 30 according to this embodiment is similar to the semiconductor device 20 as described above with reference to figure 3. Below the differences with the semiconductor device 20 are described in detail.
[0067] According to this embodiment, on the monocrystalline germanium substrate 100 an epitaxial germanium layer 105 is disposed. The epitaxial germanium layer consists of isotopically purified germanium and comprises predominantly 70Ge isotope. In an embodiment, the epitaxial germanium layer comprises at least 97 at% 70Ge.
[0068] An isotopically purified silicon-germanium alloy layer 115 is disposed on a surface of the epitaxial germanium layer 105 that faces away from the germanium substrate 100. The isotopically purified silicon-germanium alloy layer 115 is grown epitaxially on the surface of the epitaxial germanium layer, creating an heterostructure interface 160 at said surface. A location of the conductive channel 161 for charge carriers is indicated in the epitaxial germanium layer 105. [0069] The isotopically purified silicon-germanium alloy layer 115 comprises predominantly 28Si and 70Ge isotopes, with the Si amount consisting at least 97at% 28Si, and the Ge amount consisting of at least 97at% 70Ge. By isotopical purification of the silicon-germanium alloy, the amount of Si and Ge atoms with an odd number of nucleons at the interface 160 is reduced which has the effect that in case spin-qubits are present at the interface 160 the hyperfine interaction of spin-qubits with nuclear spins of Si and/or Ge and also qubit decoherence is reduced.
[0070] The epitaxial silicon-germanium alloy layer 115 is grown by an epitaxial formation process, for example by molecular beam epitaxy, chemical vapour deposition or atomic layer deposition using a precursor(s) comprising 28Si and 70Ge.
[0071] The isotopically purified SiGe alloy has a composition SixGei.x, with the Si amount 0.05 < x < 0.60.
[0072] In an embodiment, the isotopically purified SiGe alloy has the composition Sio.zGeo.s (x=0.2).
[0073] The isotopically purified SiGe alloy layer 115 has a thickness in a range between about 5 nm and about 150 nm.
[0074] In a further embodiment the silicon-germanium alloy layer comprises a double layer consisting an isotopically purified SiGe alloy first layer, enriched in 28Si and 70Ge, and an not purified SiGe alloy second layer. Of the double layer, the isotopically purified SiGe alloy first layer is disposed between the isotopically purified germanium layer and the not purified SiGe alloy second layer. The isotopically purified germanium layer, the isotopically purified SiGe alloy first layer as well as the not purified SiGe alloy second layer are epitaxial with respect to each other and to the monocrystalline germanium substrate.
[0075] According to another embodiment, the electron and hole channels formed in the heterojunction semiconductor described above may be used to form electronic devices monolithically integrated and connected to a quantum dot device, in particular a quantum dot qubit device.
[0076] According to another embodiment, the electron and hole channels formed in the heterojunction semiconductor described above may host superconducting pairing correlation when electrically contacted (proximitized) by a parent superconductor and form hybrid superconductor-semiconductor devices. Furthermore, this proximitized channel may link qubits at a distance.
[0077] According to another embodiment, the single heterojunction device described above may be used as a base layer for solar cells. [0078] According to another embodiment, the isotopically purified 70Ge and 28Si70Ge layers may have larger thermal conductivity than non-purified Ge and SiGe layers at the operating temperature of qubits (in the order of milliKelvins), which is advantageous for their operation since heating which causes qubit decoherence is reduced by better thermal conduction in isotopically purified Ge and SiGe layers.
According to an aspect, The semiconductor device can advantageously be applied in cryo-CMOS applications.
[0079] In addition to quantum dot applications, the semiconductor device 10, 20, 30 as described above can be applied in a field effect transistor, controlled by a gate voltage applied on the gate electrode 122. For example, such field effect transistors can be configured to terahertz switching frequencies.
Also, the semiconductor device can be applied as a photovoltaic device converting solar energy into electric energy. In particular, the semiconductor device can be used in space based solar cell applications, because in comparison to silicon based photovoltaic devices, the application of germanium substrates provides an improved resistance to damage from cosmic radiation which results in a longer life-time.
[0080] Due to the strained SiGe alloy layer being an optically active medium in the proximity of the conductive channel, the semiconductor device can be used as an active optical device in optoelectronic applications.
[0081] In addition, the semiconductor device can be used in photo detector devices, and fast (high speed) diodes.
[0082] The invention has been described with reference to the preferred embodiment. Obvious modifications and alterations will occur to others upon reading and understanding the preceding detailed description. It is intended that the invention be construed as including all such modifications and alterations insofar as they come within the scope of the appended claims.

Claims

Claims
1. A method for manufacturing a semiconductor device comprising: providing a monocrystalline germanium substrate, creating a layer stack comprising a germanium layer, a silicon-germanium alloy layer and a gate layer structure on a surface of the monocrystalline germanium substrate, the creation comprising: creating the germanium layer enriched in 70Geas a surface layer on the monocrystalline germanium substrate as a monocrystalline germanium layer that is epitaxial with respect to the crystal lattice of the germanium substrate; creating on the epitaxial germanium layer the silicon-germanium alloy layer as a monocrystalline layer that is epitaxial and elastically strained under tensile stress with respect to the crystal lattice of the monocrystalline germanium substrate; creating on the silicon-germanium layer the gate layer structure; wherein a heterostructure comprising a lattice matched interface is formed between the silicon-germanium alloy layer and the epitaxial germanium layer for a conductive channel for hole carriers, the channel extending vertically in at least the epitaxial germanium layer enriched in 70Ge during exposure to an electrical potential on the gate layer structure.
2. The method according to claim 1 , wherein the epitaxial silicon-germanium alloy layer consists of isotopically purified silicon enriched in 28Si and isotopically purified germanium enriched in 70Ge.
3. A semiconductor device comprising: a layer stack comprising a monocrystalline germanium substrate, a silicon-germanium alloy layer and a gate layer structure the silicon-germanium alloy layer being disposed on the monocrystalline germanium substrate, and the gate layer structure being disposed on the silicon-germanium alloy layer, at a side of the silicon-germanium alloy layer facing away from the germanium substrate, wherein the silicon-germanium alloy layer is a monocrystalline layer and epitaxial with respect to the monocrystalline germanium substrate and is disposed on a surface layer of the monocrystalline germanium substrate consisting of a germanium layer enriched in 70Ge isotope, the germanium layer being epitaxial with respect to the crystal lattice of the germanium substrate and the epitaxial silicon-germanium alloy layer being epitaxial and elastically strained under tensile stress with respect to the crystal lattice of the epitaxial germanium layer, a heterostructure comprising a lattice matched interface present between the silicongermanium alloy layer and the epitaxial germanium layer for a conductive channel for hole carriers, the channel extending vertically in at least the epitaxial germanium layer enriched in 70Ge during exposure to an electrical potential on the gate layer structure.
4. The semiconductor device according to claim 3, wherein the epitaxial silicongermanium alloy layer consists of silicon enriched in 28Si and germanium enriched in 70Ge or a mixture of Ge isotopes with an even number of nucleons.
5. The semiconductor device according to any one of preceding claims 3 - 4, wherein the epitaxial germanium layer enriched in 70Ge comprises 70Ge and optionally one or more other Ge isotopes with an even number of nucleons.
6. The semiconductor device according to any one of claims 3 - 5, wherein the monocrystalline germanium substrate consists of germanium enriched in 70Ge comprising 70Ge and optionally one or more Ge isotopes with an even number of nucleons.
7. The semiconductor device according to any one of the preceding claims 3 - 6, wherein the germanium consists of at least 97at% 70Ge.
8. The semiconductor device according to any one of the preceding claims 3 - 7, wherein the silicon consists of at least 97at% 28Si.
9. The semiconductor device according to any one of preceding claims 3 - 8, wherein the epitaxial silicon-germanium alloy layer consists of SixGei-x alloy, with a composition selected from a range 0.05 < x < 0.60.
10. The semiconductor device according to any one of the preceding claims 3 - 9, wherein the epitaxial silicon-germanium alloy layer has a thickness between about 5 nm and about 150 nm.
11. The semiconductor device according to any one of the preceding claims 3 - 5, wherein the epitaxial germanium layer enriched in 70Ge has a thickness between about 5 nm and about 1000 nm.
12. The semiconductor device according to any one of the preceding claims 3 - 11, wherein a thin capping layer is disposed between the epitaxial silicon-germanium alloy layer and the gate layer structure.
13. The semiconductor device according to claim 12, wherein the capping layer comprises at least one selected from a silicon layer, a germanium layer, a silicon dioxide layer and a germanium oxide layer.
14. The semiconductor device according to claim 13, wherein either the silicon layer or the silicon dioxide layer comprises isotopically purified silicon enriched in 28Si, and either the germanium layer or the germanium oxide layer comprises isotopically purified germanium enriched in 70Ge.
15. The semiconductor device according to any one of the preceding claims 3 - 14, wherein the gate layer structure comprises a gate electrode layer and a dielectric layer, the dielectric layer disposed between the gate electrode layer and the epitaxial silicongermanium alloy layer.
16. A field effect transistor comprising a semiconductor device according to any one of preceding claims 3 - 15.
17. A photovoltaic device or photodetector device comprising a semiconductor device according to any one of preceding claims 3 - 15.
18. An optical device comprising a semiconductor device according to any one of preceding claims 3 - 15.
19. A diode device comprising a semiconductor device according to any one of preceding claims 3 - 15.
20. A use of the semiconductor device according to any of claims 3 - 15 as an electronic device.
21. The use according to claim 20, wherein the electronic device is an integrated electronic device.
22. The use according to claim 20, wherein the electronic device is either a diode or a transistor.
23. The use according to claim 20, wherein the electronic device is a photovoltaic cell or a photo detector.
24. The use according to claim 20, wherein the electronic device is an optical device, in particular an active optical device.
EP24718296.7A 2023-04-05 2024-04-05 Method for manufacturing a single heterojunction semiconductor device and such a single heterojunction semiconductor device Pending EP4690276A1 (en)

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NL2034508A NL2034508B1 (en) 2023-04-05 2023-04-05 Method for manufacturing a single heterojunction semiconductor device and such a single heterojunction semiconductor device.
PCT/NL2024/050178 WO2024210754A1 (en) 2023-04-05 2024-04-05 Method for manufacturing a single heterojunction semiconductor device and such a single heterojunction semiconductor device

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