EP4689829A1

EP4689829A1 - Clock domain crossing for time tracking

Info

Publication number: EP4689829A1
Application number: EP24722455.3A
Authority: EP
Inventors: Sanjay deep SANJEEV; Venkateswaran Ananthanarayanan
Original assignee: Google LLC
Current assignee: Google LLC
Priority date: 2023-12-21
Filing date: 2024-04-17
Publication date: 2026-02-11
Also published as: WO2025136397A1; WO2025136435A1

Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing clock domain crossing for time tracking. One of the systems includes first circuitry of a first clock domain having a reference clock and second circuitry of a second clock domain having a core clock, with the first circuitry configured to receive an input signal in the first clock domain and to generate a plurality of toggle signals that cross into the second clock domain. The system includes a plurality of clock-domain crossing modules in the second clock domain configured to respectively receive the toggle signals crossing into the second clock domain. The system includes convergence logic configured to combine the toggle signals received in the second clock domain to output a synchronized output signal, as synchronized with the core clock, within the second clock domain that represents the input signal.

Description

CLOCK DOMAIN CROSSING FOR TIME TRACKING

BACKGROUND

This specification relates to clock domain crossing, and more particularly to systems and devices for time tracking.

Electronic devices rely on clock signals to synchronize the operations of different device components. An electronic device can govern multiple components with the same clock signal by synchronizing the operations of the components to the cycles of the clock signal. The collection of device components synchronized by the same clock signal forms a clock domain. When components are synchronized by different clock signals, a signal relayed from one clock domain may not be appropriately received by the components of another clock domain because operations in the two clock domains are not synchronized between the two clock domains. Clock domain crossing techniques are used to appropriately relay signals between components in different clock domains.

Often, the time as measured in one clock domain needs to be relayed to the components of another clock domain. For example, the proper synchronization of the computations performed by two circuits may depend on the circuits being able to relay the current times according to the clocks of the circuits. Time tracking techniques seek to allow the components of a first clock domain to appropriately relay the current time, as determined by the clock in the first clock domain, to the components of a second clock domain.

SUMMARY

This specification describes how a system can perform clock domain crossing to relay a signal from a first clock domain, having a reference clock, into a second clock domain, having a core clock with a different frequency than the reference clock. The signal relayed by the system can characterize the passage of time according to the reference clock.

In general, the system can perform clock domain tracking utilizing two circuits: (i) a first circuitry in the first clock domain and (ii) a second circuitry in the second clock domain. The first circuitry is configured to receive an input signal in the first clock domain and to generate a plurality of toggle signals that cross into the second clock domain. The second circuitry includes a plurality of clock-domain crossing modules in the second clock domain configured to respectively receive the toggle signals crossing into the second clock domain. The second circuitry also includes convergence logic configured to combine the toggle signals received in the second clock domain to propagate the input signal, as synchronized with the core clock, within the second clock domain.

Particular embodiments of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages.

By utilizing a novel converging toggle technique that can track and compensate for missed cycles of the relayed signal, the described systems utilize a simpler and more efficient (e.g., in terms of the number of required components, the power usage, the chipspace required, etc.) method for accurate time tracking than conventional techniques. In particular, the described systems avoid using less efficient (e.g., in terms of the number of required components, the power usage, the chip-space required, etc.) CDC checks or signal encoding, as required by conventional techniques. Additionally, the described systems can be used in applications with any clock frequencies for the clock domains. In particular, implementations of the described systems can perform time tracking for reference clocks having any frequency relative to corresponding core clocks (including all reference clock frequencies greater than the corresponding core clocks) utilizing simpler and more efficient circuitry than conventional systems. Therefore, the described systems provide a simple, accurate, and efficient method for time-tracking as compared to conventional techniques.

The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an example clock domain crossing system.

FIG. 2 is a flow diagram of an example process for clock domain crossing.

FIG. 3 shows an example two-toggle circuit in the first clock domain.

FIG. 4 shows an example circuit in the second clock domain.

FIG. 5 is an illustration of the operation of an example two-toggle clock domain crossing system.

FIG. 6 shows an example multi-toggle circuit in the first clock domain. FIG. 7 is an illustration of the operation of an example multi-toggle clock domain crossing system.

Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

FIG. 1 shows an example clock domain crossing system 100,

The clock domain crossing system 100 is configured to receive an input signal 102 in a reference clock domain 104 and output a synchronized output signal 106 in a core clock domain 108 that represents the input signal 102.

A reference clock signal 113 synchronizes signals and devices in the reference clock domain 104. A core clock signal 115 synchronizes signals and devices in the core clock domain 108.

The reference clock signal 113 and the core clock signal 115 characterize the cycles of respective reference and core clocks. For example, the reference clock signal 113 and the core clock signal 115 can be binary pulses output by the respective reference and core clocks for each cycle of the clocks. Throughout this specification, a cycle of one of the clock signals is used interchangeably to refer to a cycle of one of the clocks.

The reference clock signal 113 and the core clock signal 115 synchronize signals and devices based on the cycling of the respective clocks. A signal synchronized by a particular clock signal forms a time sequence of discrete values where each value is transmitted during a corresponding cycle of the particular clock signal, e.g., each value can be transmitted at a rising, or falling, edge of the clock signal. When a device is synchronized by a particular clock signal receives a signal, the device receives a single value of the received signal during each cycle of the particular clock signal, e.g., by receiving the value at a rising, or falling, edge of the clock signal. When a device is synchronized by a particular clock signal outputs a signal, the device outputs a single value of the output signal during each cycle of the particular clock signal, e.g., by outputting the value at a rising, or falling, edge of the clock signal.

The input signal 102 is a binary signal synchronized by the reference clock signal. The synchronized output signal 106 can be a binary signal synchronized by the core clock signal. The synchronized output signal 106 can represent the input signal 102 in any of a variety of ways. For example, the synchronized output signal 106 can be a binary signal that reconstructs the input signal 102 in the core clock domain 108, with the binary values of the synchronized output signal 106 each corresponding to a binary value of the input signal 102. As another example, the synchronized output signal 106 can be a multi -bit binary signal, with the binary values of the synchronized output signal 106 encoding information from the input signal 102. In general, at each cycle of the core clock, the binary values of the synchronized output signal 106 represent the input signal 102 by encoding information received from the input signal 102 during a cycle of the core clock. For example, at a given cycle of the core clock, the binary values of the synchronized output signal 106 can encode a number of binary pulses from the input signal 102 received during the previous cycle of the core clock.

To produce the synchronized output signal 106, the system 100 generates multiple toggle signals 110-A through 110-N that cross between the reference clock domain 104 and the core clock domain 108. The toggle signals 110-A through 110-N can be binary signals.

The system 100 includes a toggle generator system 112 synchronized by the reference clock. The toggle generator system 112 can receive the input signal 102 in the reference clock domain 104 and produce the toggle signals 110-A through 110-N. In general, the toggle generator system 112 can generate the toggle signals 110- A through 110-N such that exactly one of the toggle signals 110-A through 110-N changes state at each cycle of the reference clock. For example, the toggle generator system 112 can generate the toggle signals 110-A through 110-N by performing frequency division of the input signal 102.

In some implementations, the toggle generator system 112 can generate each of the toggle signals 110- A through 110-N by performing frequency division of the input signal 102 at a distinct time offset for the toggle signal. As a particular example, the toggle generator system 112 can generate N toggle signals 110-A through 110-N by performing a 2N frequency division of the input signal 102, with the toggle signals offset from each other by one cycle of the reference clock. In some implementations, the toggle generator system 112 can generate two toggle signals, where the two toggle signals are generated by performing frequency division of the input signal 102 to a quarter of the frequency of the reference clock, with the two toggle signals offset by a single cycle of the reference clock.

The system 100 includes a clock domain crossing structure 114 in the core clock domain 108. The clock domain crossing (CDC) structure 114 can receive and propagate the toggle signals 110- A through 110-N into the core clock domain 108. In particular, the CDC structure 114 can convert the toggle signals 110- A through 110-N from the reference clock domain 104 to the core clock domain 108 by outputting corresponding signals synchronized to the core clock of the core clock domain 108.

The CDC structure 114 includes multiple CDC modules 116- A through 116-N synchronized by the core clock signal 115. Each of the CDC modules 116- A through 116-N can receive a respective one of the toggle signals 110-A through 110-N and can output signals characterizing the respective toggle signal into the core clock domain 108.

The system 100 includes a convergence logic system 118 in the core clock domain 108. The convergence logic system 118 can produce the appropriately synchronized output signal 106 based on the signals output from the CDC modules 116- A through 116- N.

In some implementations, the convergence logic system 118 can use the signals output from the CDC modules 116- A through 116-N to detect the number of toggle signals 110-A through 110-N received in the core clock domain 108 that change state during a single cycle of the core clock. By detecting the number of toggle signals 110-A through 110-N that change state at each cycle of the core clock, the system 100 can automatically correct for errors caused by missed changes in the toggle signals 110-A through 110-N. During the operation of the system 100, misalignments between the reference and core clocks can cause the system to detect a change in one or more of the toggle signals 110-A through 110-N in the core clock domain 108 at a later core clock cycle. In general, at each cycle of the core clock, the convergence logic system 118 can generate the synchronized output signal 106 based on the number of toggle signals 110-A through 110-N that change state during the cycle to compensate for missed toggle signals.

When the frequency of the core clock is greater than the frequency of the reference clock, the convergence logic system 118 can use a pending toggle count to compensate for missed toggle signals 110-A through 110-N. If the convergence logic system 118 detects multiple toggle signals changing state during a particular cycle of the core clock, the system 118 can increase the pending toggle count and output an active value (e.g., a 1) as the value for the synchronized output signal 106 for the particular cycle of the core clock. In particular, if the system 118 has a non-zero pending toggle count and detects that all toggle signals are inactive for a cycle of the clock count, the system 118 can decrement the pending toggle count and output an active value (e.g., a 1) as the value for the synchronized output signal 106 for the particular cycle of the core clock.

For all relative frequencies of the core clock and the reference clock, and particularly when the frequency of the core clock is greater than one and a half times the frequency of the reference clock divided by the number of toggle signals, the convergence logic system 118 can generate the synchronized output signal 106 as a multi-bit signal that represents how many toggle signals 110- A through 110-N are detected changing state at each cycle of the core clock. As an example, the convergence logic system 118 can generate the synchronized output signal 106 to specify which toggle signals 110-A through 110-N change state at each cycle of the core clock. As another example, the convergence logic system 118 can generate the synchronized output signal 106 to specify the number of toggle signals 110-A through 110-N change state at each cycle of the core clock.

In some implementations, the system 100 can include a counter configured to increment a time value within the core clock domain 108 based on the value of the synchronized output signal 106. As an example, the counter can increment the time value by one when triggered by active values of the synchronized output signal 106. As another example, the counter can increment the time value by the number of toggle signals 110-A through 110-N detected changing state at each cycle of the core clock specified by the synchronized output signal 106.

In some implementations, the input signal 102 can be the reference clock signal 113. When the input signal 102 is the reference clock signal 113, the synchronized output signal 106 is a signal in the core clock domain 108 that represents the cycling of the reference clock in the reference clock domain 104. When the input signal 102 is the reference clock signal 113 and the system 100 includes the counter incrementing the time value in the core clock domain 108, the incremented time value in the core clock domain 108 can track the passage of time according to the reference clock.

FIG. 2 is a flow diagram of an example process 200 for implementing clock domain crossing. A clock domain crossing system, such as the clock domain crossing system 100 of FIG. 1, appropriately configured in accordance with this specification, can perform the process 200.

The system receives an input signal in a reference clock domain synchronized by a reference clock signal (step 202). The input signal is a binary signal. In some implementations, the input signal can be the reference clock signal. The system generates multiple toggle signals in the reference clock domain based on the received input signal (step 204). In particular, the system generates the toggle signals based on the received input signal such that exactly one toggle signal changes state during each cycle of the reference clock. For example, the system can perform frequency division of the received input signal to generate signal values of the toggle signals for the current cycle of the reference clock.

In some implementations, the system can generate each of the toggle signals by performing frequency division of the input signal at a distinct time offset. For example, the system can produce N toggle signals by performing a 2N frequency division of the input signal, with the toggle signals offset from each other by one cycle of the reference clock. As another example, in some implementations, the system can produce two alternating toggle signals by performing frequency division of the input signal to a quarter the frequency of the reference clock, with the sampling for the two toggle signals being offset by a single cycle of the reference clock.

The system relays the generated toggle signals into a core clock domain synchronized by a core clock (step 206). In particular, the system relays the current signal value for each toggle signal at each cycle of the core clock.

The system outputs a synchronized output signal in the core clock domain by combining the toggle signals relayed into the core clock domain (step 208). In particular, at each cycle of the core clock, the system outputs values for the synchronized output signal based on the toggle signal values relayed at the current core clock cycle.

The system can detect when multiple toggle signals change state during a core clock cycle.

In some implementations, at each core clock cycle when the system detects multiple toggle signals changing state, the system can increment a pending toggle count and output an active value for the synchronized output signal. At a core clock cycle when the system detects no toggle signals changing state and when the system has a non-zero pending toggle count, the system can decrement the pending toggle count and output an active value for the synchronized output signal.

In some implementations, at each core clock cycle when the system detects multiple toggle signals changing state, the system can output a multi-bit value for the synchronized output signal that represents how many toggle signals are detected changing state during the cunent core clock cycle. For example, the system can output the value for the synchronized output signal that specifies which toggle signals are changing state during the current core clock cycle. As another example, the system can output the value for the synchronized output signal that specifies the number of toggle signals changing state curing the current core clock cycle.

In some implementations, the system can increment a time value within the core clock domain based on the value of the synchronized output signal. As an example, the system can increment the time value by one when the system outputs active values of the synchronized output signal. As another example, the system can increment the time value by a number specified by the value of the synchronized output signal. As a particular example, the system can increment the time value by the number of toggle signals changing state during the current core clock cycle, as specified by the value of the synchronized output signal.

FIG. 3 shows an example circuit 300 for an example toggle generator 112 in the reference clock domain 104 that generates two toggle signals.

The example circuit 300 includes a frequency divider circuit 302 and a flip flop circuit 304. The frequency divider circuit 302 can receive the reference clock signal 113 as an input signal. The frequency divider circuit 302 can produce the toggle signal 306. The circuit 300 uses the toggle signal 306 as the input signal for the flip flop circuit 304, which can produce the toggle signal 308.

The frequency divider circuit 302 can generate the toggle signal 306 that alternates between an active and inactive value as determined by frequency division of the reference clock signal 113 to a frequency lower than that of the reference clock. The flip flop circuit 304 can generate the toggle signal 308 that is a delay ed or phase shifted version of the toggle signal 306.

In some implementations, the toggle signals 306 and 308 can alternate at a quarter of the frequency of the reference clock signal 113 and can be separated by a phase offset of 90 degrees, i.e., be offset by one cycle of the reference clock signal from one another. Further details regarding the operation of the circuit 300 are described below in reference to FIG. 5.

FIG. 4 shows an example circuit 400 in the core clock domain 108. The components of the circuit 400 are synchronized to the core clock.

The circuit 400 includes synchronizer circuits 402 and 404 that can receive the toggle signals 306 and 308, respectively, as generated, for example, by the circuit 300. The synchronizer circuits 402 and 404 can output signals corresponding to the toggle signals 306 and 308 that alternate between an active and inactive value as synchronized with the core clock. The synchronizer circuits 402 and 404 can have any appropriate architecture for synchronizing a received binary signal with the core clock. For example, the synchronizer circuits 402 and 404 can be a 2 flip-flop synchronizer that processes the received signal using 2 flip-flop circuits. As another example, the synchronizer circuits 402 and 404 can be an M flip-flop synchronizer that processes the received signal using M flip-flop circuits, with M > 1.

The circuit 400 includes toggle detector circuits 406 and 408 that can receive the output signals from the synchronizer circuits 402 and 404 respectively. The toggle detector circuit 406 can output an active signal value for a cycle of the core clock in which synchronizer circuit 402 output changes value. The toggle detector circuit 408 can output an active signal value for a cycle of the core clock in which synchronizer circuit 404 output changes value.

The circuit 400 includes the convergence logic circuit 118. The convergence logic circuit 118 can receive the outputs from the toggle detector circuits 406 and 408 and can, at each cycle of the core clock, output an appropriate signal value for a synchronized output signal 106 that is synchronized to the core clock. In particular, the convergence logic circuit 118 can output signal values for the synchronized output signal 106 based on the number of toggles detected changing state during each cycle of the core clock.

In some implementations, convergence logic circuit 118 can store the pending toggle count. At each cycle of the core clock in which the convergence logic circuit 118 receives only one active signal from the toggle detectors 406 and 408, the convergence logic circuit 118 can output an active value for the synchronized output signal 106 without changing the pending toggle count. At each cycle of the core clock in which the convergence logic circuit 118 receives two active signals from the toggle detectors 406 and 408, the convergence logic circuit 118 can output an active value for the synchronized output signal 106 and increment the pending toggle count by one. When the pending toggle count is non-zero and the convergence logic circuit 118 receives no active signals from the toggle detectors 406 and 408, the convergence logic circuit 118 can output an active value for the synchronized output signal 106 and can decrement the pending toggle count by one. Otherw ise, at each cycle of the core clock in which the convergence logic circuit 118 receives no active signals from the toggle detectors 406 and 408, the convergence logic circuit 118 can output an inactive value for the synchronized output signal 106 without changing the pending toggle count. In some implementations, the convergence logic circuit 118 can output multi-bit signal values for the synchronized output signal 106 that specify the number of active signals received from the toggle detectors 406 and 408. For example, the convergence logic circuit 118 can output a 2-bit value for the synchronized output signal 106 that specifies, at each cycle of the core clock, whether the circuit 118 receives 0, 1, or 2 active signals from the toggle detectors 406 and 408.

The circuit 400 can include a counter 412 that tracks a time 414 according to the reference clock within the core clock domain 108. In particular, at each cycle of the core clock, the counter 412 can increment the time 414 based on the value of the synchronized output signal 106 for the cycle. For example, at each cycle of the core clock in which the counter 412 receives an active signal value from the synchronized output signal 106, the counter 412 can increment the time 414 by one. As another example, at each cycle of the core clock, the counter 412 can increment the time 414 by a number specified by the synchronized output signal 106 for the cycle.

Further details regarding the operation of the circuit 400 are described below in reference to FIG. 5 and FIG. 7.

FIG. 5 illustrates the operation of an example clock domain crossing system, e.g., the clock domain crossing system 100, using two toggle signals.

The system receives the reference clock signal 113 as an input signal in the reference clock domain 104. The cycles of the reference clock define a reference clock time 502 in the reference clock domain 104 that increments at every cycle of the reference clock signal 113.

The system can process the reference clock signal 113 to produce the toggle signals 306 and 308, which are synchronized by the reference clock signal 113. As an example, the system can produce the toggle signals 306 and 308 using the components of the circuit 300.

As illustrated, the toggle signals 306 and 308 can cycle at a frequency a quarter of that of the reference clock signal 113. As illustrated, the toggle signals 306 and 308 can be offset from one another by a phase of 90 degrees, i.e., be offset from one another by one cycle of the reference clock signal 113.

The system can process the toggle signals 306 and 308 to produce the time 414 within the core clock domain 108 that tracks the reference clock time 502. As an example, the system can process the toggle signals 306 and 308 to produce the time 414 using the components of the circuit 400. The system components within the core clock domain 108 are synchronized by the core clock signal 115.

In general, due to misalignments between the reference and core clocks, the signals within the core clock domain 108 can be offset from and have different frequencies from signals within the reference clock domain 104. For illustrative purposes, the core clock is depicted in FIG. 5 as having the same frequency as and being in phase with the reference clock. The signals within the core clock domain 108 are depicted in FIG. 5 as having a propagation delay of one core clock cycle from corresponding signals in the reference clock domain 104.

The system receives the toggle signals 306 and 308 and produces corresponding synchronizer signals 402 and 404 as synchronized with the core clock signal 115. The system can track when a toggle is detected, e.g., with a toggle detected signal 504, and can track the number of toggles detected 506 within each core clock cycle. The system can produce a synchronized output signal (e.g., the synchronized output signal 106 of FIG. 1) based on the number of toggles detected 506. In some implementations, the system includes a counter that tracks a time value within the core clock domain 108.

In some implementations, the system can output the number of toggles detected 506 as the value of the synchronized output signal 106 and can increment the time value within the core clock domain 108 by the number of toggles detected 506.

In some implementations, the system can track a pending toggle count using a toggle pending signal 508 that indicates when the pending toggle count is one. The system can increment the tracked time 414 in the core clock domain 108 based on the toggle pending signal 508 and the number of toggles detected 506. The tracked time 414 depicted in FIG. 5 is illustrated as having been produced based on the toggle pending signal 508 and the number of toggles detected 506.

When the system detects one or more toggles signals in a core clock cycle, the system can increment the tracked time 414 by one. When the system detects no toggle signals in a core clock cycle when the toggle pending signal 508 is active, the system can deactivate the toggle pending signal 508 and increment the tracked time 414 by one.

Misalignments between the reference and core clocks can cause the system to detect a toggle signal in the core clock domain 108 at a later core clock cycle. For example, the miss 510 illustrates a change in the toggle signal 306 being detected by the synchronizer 402 one core clock cycle later. At the core clock cycle when the miss 510 occurs, the system detects no toggle signals. Because the pending toggle count is zero, the system does not increment the time 414 when the miss 510 occurs. However, the missed transition of the toggle signal 306 is detected at a later core clock cycle, in which two toggle signals are detected, resulting in the pending toggle count being incremented by one.

The miss 512 illustrates a later change in the toggle signal 308 being detected by the synchronizer 404 one core clock cycle later. At the core clock cycle when the miss 512 occurs, the system detects no toggle signals. Because the pending toggle count is now one, the system does increment the time 414 when the miss 510 occurs, resulting in the compensated time increment 514.

Following the procedures described above, the system can track the time 414 while compensating for missed signals transferred between the reference clock domain 104 and the core clock domain 108. As illustrated, the system can track the time 414 to an accuracy within one cycle of the reference clock.

FIG. 6 shows an example circuit 600 for an example toggle generator 112 in the reference clock domain 104 that generates multiple toggle signals. In particular, the example circuit 600 can generate the N toggle signals 110- A through 110-N.

The example circuit 600 includes a frequency divider circuit 602 and N - 1 flip flop circuits 604-B through 604-N. The frequency divider circuit 602 can receive the reference clock signal 113 as an input signal. The frequency divider circuit 602 can produce the toggle signal 110- A. The circuit 600 generates each of the toggle signals 110-B through 110-N using a corresponding one of the flip-flop circuits 604-B through 604-N. In particular, the flip-flop circuits 604-B through 604-N generate the toggle signals 110-B through 110-N by using the preceding toggle signal as an input. For example, the flip-flop circuit 604-B receives toggle signal 110-A as an input and produces the toggle signal 110-B as an output.

The frequency divider circuit 602 can generate the toggle signal 110-A that alternates between an active and inactive value as determined by frequency division of the reference clock signal 113 by a factor of 2N. Each of the flip-flop circuits 604-B through 604-N can generate a toggle signal output that is phase shifted by an offset of one reference clock cycle from the toggle signal input for the flip-flop circuit. Further details regarding the operation of the circuit 600 are described below in reference to FIG. 7. FIG. 7 illustrates the operation of an example multi-toggle clock domain crossing system, e.g., the clock domain crossing system 100. In particular, FIG. 7 illustrates the operation of an example clock domain crossing signal using three toggle signals.

The system receives the reference clock signal 113 as an input signal in the reference clock domain 104. The cycles of the reference clock define a reference clock time 702 in the reference clock domain 104 that increments at every cycle of the reference clock signal 113.

The system can process the reference clock signal 113 to produce the three toggle signals 110- A, 110-B, and 110-C, which are synchronized by the reference clock signal 113. As illustrated, the toggle signals 110-A, 110-B, and 110-C can cycle at a frequency a sixth of that of the reference clock signal 113. As illustrated, the toggle signals 110-A, 110-B, and 110-C can be offset from one another by one cycle of the reference clock signal 113. As an example, the system can generate the toggle signals 110-A, 110-B, and 110-C using the components of the circuit 600.

The system can process the toggle signals 110-A, 110-B, and 110-C to produce the time 414 within the core clock domain 108 that tracks the reference clock time 502.

The system components within the core clock domain 108 are synchronized by the core clock signal 115.

In general, due to misalignments between the reference and core clocks, the signals within the core clock domain 108 can be offset from and have different frequencies from signals within the reference clock domain 104. For illustrative purposes, the core clock is depicted in FIG. 7 as having half the frequency of and being in phase with the reference clock. The signals within the core clock domain 108 are depicted in FIG. 7 as having a propagation delay of one core clock cycle from corresponding signals in the reference clock domain 104.

The system receives the toggle signals 110-A, 110-B, and 110-C in the core clock domain 108, resulting in the received toggles 704- A, 704-B, and 704-C as synchronized with the core clock signal 115. The system can track the number of toggles detected 506 within each core clock cycle. The system can produce a synchronized output signal (e.g., the synchronized output signal 106 of FIG. 1) based on the number of toggles detected 708. In some implementations, the system includes a counter that tracks a time value within the core clock domain 108. In some implementations, the system can output the number of toggles detected 708 as the value of the synchronized output signal 106 and can increment the time value within the core clock domain 108 by the number of toggles detected 708.

Following the procedures described above, the system can track the time 414 while compensating for missed signals transferred between the reference clock domain 104 and the core clock domain 108.

Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of, data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. Alternatively or in addition, the program instructions can be encoded on an artificially-generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus.

The term “data processing apparatus” refers to data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can also be, or further include, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). The apparatus can optionally include, in addition to hardware, code that creates an execution environment for computer programs, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

A computer program which may also be referred to or described as a program, software, a software application, an app, a module, a software module, a script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e g., files that store one or more modules, sub-programs, or portions of code. A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a data communication network.

For a system of one or more computers to be configured to perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. For one or more computer programs to be configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by data processing apparatus, cause the apparatus to perform the operations or actions.

As used in this specification, an “engine,” or “software engine,” refers to a software implemented input/output system that provides an output that is different from the input. An engine can be an encoded block of functionality, such as a library, a platform, a software development kit (“SDK”), or an object. Each engine can be implemented on any appropriate type of computing device, e.g., servers, mobile phones, tablet computers, notebook computers, music players, e-book readers, laptop or desktop computers, PDAs, smart phones, or other stationary or portable devices, that includes one or more processors and computer readable media. Additionally, two or more of the engines may be implemented on the same computing device, or on different computing devices.

The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuitry, e.g., an FPGA or an ASIC, or by a combination of special purpose logic circuitry and one or more programmed computers.

Computers suitable for the execution of a computer program can be based on general or special purpose microprocessors or both, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read-only memory or a random access memory or both. The essential elements of a computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and data. The central processing unit and the memory can be supplemented by, or incorporated in, special purpose logic circuitry. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device, e.g., a universal serial bus (USB) flash drive, to name just a few.

Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

To provide for interaction with a user, embodiments of the subject matter described in this specification can be implemented on a computer having a display device, e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, for displaying information to the user and a keyboard and pointing device, e.g, a mouse, trackball, or a presence sensitive display or other surface by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input. In addition, a computer can interact with a user by sending documents to and receiving documents from a device that is used by the user; for example, by sending web pages to a web browser on a user's device in response to requests received from the web browser. Also, a computer can interact with a user by sending text messages or other forms of message to a personal device, e.g., a smartphone, running a messaging application, and receiving responsive messages from the user in return.

Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface, a web browser, or an app through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN) and a wide area network (WAN), e.g., the Internet.

The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. In some embodiments, a server transmits data, e.g., an HTML page, to a user device, e.g., for purposes of displaying data to and receiving user input from a user interacting with the device, which acts as a client. Data generated at the user device, e.g., a result of the user interaction, can be received at the server from the device.

In addition to the embodiments described above, the following embodiments are also innovative:

Embodiment 1 is a system comprising: first circuitry of a first clock domain having a reference clock; second circuitry of a second clock domain having a core clock, wherein the first circuitry is configured to receive an input signal in the first clock domain and to generate a plurality of toggle signals that cross into the second clock domain; a plurality of clock-domain crossing modules in the second clock domain configured to respectively receive the toggle signals crossing into the second clock domain; and convergence logic configured to combine the toggle signals received in the second clock domain to output a synchronized output signal, as synchronized with the core clock, within the second clock domain that represents the input signal.

Embodiment 2 is the system of embodiment 1, further comprising a counter configured to increment a time value within the second clock domain when triggered by the synchronized output signal. Embodiment 3 is the system of embodiment 1, further comprising a counter configured to increment a time value within the second clock domain by an amount based on the synchronized output signal.

Embodiment 4 is the system of any one of embodiments 1-3, wherein the input signal is a clock signal from the reference clock.

Embodiment 5 is the system of any one of embodiments 1-4, wherein the convergence logic is configured to detect the number of toggle signals changing state during a single cycle of the core clock.

Embodiment 6 is the system of embodiment 5, wherein the convergence logic is operable to support all core clock frequency ranges greater than or equal to the frequency of the reference clock.

Embodiment 7 is the system of embodiment 5 or embodiment 6, wherein the core clock has a frequency greater than or equal to the frequency of the reference clock.

Embodiment 8 is the system of embodiment 5, wherein the convergence logic is operable to support all core clock frequency ranges greater than or equal to one and a half times the frequency of the reference clock divided by the number of toggle signals.

Embodiment 9 is the system of embodiment 5 or embodiment 8, wherein the core clock has a frequency greater than or equal to one and a half times the frequency of the reference clock divided by the number of toggle signals.

Embodiment 10 is the system of any one of embodiments 5-7, wherein whenever multiple toggle signals change state during a given single cycle of the core clock, the convergence logic is configured to transmit an active synchronized output signal for the given cycle of the core clock and to increase a pending toggle count for a future idle cycle.

Embodiment 11 is the system of embodiment 10, wherein whenever no toggle signals change state during a given single cycle of the core clock and the pending toggle count is greater than zero, the convergence logic is configured to decrement the pending toggle count and transmit an active synchronized output signal for the given cycle of the core clock.

Embodiment 12 is the system of any one of embodiments 1-11, wherein the convergence logic is configured to increment, at each cycle of the core clock, the time value for the core clock by a number less than or equal to the number of toggle signals that change state during the cycle of the core clock. Embodiment 13 is the system of embodiment 12, wherein the convergence logic is configured to increment, at each cycle of the core clock, the time value for the core clock by the number of toggle signals that change state during the cycle of the core clock.

Embodiment 14 is the system of any one of embodiments 1-13, wherein each of the toggle signals is generated by performing frequency division of the input signal.

Embodiment 15 is the system of any one of embodiments 1-14, wherein toggle signals are generated by performing frequency division of the input signal at different time offsets.

Embodiment 16 is the system of any one of embodiments 1-15, wherein the first circuitry is configured to generate a plurality toggle signals that cross into the second clock domain, the toggle signals being generated by frequency division of the input signal to the frequency of the reference clock divided by twice the number of toggle signals with a time offset of one reference clock cycle between the generated toggle signals.

Embodiment 17 is a method, comprising: receiving, by a first circuitry of a first clock domain that has a reference clock, an input signal in the first clock domain; generating, by the first circuitry, a plurality of toggle signals that cross into a second clock domain that has a core clock; receiving, by a plurality of clock-domain crossing modules in the second clock domain, the toggle signals crossing into the second clock domain; combining, by convergence logic in the second clock domain, the toggle signals received in the second clock domain; and outputting, by the convergence logic, a synchronized output signal, as synchronized with the core clock, within the second clock domain that represents the input signal.

Embodiment 18 is the method of embodiment 17, further comprising: incrementing, by a counter in the second clock domain, a time value within the second clock domain when the counter is triggered by the synchronized output signal.

Embodiment 19 is the method of embodiment 17, further comprising: incrementing, by a counter in the second clock domain, a time value within the second clock domain by an amount based on the synchronized output signal.

Embodiment 20 is the method of any one of embodiments 17-19, wherein the input signal is a clock signal from the reference clock. Embodiment 21 is the method of any one of embodiments 17-20, further comprising: detecting, by the convergence logic, the number of toggle signals changing state during a single cycle of the core clock.

Embodiment 22 is the method of embodiment 21, wherein the convergence logic is operable to support all core clock frequency ranges greater than or equal to the frequency of the reference clock.

Embodiment 23 is the method of embodiment 21 or embodiment 22, wherein the core clock has a frequency greater than or equal to the frequency of the reference clock.

Embodiment 24 is the method of embodiment 21, wherein the convergence logic is operable to support all core clock frequency ranges greater than or equal to one and a half times the frequency of the reference clock divided by the number of toggle signals.

Embodiment 25 is the method of embodiment 21 or embodiment 24, wherein the core clock has a frequency greater than or equal to one and a half times the frequency of the reference clock divided by the number of toggle signals.

Embodiment 26 is the method of any one of embodiments 21-23, further comprising, whenever multiple toggle signals change state during a given single cycle of the core clock: transmitting, by the convergence logic, an active synchronized output signal for the given cycle of the core clock; and increasing, by the convergence logic, a pending toggle count for a future idle cycle.

Embodiment 27 is the method of embodiment 26, further comprising, whenever no toggle signals change state during a given single cycle of the core clock and the pending toggle count is greater than zero: decrementing, by the convergence logic, the pending toggle count; and transmitting, by the convergence logic, an active synchronized output signal for the given cycle of the core clock.

Embodiment 28 is the method of any one of embodiments 17-27, further comprising: incrementing, by the convergence logic, at each cycle of the core clock, the time value for the core clock by a number less than or equal to the number of toggle signals that change state during the cycle of the core clock.

Embodiment 29 is the method of embodiment 28, further comprising: incrementing, by the convergence logic, at each cycle of the core clock, the time value for the core clock by the number of toggle signals that change state during the cycle of the core clock.

Embodiment 30 is the method of any one of embodiments 17-29, wherein generating the plurality of toggle signals further comprises: generating each of the toggle signals by performing frequency division of the input signal.

Embodiment 31 is the method of any one of embodiments 17-30, wherein generating the plurality of toggle signals further comprises: generating each of the toggle signals by performing frequency division of the input signal at different time offsets.

Embodiment 32 is the method of any one of embodiments 17-31, wherein generating the plurality of toggle signals further comprises: generating, by the first circuitry, a plurality of toggle signals that cross into the second clock domain by performing frequency division of the input signal to the frequency of the reference clock divided by twice the number of toggle signals with a time offset of one reference clock cycle between the generated toggle signals.

Embodiment 33 is a computer storage medium encoded with instructions that are operable, when executed by data processing apparatus, to cause the data processing apparatus to perform operations comprising the method of any one of embodiments 17- 32.

While this specification contains many specific implementation details, these should not be constmed as limitations on the scope of any invention or on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially be claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

What is claimed is:

Claims

1. A system comprising: first circuitry of a first clock domain having a reference clock; second circuitry of a second clock domain having a core clock, wherein the first circuitry is configured to receive an input signal in the first clock domain and to generate a plurality of toggle signals that cross into the second clock domain; a plurality of clock-domain crossing modules in the second clock domain configured to respectively receive the toggle signals crossing into the second clock domain; and convergence logic configured to combine the toggle signals received in the second clock domain to output a synchronized output signal, as synchronized with the core clock, within the second clock domain that represents the input signal.

2. The system of claim 1, further comprising a counter configured to increment a time value within the second clock domain when triggered by the synchronized output signal.

3. The system of claim 1, further comprising a counter configured to increment a time value within the second clock domain by an amount based on the synchronized output signal.

4. The system of any previous claim, wherein the input signal is a clock signal from the reference clock.

5. The system of any previous claim, wherein the convergence logic is configured to detect the number of toggle signals changing state during a single cycle of the core clock.

6. The system of claim 5, wherein the convergence logic is operable to support all core clock frequency ranges greater than or equal to the frequency of the reference clock.

7. The system of claim 5 or claim 6, wherein the core clock has a frequency greater than or equal to the frequency of the reference clock.

8. The system of claim 5, wherein the convergence logic is operable to support all core clock frequency ranges greater than or equal to one and a half times the frequency of the reference clock divided by the number of toggle signals.

9. The system of claim 5 or claim 8, wherein the core clock has a frequency greater than or equal to one and a half times the frequency of the reference clock divided by the number of toggle signals.

10. The system of any one of claims 5-7, wherein whenever multiple toggle signals change state during a given single cycle of the core clock, the convergence logic is configured to transmit an active synchronized output signal for the given cycle of the core clock and to increase a pending toggle count for a future idle cycle.

11. The system of claim 10, wherein whenever no toggle signals change state during a given single cycle of the core clock and the pending toggle count is greater than zero, the convergence logic is configured to decrement the pending toggle count and transmit an active synchronized output signal for the given cycle of the core clock.

12. The system of any previous claim, wherein the convergence logic is configured to increment, at each cycle of the core clock, the time value for the core clock by a number less than or equal to the number of toggle signals that change state during the cycle of the core clock.

13. The system of claim 12, wherein the convergence logic is configured to increment, at each cycle of the core clock, the time value for the core clock by the number of toggle signals that change state during the cycle of the core clock.

14. The system of any previous claim, wherein each of the toggle signals is generated by performing frequency division of the input signal.

15. The system of any previous claim, wherein toggle signals are generated by performing frequency division of the input signal at different time offsets.

16. The system of any previous claim, wherein the first circuitry is configured to generate a plurality toggle signals that cross into the second clock domain, the toggle signals being generated by frequency division of the input signal to the frequency of the reference clock divided by twice the number of toggle signals with a time offset of one reference clock cycle between the generated toggle signals.

17. A method, comprising: receiving, by a first circuitry of a first clock domain that has a reference clock, an input signal in the first clock domain; generating, by the first circuitry, a plurality of toggle signals that cross into a second clock domain that has a core clock; receiving, by a plurality of clock-domain crossing modules in the second clock domain, the toggle signals crossing into the second clock domain; combining, by convergence logic in the second clock domain, the toggle signals received in the second clock domain; and outputting, by the convergence logic, a synchronized output signal, as synchronized with the core clock, within the second clock domain that represents the input signal.

18. The method of claim 17, further comprising: incrementing, by a counter in the second clock domain, a time value within the second clock domain when the counter is triggered by the synchronized output signal.

19. The method of claim 17, further comprising: incrementing, by a counter in the second clock domain, a time value within the second clock domain by an amount based on the synchronized output signal.

20. The method of any one of claims 17-19, wherein the input signal is a clock signal from the reference clock.

21. The method of any one of claims 17-20, further comprising: detecting, by the convergence logic, the number of toggle signals changing state during a single cycle of the core clock.

22. The method of claim 21, wherein the convergence logic is operable to support all core clock frequency ranges greater than or equal to the frequency of the reference clock.

23. The method of claim 21 or claim 22, wherein the core clock has a frequency greater than or equal to the frequency of the reference clock.

24. The method of claim 21, wherein the convergence logic is operable to support all core clock frequency ranges greater than or equal to one and a half times the frequency of the reference clock divided by the number of toggle signals.

25. The method of claim 21 or claim 24, wherein the core clock has a frequency greater than or equal to one and a half times the frequency of the reference clock divided by the number of toggle signals.

26. The method of any one of claims 21-23, further comprising, whenever multiple toggle signals change state during a given single cycle of the core clock: transmitting, by the convergence logic, an active synchronized output signal for the given cycle of the core clock; and increasing, by the convergence logic, a pending toggle count for a future idle cycle.

27. The method of claim 26, further comprising, whenever no toggle signals change state during a given single cycle of the core clock and the pending toggle count is greater than zero: decrementing, by the convergence logic, the pending toggle count; and transmitting, by the convergence logic, an active synchronized output signal for the given cycle of the core clock.

28. The method of any one of claims 17-27, further comprising: incrementing, by the convergence logic, at each cycle of the core clock, the time value for the core clock by a number less than or equal to the number of toggle signals that change state during the cycle of the core clock.

29. The method of claim 28, further comprising: incrementing, by the convergence logic, at each cycle of the core clock, the time value for the core clock by the number of toggle signals that change state during the cycle of the core clock.

30. The method of any one of claims 17-29, wherein generating the plurality of toggle signals further comprises: generating each of the toggle signals by performing frequency division of the input signal.

31. The method of any one of claims 17-30, wherein generating the plurality of toggle signals further comprises: generating each of the toggle signals by performing frequency division of the input signal at different time offsets.

32. The method of any one of claims 17-31, wherein generating the plurality of toggle signals further comprises: generating, by the first circuitry, a plurality of toggle signals that cross into the second clock domain by performing frequency division of the input signal to the frequency of the reference clock divided by twice the number of toggle signals with a time offset of one reference clock cycle between the generated toggle signals.

33. A computer storage medium encoded with instructions that are operable, when executed by data processing apparatus, to cause the data processing apparatus to perform operations comprising the method of any one of claims 17-32.