EP4684514A1

EP4684514A1 - Crest factor reduction for adjusting digital-to- analog converter output power

Info

Publication number: EP4684514A1
Application number: EP24713352.3A
Authority: EP
Inventors: Idan Michael Horn; Shay Landis; Yehonatan DALLAL
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2023-03-23
Filing date: 2024-02-29
Publication date: 2026-01-28
Also published as: IL301599B2; CN120883581A; IL301599A; IL301599B1; WO2024196562A1

Abstract

Methods and apparatus for performing crest factor reduction (CFR) to adjust the output power of a digital-to-analog converter (DAC) are described. An example method includes applying a CFR to a digital input signal to generate a crest factor reduced signal. Applying the CFR includes (a) adjusting an amplitude of a real component of the digital input signal, based on a first threshold, while maintaining a phase of the digital input signal and (b) adjusting an amplitude of an imaginary component of the digital input signal, based on a second threshold, while maintaining the phase of the digital input signal. The crest factor reduced signal is converted to an analog signal via a DAC.

Description

CREST FACTOR REDUCTION FOR ADJUSTING DIGITAL-TO-

ANAEOG CONVERTER OUTPUT POWER

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to Israel Patent Application No. 301599, filed March 23, 2023, which is assigned to the assignee hereof and hereby expressly incorporated by reference in its entirety as if fully set forth below and for all applicable purposes.

TECHNICAL FIELD

[0002] Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to techniques and apparatus for performing crest factor reduction for a digital-to-analog converter (DAC).

BACKGROUND

[0003] Wireless communication devices are widely deployed to provide various communication services such as telephony, video, data, messaging, broadcasts, and so on. Such wireless communication devices may transmit and/or receive radio frequency (RF) signals via any of various suitable radio access technologies (RATs) including, but not limited to, 5G New Radio (NR), Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobility (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, wireless local area network (WLAN) RATs (e.g., WiFi), and the like.

[0004] A wireless communication network may include a number of base stations that can support communication for a number of mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. The downlink (or forward link) refers to the communication link from the base station to the mobile station, and the uplink (or reverse link) refers to the communication link from the mobile station to the base station. A base station may transmit data and control information on the downlink to a mobile station and/or may receive data and control information on the uplink from the mobile station. The base station and/or mobile station may include a transmission digital-to-analog converter (TX DAC), which may be used, for example, to convert a digital signal to an analog signal for signal processing (e.g., filtering, upconverting, and amplifying) before transmission by one or more antennas.

SUMMARY

[0005] The systems, methods, and devices of the disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this disclosure as expressed by the claims which follow, some features will now be discussed briefly. After considering this discussion, and particularly after reading the section entitled “Detailed Description,” one will understand how the features of this disclosure provide advantages that include, but are not limited to, increasing the output power of a DAC.

[0006] Certain aspects of the present disclosure provide a method for wireless communications. The method generally includes applying a crest factor reduction to a digital input signal to generate a crest factor reduced signal. Applying the crest factor reduction includes (a) adjusting an amplitude of a real component of the digital input signal, based on a first threshold, while maintaining a phase of the digital input signal, and (b) adjusting an amplitude of an imaginary component of the digital input signal, based on a second threshold, while maintaining the phase of the digital input signal. The method also includes converting the crest factor reduced signal to an analog signal via a DAC.

[0007] Certain aspects of the present disclosure provide an apparatus for wireless communication. The apparatus includes at least one processor, a DAC, and a memory coupled to the at least one processor. The at least one processor is configured to apply a crest factor reduction to a digital input signal to generate a crest factor reduced signal. In order to apply the crest factor reduction, the at least one processor is configured to (a) adjust an amplitude of a real component of the digital input signal, based on a first threshold, while maintaining a phase of the digital input signal, and (b) adjust an amplitude of an imaginary component of the digital input signal, based on a second threshold, while maintaining the phase of the digital input signal. The DAC is configured to convert the crest factor reduced signal to an analog signal. [0008] Certain aspects of the present disclosure provide an apparatus for wireless communication. The apparatus generally includes means for applying a crest factor reduction to a digital input signal to generate a crest factor reduced signal. The means for applying the crest factor reduction includes (a) means for adjusting an amplitude of a real component of the digital input signal, based on a first threshold, while maintaining a phase of the digital input signal, and (b) means for adjusting an amplitude of an imaginary component of the digital input signal, based on a second threshold, while maintaining the phase of the digital input signal. The apparatus also includes means for converting the crest factor reduced signal to an analog signal.

[0009] To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed, and this description is intended to include all such aspects and their equivalents.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.

[0011] FIG. 1 is a diagram of an example wireless communications network, in which aspects of the present disclosure may be practiced.

[0012] FIG. 2 is a block diagram conceptually illustrating a design of an example a base station (BS) and user equipment (UE), in which aspects of the present disclosure may be practiced.

[0013] FIG. 3 is a block diagram of an example radio frequency (RF) transceiver, in which aspects of the present disclosure may be practiced. [0014] FIG. 4A illustrates an example polar clipping crest factor reduction (CFR) scenario, according to certain aspects of the present disclosure.

[0015] FIG. 4B illustrates an example independent real and imaginary component CFR scenario, according to certain aspects of the present disclosure.

[0016] FIG. 5 is a block diagram conceptually illustrating one or more components of an RF transmitter configured to perform CFR, according to certain aspects of the present disclosure.

[0017] FIG. 6A illustrates a graph of a threshold applied to real signal samples of a digital signal, according to certain aspects of the present disclosure.

[0018] FIG. 6B illustrates a graph of a threshold applied to imaginary signal samples of a digital signal, according to certain aspects of the present disclosure.

[0019] FIG. 6C illustrates a graph of a threshold applied to complex signal samples of a digital signal, according to certain aspects of the present disclosure.

[0020] FIG. 7 is a flow diagram of example operations for performing CFR for a DAC, in accordance with certain aspects of the present disclosure.

[0021] FIG. 8A illustrates a flowchart of an example method for performing CFR for a DAC, in accordance with certain aspects of the present disclosure.

[0022] FIG. 8B illustrates a flowchart of another example method for performing CFR for a DAC, in accordance with certain aspects of the present disclosure.

[0023] FIG. 9A illustrates a constellation diagram with polar clipping CFR.

[0024] FIG. 9B illustrates a constellation diagram with independent-component CFR, in accordance with certain aspects of the present disclosure.

[0025] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0026] Certain aspects of the present disclosure relate to techniques and apparatus for performing crest factor reduction (CFR) to adjust (e.g., increase) the output power of a digital-to-analog converter (DAC) in a communication system, for example. The techniques and apparatus described herein may be implemented in a communication system operating in the sub-terahertz (Sub-THz) spectrum.

[0027] The Sub-THz spectrum generally refers to frequency spectrum ranging between 90 gigahertz (GHz) and 300 GHz. The Sub-THz spectrum offers high available spectrum bandwidths (e.g., tens of GHz), which can be used to achieve very high throughputs (e.g., ~ 1 terabyte per second). However, one of the main challenges with operating in the Sub-THz spectrum is strong path loss due to the increase in the carrier frequency and low achievable output power from the power amplifiers (PAs) due to transistor limitations.

[0028] In order to support the high bandwidths of the Sub-THz spectrum, the DAC(s) and analog-to-digital converter(s) (ADC(s)) in a communication system may use high sampling rates, increasing the complexity and power consumption of these components. To reduce the complexity of the DAC(s) and ADC(s), the effective number of bits (ENOB) of the DAC(s) and ADC(s) can be reduced, but at the cost of an increase in the error vector magnitude (EVM) of the communication system.

[0029] To address this, certain aspects described herein provide techniques for using an improved CFR technique to increase the output power of a DAC in a transmitter. Conventional CFR is a technique generally used to reduce the peak-to-average-power ratio (PAPR) of a signal supplied to PAs in a communication system, for example, in order to increase the PA input signal power. CFR can be used to reduce PAPR by limiting the signal peaks sent to the PA to a desired threshold value. CFR can be implemented using various methods, such as polar clipping, peak windowing, noise shaping, pulse injection, and peak cancellation.

[0030] Compared to using conventional CFR methods, such as polar clipping, to reduce the PAPR of a complex signal at the input to the PA of a transmitter, aspects described herein may use an independent-component CFR technique that reduces the PAPR of each real and imaginary signal (e.g., each in-phase (I) and quadrature (Q) component of a complex signal) that is input to the DAC of the transmitter, while maintaining the complex signal’s phase. Using CFR in this manner can increase (e.g., maximize) the DAC’s output power, reduce the ratio between the (i) DAC’s quantization noise floor affected by the ENOB and (ii) signal power, increase baseband output power, and increase throughput.

[0031] Various aspects of the disclosure are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure disclosed herein, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.

[0032] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0033] As used herein, the term “connected with” in the various tenses of the verb “connect” may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element ). In the case of electrical components, the term “connected with” may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements^ and B (and any components electrically connected therebetween). An Example Wireless System

[0034] FIG. 1 illustrates an example wireless communications network 100, in which aspects of the present disclosure may be practiced. For example, the wireless communications network 100 may be a New Radio (NR) system (e.g., a Fifth Generation (5G) NR network), an Evolved Universal Terrestrial Radio Access (E-UTRA) system (e.g., a Fourth Generation (4G) network), a Universal Mobile Telecommunications System (UMTS) (e.g., a Second Generation/Third Generation (2G/3G) network), or a code division multiple access (CDMA) system (e.g., a 2G/3G network), or may be configured for communications according to an IEEE standard such as one or more of the 802.11 standards, etc.

[0035] As illustrated in FIG. 1, the wireless communications network 100 may include a number of base stations (BSs) 1 lOa-z (each also individually referred to herein as “BS 110” or collectively as “BSs 110”) and other network entities. A BS may also be referred to as an access point (AP), an evolved Node B (eNodeB or eNB), a next generation Node B (gNodeB or gNB), or some other terminology.

[0036] A BS 110 may provide communication coverage for a particular geographic area, sometimes referred to as a “cell,” which may be stationary or may move according to the location of a mobile BS 110. In some examples, the BSs 110 may be interconnected to one another and/or to one or more other BSs or network nodes (not shown) in wireless communications network 100 through various types of backhaul interfaces (e.g., a direct physical connection, a wireless connection, a virtual network, or the like) using any suitable transport network. In the example shown in FIG. 1, the BSs 110a, 110b, and 110c may be macro BSs for the macro cells 102a, 102b, and 102c, respectively. The BS HOx may be a pico BS for a pico cell 102x. The BSs 1 lOy and 1 lOz may be femto BSs for the femto cells 102y and 102z, respectively. A BS may support one or multiple cells.

[0037] The BSs 110 communicate with one or more user equipments (UEs) 120a-y (each also individually referred to herein as “UE 120” or collectively as “UEs 120”) in the wireless communications network 100. A UE may be fixed or mobile and may also be referred to as a user terminal (UT), a mobile station (MS), an access terminal, a station (STA), a client, a wireless device, a mobile device, or some other terminology. A user terminal may be a wireless device, such as a cellular phone, a smartphone, a personal digital assistant (PDA), a handheld device, a wearable device, a wireless modem, a laptop computer, a tablet, a personal computer, etc.

[0038] The BSs 110 are considered transmitting entities for the downlink and receiving entities for the uplink. The UEs 120 are considered transmitting entities for the uplink and receiving entities for the downlink. As used herein, a “transmitting entity” is an independently operated apparatus or device capable of transmitting data via a frequency channel, and a “receiving entity” is an independently operated apparatus or device capable of receiving data via a frequency channel. In the following description, the subscript “d ” denotes the downlink, the subscript “np” denotes the uplink. N_up UEs may be selected for simultaneous transmission on the uplink, Ndn UEs may be selected for simultaneous transmission on the downlink. N_up may or may not be equal to Ndn, and N_up and Ndn may be static values or can change for each scheduling interval. Beamsteering or some other spatial processing technique may be used at the BSs 110 and/or UEs 120.

[0039] The UEs 120 (e.g., 120x, 120y, etc.) may be dispersed throughout the wireless communications network 100, and each UE 120 may be stationary or mobile. The wireless communications network 100 may also include relay stations (e.g., relay station 1 lOr), also referred to as relays or the like, that receive a transmission of data and/or other information from an upstream station (e.g., a BS 110a or a UE 120r) and send a transmission of the data and/or other information to a downstream station (e.g., a UE 120 or a BS 110), or that relays transmissions between UEs 120, to facilitate communication between devices.

[0040] The BSs 110 may communicate with one or more UEs 120 at any given moment on the downlink and uplink. The downlink (i.e., forward link) is the communication link from the BSs 110 to the UEs 120, and the uplink (i.e., reverse link) is the communication link from the UEs 120 to the BSs 110. A UE 120 may also communicate peer-to-peer with another UE 120.

[0041] The wireless communications network 100 may use multiple transmit and multiple receive antennas for data transmission on the downlink and uplink. BSs 110 may be equipped with a number N_ap of antennas to achieve transmit diversity for downlink transmissions and/or receive diversity for uplink transmissions. A set N_u of UEs 120 may receive downlink transmissions and transmit uplink transmissions. Each UE 120 may transmit user-specific data to and/or receive user-specific data from the BSs 110. In general, each UE 120 may be equipped with one or multiple antennas. The N_u UEs 120 can have the same or different numbers of antennas.

[0042] The wireless communications network 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communications network 100 may also utilize a single carrier or multiple carriers for transmission. Each UE 120 may be equipped with a single antenna (e.g., to keep costs down) or multiple antennas (e.g., where the additional cost can be supported).

[0043] A network controller 130 (also sometimes referred to as a “system controller”) may be in communication with a set of BSs 110 and provide coordination and control for these BSs 110 (e.g., via a backhaul). In certain cases (e.g., in a 5G NR system), the network controller 130 may include a centralized unit (CU) and/or a distributed unit (DU). In certain aspects, the network controller 130 may be in communication with a core network 132 (e.g., a 5G Core Network (5GC)), which provides various network functions such as Access and Mobility Management, Session Management, User Plane Function, Policy Control Function, Authentication Server Function, Unified Data Management, Application Function, Network Exposure Function, Network Repository Function, Network Slice Selection Function, etc.

[0044] In certain aspects of the present disclosure, the BSs 110 and/or the UEs 120 may include circuitry configured to perform crest factor reduction to increase the output power of a DAC in the transmit (TX) path, as described in more detail herein.

[0045] FIG. 2 illustrates example components of BS 110a and UE 120a (e.g., from the wireless communications network 100 of FIG. 1), in which aspects of the present disclosure may be implemented.

[0046] On the downlink, at the BS 110a, a transmit processor 220 may receive data from a data source 212, control information from a controller/processor 240, and/or possibly other data (e.g., from a scheduler 244). The various types of data may be sent on different transport channels. For example, the control information may be designated for the physical broadcast channel (PBCH), physical control format indicator channel (PCFICH), physical hybrid automatic repeat request (HARQ) indicator channel (PHICH), physical downlink control channel (PDCCH), group common PDCCH (GC PDCCH), etc. The data may be designated for the physical downlink shared channel (PDSCH), etc. A medium access control (MAC)-control element (MAC-CE) is a MAC layer communication structure that may be used for control command exchange between wireless nodes. The MAC-CE may be carried in a shared channel such as a PDSCH, a physical uplink shared channel (PUSCH), or a physical sidelink shared channel (PSSCH).

[0047] The processor 220 may process (e.g., encode and symbol map) the data and control information to obtain data symbols and control symbols, respectively. The transmit processor 220 may also generate reference symbols, such as for the primary synchronization signal (PSS), secondary synchronization signal (SSS), PBCH demodulation reference signal (DMRS), and channel state information reference signal (CSI-RS).

[0048] A transmit (TX) multiple-input, multiple-output (MIMO) processor 230 may perform spatial processing (e.g., precoding) on the data symbols, the control symbols, and/or the reference symbols, if applicable, and may provide output symbol streams to the modulators (MODs) in transceivers 232a-232t. Each modulator in transceivers 232a- 232t may process a respective output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM), etc.) to obtain an output sample stream. Each of the transceivers 232a-232t may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain a downlink signal. Downlink signals from the transceivers 232a-232t may be transmitted via the antennas 234a-234t, respectively.

[0049] At the UE 120a, the antennas 252a-252r may receive the downlink signals from the BS 110a and may provide received signals to the transceivers 254a-254r, respectively. The transceivers 254a-254r may condition (e.g., filter, amplify, downconvert, and digitize) a respective received signal to obtain input samples. Each demodulator (DEMOD) in the transceivers 232a-232t may further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. A MIMO detector 256 may obtain received symbols from all the demodulators in transceivers 254a-254r, perform MIMO detection on the received symbols if applicable, and provide detected symbols. A receive processor 258 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for the UE 120a to a data sink 260, and provide decoded control information to a controller/processor 280.

[0050] On the uplink, at UE 120a, a transmit processor 264 may receive and process data (e.g., for the physical uplink shared channel (PUSCH)) from a data source 262 and control information (e.g., for the physical uplink control channel (PUCCH)) from the controller/processor 280. The transmit processor 264 may also generate reference symbols for a reference signal (e.g., the sounding reference signal (SRS)). The symbols from the transmit processor 264 may be precoded by a TX MIMO processor 266 if applicable, further processed by the modulators (MODs) in transceivers 254a-254r (e.g., for single-carrier frequency division multiplexing (SC-FDM), etc.), and transmitted to the BS 110a. At the BS 110a, the uplink signals from the UE 120a may be received by the antennas 234, processed by the demodulators in transceivers 232a-232t, detected by a MIMO detector 236 if applicable, and further processed by a receive processor 238 to obtain decoded data and control information sent by the UE 120a. The receive processor 238 may provide the decoded data to a data sink 239 and the decoded control information to the controller/processor 240.

[0051] The memories 242 and 282 may store data and program codes for BS 110a and UE 120a, respectively. The memories 242 and 282 may also interface with the controllers/processors 240 and 280, respectively. A scheduler 244 may schedule UEs for data transmission on the downlink and/or uplink.

[0052] Antennas 252, processors 258, 264, 266, and/or controller/processor 280 of the UE 120a and/or antennas 234, processors 220, 230, 238, and/or controller/processor 240 of the BS 110a may be used to perform the various techniques and methods described herein.

[0053] In certain aspects of the present disclosure, the processors 264, 266, and/or controller/processor 280 of the UE 120a, and/or the processors 220, 230, and/or controller/processor 240 of the BS 110a may perform crest factor reduction to increase the output power of a DAC in the respective TX path, as described in more detail herein. Example RF Transceiver

[0054] FIG. 3 is a block diagram of an example radio frequency (RF) transceiver circuit 300, in accordance with certain aspects of the present disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also known as a “transmit chain”) for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also known as a “receive chain”) for receiving signals via the antennas 306. When the TX path 302 and the RX path 304 share an antenna 306, the paths may be connected with the antenna via an interface 308, which may include any of various suitable RF devices, such as a switch, a duplexer, a diplexer, a multiplexer, and the like.

[0055] Receiving in-phase (I) and/or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, the mixer 314, the DA 316, and the PA 318 may be included in a radio frequency integrated circuit (RFIC). For certain aspects, the PA 318 may be external to the RFIC.

[0056] The BBF 312 filters the baseband signals received from the DAC 310, and the mixer 314 mixes the filtered baseband signals with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to a radio frequency). This frequency-conversion process produces the sum and difference frequencies between the LO frequency and the frequencies of the baseband signal of interest. The sum and difference frequencies are referred to as the “beat frequencies.” The beat frequencies are typically in the RF range, such that the signals output by the mixer 314 are typically RF signals, which may be amplified by the DA 316 and/or by the PA 318 before transmission by the antenna(s) 306. While one mixer 314 is illustrated, several mixers may be used to upconvert the filtered baseband signals to one or more intermediate frequencies and to thereafter upconvert the intermediate frequency (IF) signals to a frequency for transmission.

[0057] The RX path 304 may include a low noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, the mixer 326, and the BBF 328 may be included in one or more RFICs, which may or may not be the same RFIC that includes the TX path components. RF signals received via the antenna(s) 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signals with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., downconvert). The baseband signals output by the mixer 326 may be filtered by the BBF 328 before being converted by an analog-to-digital converter (ADC) 330 to digital I and/or Q signals for digital signal processing.

[0058] Certain transceivers may employ frequency synthesizers with a variablefrequency oscillator (e.g., a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a particular tuning range. Thus, the transmit LO may be produced by a TX frequency synthesizer 320, which may be buffered or amplified by amplifier 322 before being mixed with the baseband signals in the mixer 314. Similarly, the receive LO may be produced by an RX frequency synthesizer 332, which may be buffered or amplified by amplifier 334 before being mixed with the RF signals in the mixer 326. For certain aspects, a single frequency synthesizer may be used for both the TX path 302 and the RX path 304. In certain aspects, the TX frequency synthesizer 320 and/or RX frequency synthesizer 332 may include a frequency multiplier, such as a frequency doubler, that is driven by an oscillator (e.g., a VCO) in the frequency synthesizer.

[0059] A controller 336 (e.g., controller/processor 280, processor 264, or processor 266 of UE 120a or controller/processor 240, processor 220, or processor 230 of the BS 110a in FIG. 2) may direct the operation of the RF transceiver circuit 300, such as transmitting signals via the TX path 302 and/or receiving signals via the RX path 304. The controller 336 may be a processor, a digital signal processor (DSP), an applicationspecific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. A memory 338 (e.g., memory 282 in FIG. 2) may store data and/or program codes for operating the RF transceiver circuit 300. The controller 336 and/or the memory 338 may include control logic (e.g., complementary metal-oxide-semiconductor (CMOS) logic).

[0060] In certain aspects, the controller 336 is configured to perform crest factor reduction to increase the output power of the DAC 310, as described in more detail herein. [0061] While FIGs. 1-3 provide wireless communications as an example application in which certain aspects of the present disclosure may be implemented to facilitate understanding, certain aspects described herein may be used for crest factor reduction in any of various other suitable systems (e.g., an audio system or other electronic system).

Example Crest Factor Reduction to Adjust DAC Output Power

[0062] As noted, conventional CFR techniques, such as polar clipping CFR, generally involve reducing the PAPR of a complex signal (e.g., combined I and Q signals) by reducing the signal’s amplitude and maintaining the phase. An example polar clipping CFR scenario is shown in the constellation diagram 900A of FIG. 9A, where the x-axis represents the I component in the complex plane and the y-axis represents the Q component in the complex plane. Each of the arrows in the constellation diagram 900A indicates a reduction in signal amplitude along a particular phase angle. However, reducing the amplitude of the complex signal (as opposed to separately reducing the amplitude of the I and Q signals) may not increase the output power of the DAC, making this conventional CFR technique unsuitable for communication systems operating in certain frequency ranges, such as the Sub-THz spectrum.

[0063] Consider FIG. 4A, which depicts an example polar clipping CFR scenario 400 A, according to certain aspects described herein. Here, the matrix 410 includes multiple pairs of I and Q samples over a time period, where each pair of the I and Q samples are aligned in time (e.g., the samples in each respective column of the matrix 410 are for the same moment in time). In this polar clipping scenario, given the initial I and Q samples in the matrix 410, the polar clipping CFR technique generates an amplitude vector 420, which includes a respective complex amplitude value (= (I² + Q²)) for each pair of I and Q samples in the matrix 410 (e.g., each column of the matrix 410). The polar clipping CFR technique may then perform amplitude thresholding on the amplitude vector 420 using a threshold, which may be based on a target gain of the DAC (e.g., a transmit DAC, such as DAC 310). Here, for example, the polar clipping CFR technique uses a threshold = 1 (which is based on a target 3 dB gain) on the amplitude vector 420 to generate an amplitude-reduced vector 430.

[0064] The polar clipping CFR technique uses the amplitude-reduced vector 430 to reduce the amplitude values of certain initial I and Q values in the matrix 410 (which have complex amplitudes that do not pass the threshold), while maintaining the phase. As shown, for example, the polar clipping CFR technique generates a matrix 440 which includes a modified set of I and Q samples (relative to the initial I and Q samples in matrix 410). In particular, the amplitude values of the I and Q samples in the 2^nd, 3^rd, 4^th, and 5^th columns of the matrix 440 have been reduced relative to the amplitude values of the initial I and Q samples in the 2^nd, 3^rd, 4^th, and 5^th columns of the matrix 410, respectively, based on ratios between amplitude values in the amplitude-reduced vector 430 to the corresponding amplitude values in the amplitude vector 420 over the threshold. However, as shown in FIG. 4 A, using the I and Q samples in the matrix 440 from amplitude thresholding as the DAC’ s input may not result in a change in the DAC’ s output power. Here, for example, the DAC’s power gain is 0 dB, since at least one of the I and Q samples in the matrix 440 is already at the maximum value of 1.0.

[0065] To address this, aspects described herein provide techniques for applying an improved CFR technique to adjust the output power of a DAC in a transmitter. In certain aspects, the improved CFR technique described herein involves separately reducing the amplitude of the I and Q components (the real and imaginary components) of a complex digital input signal to the DAC, while maintaining the phase of the complex digital input signal. An example of independent-component CFR is shown in the constellation diagram 900B of FIG. 9B.

[0066] FIG. 5 is a block diagram conceptually illustrating one or more components of an RF transmitter circuit 500 configured to perform CFR (e.g., for a DAC), according to certain aspects described herein. The RF transmitter circuit 500 may be similar to the transmit chain of the RF transceiver circuit 300 depicted in FIG. 3. As shown, the RF transmitter circuit 500 includes a processor 502, a DAC 506, a combiner/upconverter circuit 508, a filter 510, a CFR circuit 512, and an amplifier 516.

[0067] The processor 502 may be similar to one or more of the processors 264, 266, and/or controller/processor 280 of the UE 120a, or the processors 220, 230, and/or controller/processor 240 of the BS 110a. Here, the processor 502 incudes CFR logic 504, which is configured to perform independent-component CFR to adjust the output power of the DAC 506. In addition to performing independent-component CFR to adjust the output power of the DAC 506, the CFR logic 504 may perform other CFR techniques, such as polar clipping CFR, before or after the independent-component CFR is performed. For example, the CFR logic 504 may include one or more CFR blocks, each configured to perform a respective CFR technique.

[0068] As shown, the I signal (e.g., real component) and Q signal (e.g., imaginary component) of a complex digital input signal is applied to the CFR logic 504. In some aspects, the CFR logic 504 reduces the amplitude of each of the I signal and the Q signal separately, while maintaining the phase of the complex digital input signal, to produce amplitude-reduced signals IR and QR. In some aspects, the CFR logic 504 may reduce the amplitudes of the I signal and Q signal, based on respective clipping thresholds that are determined based on a target gain of the DAC 506. For example, FIG. 6A illustrates a graph 600 A of a clipping threshold 610 applied to amplitudes of I component samples, and FIG. 6B illustrates a graph 600B of a clipping threshold 620 applied to amplitudes of Q component samples, according to certain aspects described herein. In some aspects, the clipping threshold 610 and the clipping threshold 620 may be the same (e.g., if the I and Q signals are symmetric). In another aspect, the clipping threshold 610 and the clipping threshold 620 may be different (e.g., if the I and Q signals are not symmetric).

[0069] The DAC 506 (e.g., similar to DAC 310) converts the amplitude-reduced signals IR and QR to the analog domain, producing analog signals Is and Qs. In certain aspects described below, the DAC 506 may apply a gain factor to the amplitude-reduced signals IR and QR, prior to the conversion to the analog domain. In these aspects, the analog signals Is and Qs may be amplified relative to the amplitude-reduced signals IR and QR, respectively. In certain aspects, another component/logic block implemented prior to the DAC 506 may apply the gain factor to the I and Q signals.

[0070] The combiner/upconverter circuit 508 combines the analog signals Is and Qs and upconverts the combined signal to produce a crest factor reduced signal SCFR. In certain aspects, the combiner/upconverter circuit 508 may be implemented, in part, with a quadrature mixer. In certain aspects, the crest factor reduced signal SCFR may have a frequency for transmission in the Sub-THz spectrum (e.g., 90 GHz to 300 GHz). In these aspects, the combiner/upconverter circuit 508 may combine the analog signals Is and Qs and upconvert the combined signal one or more times to generate the crest factor reduced signal SCFR having a frequency for transmission, for example, in the Sub-THz spectrum. The filter 510 (e.g., similar to BBF 312) filters the crest factor reduced signal SCFR to generate a filtered crest factor reduced signal SCFRI . [0071] The optional CFR circuit 512 may apply another CFR technique (e.g., polar clipping CFR or other CFR) to the filtered crest factor reduced signal SCFRI to produce another crest factor reduced signal SCFR2. In certain aspects, the other CFR technique is a polar clipping CFR, which reduces the amplitude of the filtered crest factor reduced signal SCFRI based on a clipping threshold, while maintaining a phase of the filtered crest factor reduced signal SCFRI . FIG. 6C illustrates a graph 600C of a clipping threshold 630 applied to amplitude samples of an analog signal (or a signal-processed version of the analog signal), according to certain aspects described herein. The amplifier 516 (e.g., similar to DA 316 and/or PA 318) amplifies the crest factor reduced signal SCFR2 to generate an amplified crest factor reduced signal SCFRS.

Example CFR Operations

[0072] FIG. 7 is a flow diagram of example operations 700 for performing CFR to adjust the output power of a DAC (e.g., DAC 506), in accordance with certain aspects of the present disclosure. The operations 700 may be performed, for example, by a processor (e.g., processor 502).

[0073] The operations 700 may generally involve, at block 702, applying a CFR to a digital input signal (e.g., a complex digital signal) to generate a crest factor reduced signal. Applying the CFR to the digital input signal may include, at block 704, adjusting an amplitude of a real component (e.g., an in-phase (I) component) of the digital input signal, based on a first threshold (e.g., clipping threshold 610), while maintaining a phase of the digital input signal. Applying the CFR to the digital input signal may also include, at block 706, adjusting an amplitude of an imaginary component (e.g., a quadrature (Q) component) of the digital input signal, based on a second threshold (e.g., clipping threshold 620), while maintaining the phase of the digital input signal.

[0074] In some aspects, at least one of the first threshold or the second threshold may be based on a target gain of the DAC. In some aspects, at least one of the first threshold or the second threshold may be based on a PAPR value or on the DAC maximal allowed input voltage. In some aspects, the operations in block 704 may be performed prior to the operations in block 706. In another aspect, the operations in block 706 may be performed prior to the operations in block 704. [0075] The operations 700 may also involve, at block 708, converting the crest factor reduced signal to an analog signal via a DAC (e.g., DAC 506). Converting the crest factor reduced signal may include, at block 710, applying a gain factor to the crest factor reduced signal to generate a gained signal. In certain aspects, the gain factor may be applied via the DAC. In other aspects, the gain factor may be applied by logic before the DAC. Converting the crest factor reduced signal may also include, at block 712, converting the gained signal to the analog signal using the DAC.

[0076] In certain aspects, adjusting the amplitude of the real component of the digital input signal while maintaining the phase of the digital input signal (in block 704) may include, for each sample of the real component of the digital input signal having an amplitude value greater than the first threshold: (i) reducing the amplitude value of the sample of the real component to the first threshold, and (ii) reducing an amplitude value of a sample of the imaginary component of the digital input signal, corresponding in time to the sample of the real component, by an amount that is based on a ratio of the amplitude value of the sample of the real component to the amplitude value of the sample of the imaginary component. In these aspects, the amplitude value of the sample of the imaginary component may be reduced to an amplitude value that is equal to the first threshold divided by the ratio of the amplitude value of the sample of the real component to the amplitude value of the sample of the imaginary component.

[0077] In certain aspects, adjusting the amplitude of the imaginary component of the digital input signal while maintaining the phase of the digital input signal (in block 706) may include, for each sample of the imaginary component of the digital input signal having an amplitude value greater than the second threshold: (i) reducing the amplitude value of the sample of the imaginary component to the second threshold, and (ii) reducing an amplitude value of the sample of the real component of the digital input signal, corresponding in time to the sample of the imaginary component, by an amount that is based on the ratio of the amplitude value of the sample of the real component to the amplitude value of the sample of the imaginary component. In these aspects, the amplitude value of the sample of the imaginary component may be reduced to an amplitude value that is equal to the second threshold multiplied by the ratio of the amplitude value of the sample of the real component to the amplitude value of the imaginary component. [0078] In certain aspects, the operations 700 may further involve applying another CFR to the analog signal or a signal-processed version of the analog signal to generate another crest factor reduced signal. In these aspects, the other CFR may involve (i) adjusting an amplitude of the analog signal or a signal-processed version of the analog signal based on a third threshold (e.g., threshold 630), while maintaining a phase of the analog signal, and (ii) amplifying the other crest factor reduced signal via an amplifier. In some aspects, the other CFR includes polar clipping CFR or another CFR technique.

[0079] In certain aspects, the operations 700 may further involve applying another CFR to a signal to generate the digital input signal, before applying the CFR to the digital input signal (e.g., in block 702). In these aspects, the other CFR may include polar clipping CFR or another CFR technique.

[0080] In certain aspects, the operations 700 may further involve (i) combining a real component of the analog signal and an imaginary component of the analog signal to generate a combined signal and (ii) upconverting the combined signal one or more times to generate a signal having a frequency for transmission in a range from 90 GHz to 300 GHz.

[0081] FIG. 8A illustrates a flowchart of an example method 800A for performing CFR to adjust the output power of a DAC (e.g., DAC 506), according to certain aspects of the present disclosure. Method 800A may be performed, for example, by a processor (e.g., processor 502).

[0082] Method 800A may enter at block 802A, where the processor determines a first threshold (e.g., Ithreshoid) and a second threshold (e.g., Qthreshoid), based on the digital input signal. For example, at least one of the first threshold or the second threshold may be based or set on a target gain of the DAC. Referring to FIG. 4B, which depicts an example scenario 400B of CFR being applied separately to I and Q signals, the first threshold may be set to 0.8 and the second threshold may be set to 0.8.

[0083] Blocks 804A and 806A may be performed for each real signal sample having a higher amplitude value than the first threshold. At block 804A, the processor reduces the amplitude value of the real signal sample to the first threshold. In FIG. 4B, for example, after applying I thresholding in a first stage (labeled “Stage 1”) to the I values in the matrix 410, the method 800 generates a matrix 450 in which the amplitude values of I samples in the corresponding 1^st, 2^nd, 3^rd, and 4^th columns of the matrix 450 have been reduced to the Ithreshoid = 0.8, relative to the amplitude values of the initial I samples in the 1^st, 2^nd, 3^rd, and 4^th columns of the matrix 410. Note, the first stage depicted in FIG. 4B is when the independent I-component CFR is performed on the initial I samples in the matrix 410.

[0084] At block 806A, the processor reduces the amplitude value of the imaginary signal sample, corresponding in time to the real signal sample, by an amount that is based on a ratio of the amplitude value of the real signal sample to the amplitude value of the imaginary signal sample. Referring again to FIG. 4B, for example, the amplitude value of the Q sample in the 2^nd column of matrix 450 has been reduced to a reduced amplitude value (e.g., Q = 0.44) equal to the Ithreshoid (e.g., Ithreshoid = 0.8) divided by the ratio of the amplitude value of the initial I sample in the 2^nd column of matrix 410 (e.g., linitiai = 0.9) to the amplitude value of the initial Q sample in the 2^nd column of matrix 410 (e.g., Qinitiai = 0.5).

[0085] Blocks 808 A and 810A may be performed for each imaginary signal sample having a higher amplitude value than the second threshold. At block 808A, the processor reduces the amplitude value of the imaginary signal sample to the second threshold. In FIG. 4B, for example, after applying Q thresholding in a second stage (labeled “Stage 2”) to the Q values in the matrix 450, method 800A generates a matrix 460 in which the amplitude value of the Q sample in the corresponding 5^th column of the matrix 460 has been reduced to the Qthreshoid = 0.8, relative to the amplitude values of the initial I samples in the 1^st, 2^nd, 3^rd, and 4^th columns of the matrix 450. Note, the second stage depicted in FIG. 4B is when the independent Q-component CFR is performed on the Q samples in the matrix 450.

[0086] At block 810A, the processor reduces the amplitude value of the real signal sample, corresponding in time to the imaginary signal sample, by an amount that is based on a ratio of the amplitude value of the real signal sample to the amplitude value of the imaginary signal sample. Referring again to FIG. 4B, for example, the amplitude value of the I sample in the 5^th column of matrix 460 has been reduced to a reduced amplitude value (e.g., I = 0.48) equal to the Qthreshoid (e.g., Qthreshoid = 0.8) multiplied by the ratio of the amplitude value of the I sample in the 5^th column of matrix 450 (e.g., Istagei = 0.6) to the amplitude value of the Q sample in the 5^th column of matrix 450 (e.g., Qstagei = 1.0). The amplitude values of the I and Q samples in the matrix 460 are crest factor reduced values (resulting in signals with reduced PAPR) that can now be amplified. Additionally, note that the phase of the complex digital signal has been preserved in the matrix 460, because the ratio of the Q amplitude to the I amplitude for each pair of I and Q samples (corresponding in time) has been preserved between the matrix 460 (Stage 2) and the matrix 410 (e.g., initial matrix). For example, (0.8/0.48) in the 5^th column of matrix 460 is equal to (1.0/0.6) in the 5^th column of matrix 410.

[0087] As shown in FIG. 4B, after applying a gain factor (e.g., gain = 1.25) to the I and Q samples in the matrix 460, the resulting gained I and Q samples in the matrix 470 may be used as the DAC’s input, resulting in a 2 dB output power gain. At block 812A, a gain factor is applied to the real and imaginary signals. The gain factor may be applied using the DAC or via logic implemented prior to the DAC. At block 814A, the processor verifies that the EVM satisfies a predetermined criteria (e.g., is below a predetermined EVM threshold, which may be based on a target/desired constellation).

[0088] FIG. 8B illustrates a flowchart of an example method 800B for performing CFR to adjust the output power of a DAC (e.g., DAC 506), according to certain aspects of the present disclosure. Method 800B may be performed, for example, by a processor (e.g., processor 502). Method 800B is similar to method 800A, except that the imaginary component samples in method 800B are modified before the real component samples in method 800B, as described below.

[0089] Method 800B may enter at block 802B, where the processor determines a first threshold (e.g., Threshold) and a second threshold (e.g., Qthreshoid), based on the digital input signal. For example, at least one of the first threshold or the second threshold may be based or set on a target gain of the DAC.

[0090] Blocks 804B and 806B may be performed for each imaginary signal sample having a higher amplitude value than the second threshold. At block 804B, the processor reduces the amplitude value of the imaginary signal sample to the second threshold. At block 806B, the processor reduces the amplitude value of the real signal sample, corresponding in time to the imaginary signal sample, by an amount that is based on a ratio of the amplitude value of the real signal sample to the amplitude value of the imaginary signal sample. [0091] Blocks 808B and 81 OB may be performed for each real signal sample having a higher amplitude value than the first threshold. At block 808B, the processor reduces the amplitude value of the real signal sample to the first threshold. At block 81 OB, the processor reduces the amplitude value of the imaginary signal sample, corresponding in time to the real signal sample, by an amount that is based on a ratio of the amplitude value of the real signal sample to the amplitude value of the imaginary signal sample. At block 812B, a gain factor is applied to the real and imaginary signals. The gain factor may be applied using the DAC or via logic implemented prior to the DAC. At block 814B, the processor verifies that the EVM satisfies a predetermined criteria (e.g., is below a predetermined EVM threshold, which may be based on a target/desired constellation).

Example Aspects

[0092] In addition to the various aspects described above, specific combinations of aspects are within the scope of the present disclosure, some of which are detailed below:

[0093] Aspect 1 : A method for wireless communications, comprising: applying a crest factor reduction to a digital input signal to generate a crest factor reduced signal, comprising: adjusting an amplitude of a real component of the digital input signal, based on a first threshold, while maintaining a phase of the digital input signal; and adjusting an amplitude of an imaginary component of the digital input signal, based on a second threshold, while maintaining the phase of the digital input signal; and converting the crest factor reduced signal to an analog signal via a digital-to-analog converter (DAC).

[0094] Aspect 2: The method of Aspect 1, wherein at least one of the first threshold or the second threshold is based on a target gain of the DAC.

[0095] Aspect 3: The method of Aspect 2, wherein the converting comprises: applying a gain factor to the crest factor reduced signal with the DAC according to the target gain to generate a gained signal; and converting the gained signal to the analog signal using the DAC.

[0096] Aspect 4: The method of any of Aspects 1 to 3, wherein adjusting the amplitude of the real component of the digital input signal while maintaining the phase of the digital input signal comprises: for each sample of the real component of the digital input signal having an amplitude value greater than the first threshold: reducing the amplitude value of the sample of the real component to the first threshold; and reducing an amplitude value of a sample of the imaginary component of the digital input signal, corresponding in time to the sample of the real component, by an amount that is based on a ratio of the amplitude value of the sample of the real component to the amplitude value of the sample of the imaginary component.

[0097] Aspect 5 : The method of Aspect 4, wherein reducing the amplitude value of the sample of the imaginary component comprises reducing the amplitude value of the sample of the imaginary component to a reduced amplitude value that is equal to the first threshold divided by the ratio of the amplitude value of the sample of the real component to the amplitude value of the sample of the imaginary component.

[0098] Aspect 6: The method of any of Aspects 4 to 5, wherein: the amplitude of the imaginary component of the digital input signal is adjusted after the amplitude of the real component of the digital input signal is adjusted; and adjusting the amplitude of the imaginary component of the digital input signal comprises: for each sample of the imaginary component of the digital input signal having an amplitude value greater than the second threshold: reducing the amplitude value of the sample of the imaginary component to the second threshold; and reducing an amplitude value of the sample of the real component of the digital input signal, corresponding in time to the sample of the imaginary component, by an amount that is based on the ratio of the amplitude value of the sample of the real component to the amplitude value of the sample of the imaginary component.

[0099] Aspect 7 : The method of Aspect 6, wherein reducing the amplitude value of the sample of the real component comprises reducing the amplitude value of the sample of the real component to a reduced amplitude value that is equal to the second threshold multiplied by the ratio of the amplitude value of the sample of the real component to the amplitude value of the imaginary component.

[0100] Aspect 8: The method of any of Aspects 1 to 4, wherein adjusting the amplitude of the imaginary component of the digital input signal while maintaining the phase of the digital input signal comprises: for each sample of the imaginary component of the digital input signal having an amplitude value greater than the second threshold: reducing the amplitude value of the sample of the imaginary component to the second threshold; and reducing an amplitude value of a sample of the real component of the digital input signal, corresponding in time to the sample of the imaginary component, by an amount that is based on a ratio of the amplitude value of the sample of the real component to the amplitude value of the sample of the imaginary component.

[0101] Aspect 9: The method of Aspect 8, wherein: the amplitude of the real component of the digital input signal is adjusted after the amplitude of the imaginary component of the digital input signal is adjusted; and adjusting the amplitude of the real component of the digital input signal comprises: for each sample of the real component of the digital input signal having an amplitude value greater than the first threshold: reducing the amplitude value of the sample of the real component to the first threshold; and reducing an amplitude value of the sample of the imaginary component of the digital input signal, corresponding in time to the sample of the real component, by an amount that is based on the ratio of the amplitude value of the sample of the real component to the amplitude value of the sample of the imaginary component.

[0102] Aspect 10: The method of any of Aspects 1 to 9, further comprising: applying another crest factor reduction to the analog signal or a signal-processed version of the analog signal to generate another crest factor reduced signal, comprising adjusting an amplitude of the analog signal or the signal-processed version of the analog signal based on a third threshold, while maintaining a phase of the analog signal; and amplifying the other crest factor reduced signal via an amplifier.

[0103] Aspect 11 : The method of Aspect 10, wherein the other crest factor reduction comprises polar clipping crest factor reduction.

[0104] Aspect 12: The method of any of Aspects 10 to 11, further comprising applying another crest factor reduction to a signal to generate the digital input signal, before applying the crest factor reduction to the digital input signal.

[0105] Aspect 13: The method of Aspect 12, wherein the other crest factor reduction comprises polar clipping crest factor reduction.

[0106] Aspect 14: The method of any of Aspects 1 to 13, further comprising: combining a real component of the analog signal and an imaginary component of the analog signal to generate a combined signal; and upconverting the combined signal one or more times to generate a signal having a frequency for transmission in a range from 90 gigahertz (GHz) to 300 GHz.

[0107] Aspect 15: The method of any of Aspects 1 to 14, wherein the amplitude of the real component of the digital input signal is adjusted after the amplitude of the imaginary component of the digital input signal is adjusted.

[0108] Aspect 16: The method of any of Aspects 1 to 15, wherein the first threshold is the same as the second threshold.

[0109] Aspect 17: The method of any of Aspects 1 to 16, wherein at least one of the first threshold or the second threshold is based on a peak-to-average-power ratio (PAPR) value or on an allowed input voltage of the DAC.

[0110] Aspect 18: An apparatus comprising: at least one processor; a digital -to- analog converter (DAC); and a memory coupled to the at least one processor and storing computer-executable instructions, which, when executed by the at least one processor, perform a method in accordance with any of Aspects 1-17.

[0111] Aspect 19: An apparatus comprising means for performing a method in accordance with any of Aspects 1-17.

[0112] Aspect 20: A non-transitory computer-readable medium comprising executable instructions that, when executed by a processor of an apparatus, cause the apparatus to perform a method in accordance with any of Aspects 1-17.

[0113] Aspect 21 : A computer program product embodied on a computer-readable storage medium comprising code for performing a method in accordance with any of Aspects 1-17.

Conclusion

[0114] Described herein is an improved CFR technique to increase the output power of a DAC, while maintaining the signal phase. The improved CFR technique separately reduces the PAPR of the real and imaginary components of a complex digital input signal while maintaining the phase of the complex signal. By performing the improved CFR technique described herein, a transmitter can increase (e.g., maximize) the DAC’s output power, reduce the ratio between the DAC’s ENOB and signal power, increase baseband output power, and increase throughput, compared to conventional CFR techniques.

[0115] The above description provides examples, and is not limiting of the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements discussed without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For instance, the methods described may be performed in an order different from that described, and various steps may be added, omitted, or combined. Also, features described with respect to some examples may be combined in some other examples. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to, or other than, the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0116] The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application-specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components. For example, means for applying a crest factor reduction to a digital input signal may include, for example, one or more processors (e.g., controller 336, processor 502). Means for adjusting an amplitude may include, for example, one or more processors (e.g., controller 336, processor 502). Means for converting the crest factor reduced signal to an analog signal may include, for example, a DAC (e.g., DAC 506).

[0117] As used herein, a phrase referring to “at least one of’ a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b. or c” is intended to cover: a, b. c, a-b. a-c, b-c. and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b. a-a-c, a-b-b. a- c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b. and c).

[0118] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

[0119] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes, and variations may be made in the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A method for wireless communications, comprising: applying a crest factor reduction to a digital input signal to generate a crest factor reduced signal, comprising: adjusting an amplitude of a real component of the digital input signal, based on a first threshold, while maintaining a phase of the digital input signal; and adjusting an amplitude of an imaginary component of the digital input signal, based on a second threshold, while maintaining the phase of the digital input signal; and converting the crest factor reduced signal to an analog signal via a digital-to- analog converter (DAC).

2. The method of claim 1, wherein at least one of the first threshold or the second threshold is based on a target gain of the DAC.

3. The method of claim 2, wherein the converting comprises: applying a gain factor to the crest factor reduced signal with the DAC according to the target gain to generate a gained signal; and converting the gained signal to the analog signal using the DAC.

4. The method of claim 1, wherein adjusting the amplitude of the real component of the digital input signal while maintaining the phase of the digital input signal comprises: for each sample of the real component of the digital input signal having an amplitude value greater than the first threshold: reducing the amplitude value of the sample of the real component to the first threshold; and reducing an amplitude value of a sample of the imaginary component of the digital input signal, corresponding in time to the sample of the real component, by an amount that is based on a ratio of the amplitude value of the sample of the real component to the amplitude value of the sample of the imaginary component.

5. The method of claim 4, wherein reducing the amplitude value of the sample of the imaginary component comprises reducing the amplitude value of the sample of the imaginary component to a reduced amplitude value that is equal to the first threshold divided by the ratio of the amplitude value of the sample of the real component to the amplitude value of the sample of the imaginary component.

6. The method of claim 4, wherein: the amplitude of the imaginary component of the digital input signal is adjusted after the amplitude of the real component of the digital input signal is adjusted; and adjusting the amplitude of the imaginary component of the digital input signal comprises: for each sample of the imaginary component of the digital input signal having an amplitude value greater than the second threshold: reducing the amplitude value of the sample of the imaginary component to the second threshold; and reducing an amplitude value of the sample of the real component of the digital input signal, corresponding in time to the sample of the imaginary component, by an amount that is based on the ratio of the amplitude value of the sample of the real component to the amplitude value of the sample of the imaginary component.

7. The method of claim 6, wherein reducing the amplitude value of the sample of the real component comprises reducing the amplitude value of the sample of the real component to a reduced amplitude value that is equal to the second threshold multiplied by the ratio of the amplitude value of the sample of the real component to the amplitude value of the imaginary component.

8. The method of claim 1, wherein adjusting the amplitude of the imaginary component of the digital input signal while maintaining the phase of the digital input signal comprises: for each sample of the imaginary component of the digital input signal having an amplitude value greater than the second threshold: reducing the amplitude value of the sample of the imaginary component to the second threshold; and reducing an amplitude value of a sample of the real component of the digital input signal, corresponding in time to the sample of the imaginary component, by an amount that is based on a ratio of the amplitude value of the sample of the real component to the amplitude value of the sample of the imaginary component.

9. The method of claim 8, wherein: the amplitude of the real component of the digital input signal is adjusted after the amplitude of the imaginary component of the digital input signal is adjusted; and adjusting the amplitude of the real component of the digital input signal comprises: for each sample of the real component of the digital input signal having an amplitude value greater than the first threshold: reducing the amplitude value of the sample of the real component to the first threshold; and reducing an amplitude value of the sample of the imaginary component of the digital input signal, corresponding in time to the sample of the real component, by an amount that is based on the ratio of the amplitude value of the sample of the real component to the amplitude value of the sample of the imaginary component.

10. The method of claim 1, further comprising: applying another crest factor reduction to the analog signal or a signal-processed version of the analog signal to generate another crest factor reduced signal, comprising adjusting an amplitude of the analog signal or the signal-processed version of the analog signal based on a third threshold, while maintaining a phase of the analog signal; and amplifying the other crest factor reduced signal via an amplifier.

11. The method of claim 10, wherein the other crest factor reduction comprises polar clipping crest factor reduction.

12. The method of claim 1, further comprising applying another crest factor reduction to a signal to generate the digital input signal, before applying the crest factor reduction to the digital input signal.

13. The method of claim 12, wherein the other crest factor reduction comprises polar clipping crest factor reduction.

14. The method of claim 1, further comprising: combining a real component of the analog signal and an imaginary component of the analog signal to generate a combined signal; and upconverting the combined signal one or more times to generate a signal having a frequency for transmission in a range from 90 gigahertz (GHz) to 300 GHz.

15. The method of claim 1 , wherein the amplitude of the real component of the digital input signal is adjusted after the amplitude of the imaginary component of the digital input signal is adjusted.

16. The method of claim 1, wherein the first threshold is the same as the second threshold.

17. The method of claim 1, wherein at least one of the first threshold or the second threshold is based on a peak-to-average-power ratio (PAPR) value or on an allowed input voltage of the DAC.

18. An apparatus for wireless communication, comprising: at least one processor configured to apply a crest factor reduction to a digital input signal to generate a crest factor reduced signal, wherein in order to apply the crest factor reduction, the at least one processor is configured to: adjust an amplitude of a real component of the digital input signal, based on a first threshold, while maintaining a phase of the digital input signal; and adjust an amplitude of an imaginary component of the digital input signal, based on a second threshold, while maintaining the phase of the digital input signal; a digital -to-analog converter (D AC) configured to convert the crest factor reduced signal to an analog signal; and a memory coupled to the at least one processor.

19. The apparatus of claim 18, wherein: at least one of the first threshold or the second threshold is based on a target gain of the DAC; and in order to convert the crest factor reduced signal to the analog signal, the DAC is configured to: apply a gain factor to the crest factor reduced signal according to the target gain to generate a gained signal; and convert the gained signal to the analog signal.

20. An apparatus for wireless communication, comprising: means for applying a crest factor reduction to a digital input signal to generate a crest factor reduced signal, comprising: means for adjusting an amplitude of a real component of the digital input signal, based on a first threshold, while maintaining a phase of the digital input signal; and means for adjusting an amplitude of an imaginary component of the digital input signal, based on a second threshold, while maintaining the phase of the digital input signal; and means for converting the crest factor reduced signal to an analog signal.