EP4681515A1

EP4681515A1 - Array substrate and display apparatus

Info

Publication number: EP4681515A1
Application number: EP23958606.8A
Authority: EP
Inventors: Cong FAN; Wei Zhang; Guanghua Xu; Hongli Wang
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2023-11-17
Filing date: 2023-11-17
Publication date: 2026-01-21
Also published as: WO2025102332A1; CN120345393A; WO2025102332A9; EP4681515A4

Abstract

An array substrate is provided. The array substrate includes a planarization layer; a partition layer on the planarization layer; an anode layer on a side of the partition layer away from the planarization layer; a pixel definition layer on a side of the anode layer away from the planarization layer; a spacer layer on a side of the pixel definition layer away from the planarization layer; and a plurality of partition grooves extending through the pixel definition layer. An orthographic projection of the partition layer on a base substrate at least partially overlaps with an orthographic projection of the anode layer on the base substrate. The orthographic projection of the partition layer on the base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of a respective partition groove of the plurality of partition grooves on the base substrate.

Description

ARRAY SUBSTRATE AND DISPLAY APPARATUS

TECHNICAL FIELD

The present invention relates to display technology, more particularly, to an array substrate and a display apparatus.

BACKGROUND

Organic Light Emitting Diode (OLED) display is one of the hotspots in the field of flat panel display research today. OLED is driven by a driving current required to be kept constant to control illumination. The OLED display panel includes a plurality of pixel units configured with pixel-driving circuits arranged in multiple rows and columns.

SUMMARY

In one aspect, the present disclosure provides an array substrate, comprising a planarization layer; a partition layer on the planarization layer; an anode layer on a side of the partition layer away from the planarization layer; a pixel definition layer on a side of the anode layer away from the planarization layer; a spacer layer on a side of the pixel definition layer away from the planarization layer; and a plurality of partition grooves extending through the pixel definition layer; wherein an orthographic projection of the partition layer on a base substrate at least partially overlaps with an orthographic projection of the anode layer on the base substrate; and the orthographic projection of the partition layer on the base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of a respective partition groove of the plurality of partition grooves on the base substrate.
Optionally, the orthographic projection of the partition layer on the base substrate covers at least 20%, and is non-overlapping with at least 20%, of the orthographic projection of the respective partition groove of the plurality of partition grooves on the base substrate.
Optionally, the partition layer comprises a plurality of partition blocks; wherein an orthographic projection of a respective partition block of the plurality of partition blocks on the base substrate at least partially overlaps with an orthographic projection of a respective anode of a respective subpixel on the base substrate.
Optionally, the partition layer further comprises a plurality of bridges connecting multiple partition blocks of the plurality of partition blocks; wherein an orthographic projection of a respective bridge of the plurality of bridges on the base substrate is at least partially non-overlapping with the orthographic projection of the respective anode of a respective subpixel on the base substrate.
Optionally, an orthographic projection of a partition block in at least one subpixel on the base substrate is non-overlapping with an orthographic projection of any of the plurality of partition grooves on the base substrate; and an orthographic projection of a partition block in one or more subpixels on the base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves on the base substrate.
Optionally, a respective spacer of the spacer layer is in a region between four adjacent subpixels; and an orthographic projection of the respective spacer on the base substrate is partially surrounded by orthographic projections of one or more second partition grooves, one or more third partition grooves, and one or more fourth partition grooves on the base substrate.
Optionally, a cross-section of a respective spacer of the spacer layer along a plane parallel to a surface of the planarization layer has a maximum width; and a minimum distance between two adjacent subpixel apertures of two adjacent subpixels is greater than the maximum width.
Optionally, a cross-section of a respective spacer of the spacer layer along a plane parallel to a surface of the planarization layer has a maximum width; and a sum of the maximum width and two times a minimum distance between a respective spacer of the spacer layer and an adjacent partition groove is less than the minimum distance between two adjacent subpixel apertures of two adjacent subpixels, and greater than one half of the minimum distance between two adjacent subpixel apertures of two adjacent subpixels.
Optionally, an orthographic projection of a respective spacer of the spacer layer on the base substrate is substantially non-overlapping with an orthographic projection of the partition layer on the base substrate.
Optionally, an orthographic projection of a respective spacer of the spacer layer on the base substrate at least partially overlaps with an orthographic projection of the partition layer on the base substrate.
Optionally, an orthographic projection of a respective spacer of the spacer layer on the base substrate at least partially overlaps with an orthographic projection of a respective bridge of a plurality of bridges on the base substrate.
Optionally, an anode of at least one subpixel comprises a first connecting portion connected to a transistor through a first via extending through the planarization layer; an anode of at least another subpixel comprises a second connecting portion connected to a transistor through a second via extending through the planarization layer; an orthographic projection of the respective spacer on the base substrate is spaced apart from an orthographic projection of the first connecting portion on the base substrate by a first distance; an orthographic projection of the respective spacer on the base substrate is spaced apart from an orthographic projection of the second connecting portion on the base substrate by a second distance; the first distance is equal to or greater than 1.0 μm; and the second distance is equal to or greater than 1.0 μm.
Optionally, the array substrate further comprises a plurality of light emitting layers on a side of the anode layer away from the planarization layer; wherein a respective light emitting layer of the plurality of light emitting layers is at least partially in a respective subpixel aperture of a plurality of subpixel apertures; and an orthographic projection of a respective spacer of the spacer layer on the base substrate is at least partially surrounded by orthographic projections of four adjacent subpixels on the base substrate.
Optionally, the array substrate further comprises a notch recessing into the first light emitting layer; wherein an orthographic projection of the respective spacer on the base substrate is substantially non-overlapping with orthographic projections of the first light emitting layer, the second light emitting layer, the third light emitting layer, and the fourth light emitting layer on the base substrate.
Optionally, a minimum distance between the respective spacer and the edge of the first light emitting layer is equal to or greater than one third of a minimum distance between the respective spacer and an adjacent partition groove.
Optionally, a respective spacer of the spacer layer is in a region between six adjacent subpixels; and an orthographic projection of the respective spacer on the base substrate is partially surrounded by orthographic projections of one or more first partition grooves, one or more second partition grooves, and one or more third partition grooves on the base substrate.
Optionally, in a region outside the plurality of partition grooves, the planarization layer has a first thickness; in a region having a respective partition groove of the plurality of partition grooves, the planarization layer has a second thickness; the second thickness is less than the first thickness; and an edge of a portion of the partition layer partially extends into the respective partition groove.
Optionally, the array substrate comprises a partition structure; wherein the partition structure comprises a portion of the planarization layer; a portion of the partition layer on the portion of the planarization layer; and a recess recessing into portion of the planarization layer underneath an edge portion of the partition layer.
Optionally, a portion of the pixel definition layer on the partition layer and between a partition groove of the plurality of partition grooves and a subpixel aperture of the plurality of subpixel apertures has a first slope angle on a side abutting the partition groove and a second slope angle on a side abutting the subpixel aperture; and the first slope angle is different from the second slope angle.
In another aspect, the present disclosure provides an array substrate, comprising a planarization layer; an anode layer on the planarization layer; a pixel definition layer on a side of the anode layer away from the planarization layer; a partition layer on a side of the pixel definition layer away from the planarization layer; a spacer layer on a side of the pixel definition layer away from the planarization layer; and a plurality of partition grooves; wherein the partition layer comprises a plurality of partition blocks; a respective partition block of the plurality of partition blocks is limited in a partition groove of the plurality of partition grooves; an orthographic projection of the plurality of partition blocks on a base substrate is non-overlapping with an orthographic projection of the anode layer on the base substrate; and the orthographic projection of the anode layer on the base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of a respective partition groove of the plurality of partition grooves on the base substrate.
In another aspect, the present disclosure provides a display apparatus, comprising the array substrate described herein or fabricated by a method described herein, and one or more integrated circuits connected to the array substrate.
BRIEF DESCRIPTION OF THE FIGURES
The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present invention.
FIG. 1 illustrates subpixel crosstalk in a related array substrate.
FIG. 2 illustrates a low grayscale image displayed by subpixels of a same color in an array substrate having a partition structure in some embodiments according to the present disclosure.
FIG. 3 is a schematic diagram illustrating the structure of a single organic light emitting diode.
FIG. 4 is a schematic diagram illustrating the structure of a tandem organic light emitting diode.
FIG. 5A to FIG. 5F illustrate a process of fabricating an array substrate in some embodiments according to the present disclosure.
FIG. 6 is a focus ion beam image of a cross-section of a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 7A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 7B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 7C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 7D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 7E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 7F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 8A is a cross-sectional view along an A-A’ line in FIG. 7A.
FIG. 8B is a cross-sectional view of a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 9 is a cross-sectional view along an A-A’ line in FIG. 7A when a charge generation layer and a cathode layer are formed in the array substrate.
FIG. 10A is a schematic diagram illustrating the structure of a partition layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 10B is a schematic diagram illustrating the structure of an anode layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 10C is a schematic diagram illustrating the structure of an anode layer and a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 11 is a zoom-in view of a portion of an array substrate depicted in FIG. 7A.
FIG. 12 is a zoom-in view of a portion of an array substrate depicted in FIG. 11.
FIG. 13A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 13B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 13C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 13D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 13E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 13F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 14 is a cross-sectional view along a B-B’ line in FIG. 13A.
FIG. 15 is a cross-sectional view along a B-B’ line in FIG. 13A when a charge generation layer and a cathode layer are formed in the array substrate.
FIG. 16A is a schematic diagram illustrating the structure of a partition layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 16B is a schematic diagram illustrating the structure of an anode layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 16C is a schematic diagram illustrating the structure of an anode layer and a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 17 is a zoom-in view of a portion of an array substrate depicted in FIG. 13A.
FIG. 18 is a zoom-in view of a portion of an array substrate depicted in FIG. 17.
FIG. 19A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 19B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 19C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 19D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 19E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 19F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 20 is a cross-sectional view along a C-C’ line in FIG. 19A.
FIG. 21 is a cross-sectional view along a C-C’ line in FIG. 19A when a charge generation layer and a cathode layer are formed in the array substrate.
FIG. 22A is a schematic diagram illustrating the structure of a partition layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 22B is a schematic diagram illustrating the structure of an anode layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 22C is a schematic diagram illustrating the structure of an anode layer and a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 23A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 23B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 23C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 23D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 23E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 23F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 23G is a schematic diagram illustrating the structure of light emitting layers in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 24 is a cross-sectional view along a D-D’ line in FIG. 23A.
FIG. 25A is a schematic diagram illustrating the structure of a partition layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 25B is a schematic diagram illustrating the structure of an anode layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 25C is a schematic diagram illustrating the structure of an anode layer and a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 26 is a zoom-in view of a portion of an array substrate depicted in FIG. 23A without showing a plurality of light emitting layers.
FIG. 27 is a zoom-in view of a portion of an array substrate depicted in FIG. 26 without showing a plurality of light emitting layers.
FIG. 28 illustrates a layout of a respective spacer relative to adjacent light emitting layers in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 29 is a schematic diagram illustrating the structure of a first light emitting layer in some embodiments according to the present disclosure.
FIG. 30 illustrates a relative position of a respective spacer with respect to a mask plate for depositing a first light emitting material in some embodiments according to the present disclosure.
FIG. 31A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 31B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 31C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 31D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 31E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 31F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 31G is a schematic diagram illustrating the structure of light emitting layers in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 32A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 32B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 32C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 32D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 32E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 32F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 33 is a cross-sectional view along a E-E’ line in FIG. 32A.
FIG. 34A is a schematic diagram illustrating the structure of a partition layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 34B is a schematic diagram illustrating the structure of an anode layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 34C is a schematic diagram illustrating the structure of an anode layer and a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 35 is a zoom-in view of a portion of an array substrate depicted in FIG. 32A.
FIG. 36A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 36B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 36C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 36D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 36E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 36F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 37A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 37B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 37C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 37D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 37E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 37F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 38 is a cross-sectional view along an F-F’ line in FIG. 37A.
FIG. 39 is a cross-sectional view along an F-F’ line in FIG. 37A when a charge generation layer and a cathode layer are formed in the array substrate.
FIG. 40A is a schematic diagram illustrating the structure of a partition layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 40B is a schematic diagram illustrating the structure of an anode layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 40C is a schematic diagram illustrating the structure of an anode layer and a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 41 is a zoom-in view of a portion of an array substrate depicted in FIG. 37A.
FIG. 42 is a zoom-in view of a portion of an array substrate depicted in FIG. 41.
FIG. 43A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 43B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 43C is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 43D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 43E is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 43F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure.
FIG. 44 is a cross-sectional view along a G-G’ line in FIG. 43A.
FIG. 45 is a zoom-in view of a portion of an array substrate depicted in FIG. 43A.
FIG. 46 is a zoom-in view of a portion of an array substrate depicted in FIG. 45.
FIG. 47 illustrates a detailed structure in a display area in an array substrate in some embodiments according to the present disclosure.

DETAILED DESCRIPTION

The disclosure will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of some embodiments are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
The present disclosure provides, inter alia, an array substrate and a display apparatus that substantially obviate one or more of the problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a planarization layer; a partition layer on the planarization layer; an anode layer on a side of the partition layer away from the planarization layer; a pixel definition layer on a side of the anode layer away from the planarization layer; a spacer layer on a side of the pixel definition layer away from the planarization layer; and a plurality of partition grooves extending through the pixel definition layer. Optionally, an orthographic projection of the partition layer on a base substrate at least partially overlaps with an orthographic projection of the anode layer on the base substrate. Optionally, the orthographic projection of the partition layer on the base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of a respective partition groove of the plurality of partition grooves on the base substrate.
To address pixel crosstalk issue, the inventors of the present disclosure discover a novel array substrate having a partition structure that can at least partially segregate common layers in the array substrate between adjacent subpixels. The inventors of the present disclosure discover that, surprisingly and unexpectedly, the partition structure can effectively prevent subpixel crosstalk, particularly noticeable when subpixels of a same color are displaying a low grayscale image. FIG. 1 illustrates subpixel crosstalk in a related array substrate. The related array substrate lacks a partition structure according to the present disclosure. Referring to FIG. 1, the array substrate includes a plurality of subpixels, e.g., a plurality of subpixels of a same color. When displaying a low grayscale image, subpixel crosstalk CT is observed because the common layer in the array substrate is not sufficiently segregated between adjacent subpixels.
FIG. 2 illustrates a low grayscale image displayed by subpixels of a same color in an array substrate having a partition structure in some embodiments according to the present disclosure. As shown in FIG. 2, by having the partition structure, subpixel crosstalk between adjacent subpixels in the array substrate is significantly reduced.
The inventors of the present disclosure discover that the partition structure is particularly effective in a tandem organic light emitting diode display panel. FIG. 3 is a schematic diagram illustrating the structure of a single organic light emitting diode. Referring to FIG. 3, the single organic light emitting diode in some embodiments includes a hole transport layer HTL, a light emitting layer EL on the hole transport layer HTL, a hole barrier layer HBL on a side of the light emitting layer EL away from the hole transport layer HTL, an electron transport layer ETL on a side of the hole barrier layer HBL away from the hole transport layer HTL, and a cathode CD on a side of the electron transport layer ETL away from the hole transport layer HTL.
FIG. 4 is a schematic diagram illustrating the structure of a tandem organic light emitting diode. Referring to FIG. 4, the tandem organic light emitting diode in some embodiments includes a first hole transport layer HTL1, a first light emitting layer EL1 on the first hole transport layer HTL1, a first hole barrier layer HBL1 on a side of the first light emitting layer EL1 away from the first hole transport layer HTL1, a N-type charge generation layer NCGL on a side of the first hole barrier layer HBL1 away from the first hole transport layer HTL1, a P-type charge generation layer PCGL on a side of the N-type charge generation layer NCGL away from the first hole transport layer HTL1, a second hole transport layer HTL2 on a side of the P-type charge generation layer PCGL away from the first hole transport layer HTL1, a second light emitting layer EL2 on a side of the second hole transport layer HTL2 away from the first hole transport layer HTL1, a second hole barrier layer HBL2 on a side of the second light emitting layer EL2 away from the first hole transport layer HTL1, an electron transport layer ETL on a side of the second hole barrier layer HBL2 away from the first hole transport layer HTL1, and a cathode CD on a side of the electron transport layer ETL away from the first hole transport layer HTL1.
Referring to FIG. 4, common layers in the tandem organic light emitting diode includes one or more charge generation layers (e.g., the P-type charge generation layer PCGL and the N-type charge generation layer NCGL) , one or more hole transport layers (e.g., the first hole transport layer HTL1 and the second hole transport layer HTL2) , one or more hole barrier layers (e.g., the first hole barrier layer HBL1 and the second hole barrier layer HBL2) , and the electron transport layer ETL. The inventors of the present disclosure discover that the tandem organic light emitting diode display panel is particularly prone to the subpixel crosstalk defect due to the presence of the one or more charge generation layers, and the partition structure is particularly effective in a tandem organic light emitting diode display panel.
The inventors of the present disclosure further discover that the partition structure occupies a large portion of the space between adjacent light emitting diodes, greatly limiting the space available for the placement of the spacer for supporting a fine metal mask. The inventors of the present disclosure discover that, surprisingly and unexpectedly, the unique structure of the present array substrate ensures the spacer can be properly positioned with the necessary gap between the spacer and the partition structure. The spacer in the present array substrate can effectively maintain the support function of the spacer for the fine metal mask, preventing light emitting materials in the subpixel region from being scraped by the fine metal mask, effectively preventing color mixing or an increased occurrence of dark spots.
FIG. 5A to FIG. 5F illustrate a process of fabricating an array substrate in some embodiments according to the present disclosure. Referring to FIG. 5A, a planarization material layer PLM is formed on a transistor plate TP. The transistor plate TP includes a plurality of pixel driving circuits configured to drive light emission in a plurality of light emitting elements. A respective pixel driving circuit includes a plurality of transistors and one or more capacitors.
Referring to FIG. 5B, a partition material layer PML is formed on a side of the planarization material layer PLM away from the transistor plate TP. Various appropriate materials and various appropriate fabricating methods may be used to make the partition material layer PML. For example, an insulating material may be deposited by a plasma-enhanced chemical vapor deposition (PECVD) process or a sputtering process, e.g., a magnetron sputtering process. Examples of insulating materials suitable for making the partition material layer PML include, but are not limited to, silicon oxide (SiOy) , silicon nitride (SiNy, e.g., Si₃N₄) , silicon oxynitride (SiO_xN_y) .
Referring to FIG. 5C, the partition material layer PML is etched to form a partition layer PL. The etching process also removes a portion of the planarization material layer that is not covered by the mask plate, thereby forming a planarization layer PLN. The partition layer PL has an undercut profile. Along a plane perpendicular to a surface of the transistor plate TP and intersecting the partition layer PL, the planarization layer PLN, and the transistor plate TP, a portion of the partition layer PL between two adjacent grooves resulting from the etching process has a first width on a first side and a second width on a second side, the first side and the second side being opposite to each other. The first side is on a side of the second side away from the transistor plate TP. Optionally, the second side is in contact with the planarization layer PLN. Optionally, the first width is greater than the second width.
In some embodiments, the portion of the partition layer PL and a portion of the planarization layer PLN between two adjacent grooves resulting from the etching process constitute a partition structure PS. The portion of the planarization layer PLN between two adjacent grooves resulting from the etching process has a first thickness, and a portion of the planarization layer PLN in a region corresponding to the two adjacent grooves resulting from the etching process has a second thickness. Optionally, the first thickness is greater than the second thickness.
The inventors of the present disclosure discover that, by having the partition structure PS, one or more common layers (e.g., one or more charge generation layers) deposited on the substrate can be at least partially segregated by the partition structure PS, subpixel crosstalk between adjacent subpixels in the array substrate is significantly reduced.
Referring to FIG. 5D, an anode layer ADL comprising an anode of a light emitting element is formed on a side of the partition layer PL away from the transistor plate TP. Optionally, the anode AD is in direct contact with the partition layer PL. Optionally, an orthographic projection of the partition layer PL on a base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) an orthographic projection of the anode layer ADL on the base substrate.
Referring to FIG. 5E, a pixel definition layer PDL is formed on a side of the anode layer ADL away from the transistor plate TP. Referring to FIG. 5F, a spacer layer SPL is formed on a side of a portion of the pixel definition layer PDL away from the transistor plate TP. In the example depicted in FIG. 5F, a spacer of the spacer layer SPL is formed on the portion of the pixel definition layer PDL in a region between two adjacent anodes on a portion of the partition layer PL.
The inventors of the present disclosure discover that the portion of the pixel definition layer PDL on the portion of the partition layer PL often has an uneven thickness due to its close proximity to an edge of the partition layer PL. As a result, the spacer layer SPL on the portion of the pixel definition layer PDL has an uneven morphology. FIG. 6 is a focus ion beam image of a cross-section of a portion of an array substrate in some embodiments according to the present disclosure. Referring to FIG. 6, due to the uneven thickness of the portion of the pixel definition layer PDL, the spacer layer SPL on the portion of the pixel definition layer PDL has an uneven morphology. For example, in the cross-section, the spacer layer SPL has a first slope angle of θ1 on a first side, and a second slope angle of θ2 on a second side, the first slope angle of θ1 and the second slope angle of θ2 being different from each other. In one particular example, the first slope angle of θ1 is 25 degrees, and the second slope angle of θ2 is 15 degrees. The inventors of the present disclosure discover that this uneven morphology of the spacer layer SPL results in defects such as dark spots when the array substrate is configured to display an image. The inventors of the present disclosure discover that the array substrate discussed in the present disclosure obviates these defects.
FIG. 7A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure. FIG. 7B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 7C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 7D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 7E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 7F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 8A is a cross-sectional view along an A-A’ line in FIG. 7A. FIG. 9 is a cross-sectional view along an A-A’ line in FIG. 7A when a charge generation layer and a cathode layer are formed in the array substrate.
Referring to FIG. 7A to FIG. 7F, FIG. 8A, and FIG. 9, the array substrate in some embodiments includes a planarization layer PLN, a partition layer PL on the planarization layer PLN, an anode layer ADL on a side of the partition layer PL away from the planarization layer PLN, a pixel definition layer PDL on a side of the anode layer ADL away from the planarization layer PLN, and a spacer layer SPL on a side of the pixel definition layer PDL away from the planarization layer PLN. The array substrate in some embodiments further includes a plurality of subpixel apertures SA extending through the pixel definition layer PDL. The array substrate further includes a light emitting layer EL at least partially in a respective subpixel aperture of the plurality of subpixel apertures.
The array substrate in some embodiments further includes a plurality of partition grooves PG. In a region outside the plurality of partition grooves PG, the planarization layer PLN has a first thickness t1. In a region having the respective partition groove of the plurality of partition grooves PG, the planarization layer PLN has a second thickness t2. The second thickness t2 is less than the first thickness t1. In some embodiments, an edge of a portion of the partition layer PL partially extends into a respective partition groove of the plurality of partition grooves PG.
In some embodiments, the array substrate includes a partition structure PS. The partition structure PS includes a portion of the planarization layer PLN and a portion of the partition layer PL on the portion of the planarization layer PLN. The partition structure PS in some embodiments further includes a recess RS recessing into portion of the planarization layer PLN underneath an edge portion of the partition layer PL.
When one or more common layers (e.g., a charge generation layer CGL and a cathode layer CD) are deposited on the substrate, the one or more common layers are at least partially segregated by the partition structure PS. In some embodiments, the array substrate further includes one or more residual common layers (e.g., a residual charge generation layer RCGL and a residual cathode layer RCD) in a respective partition groove of the plurality of partition grooves PG. The inventors of the present disclosure discover that, by having the partition structure PS, subpixel crosstalk between adjacent subpixels in the array substrate is significantly reduced.
FIG. 8B is a cross-sectional view of a portion of an array substrate in some embodiments according to the present disclosure. Referring to FIG. 8B, in some embodiments, a portion of the pixel definition layer PDL on the partition layer PL and between a partition groove of the plurality of partition grooves PG and a subpixel aperture of the plurality of subpixel apertures SA has a first slope angle α1 on a side abutting the partition groove and a second slope angle α2 on a side abutting the subpixel aperture. Optionally, the first slope angle α1 is different from the second slope angle α2. Optionally, the second slope angle α2 is greater than the first slope angle α1.
FIG. 10A is a schematic diagram illustrating the structure of a partition layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 10B is a schematic diagram illustrating the structure of an anode layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 10C is a schematic diagram illustrating the structure of an anode layer and a partition layer in a portion of an array substrate in some embodiments according to the present disclosure. Referring to FIG. 7A to 7F, FIG. 8A, FIG. 9, and FIG. 10A to FIG. 10C, in some embodiments, an orthographic projection of the partition layer PL on a base substrate at least partially overlaps with an orthographic projection of the anode layer ADL on the base substrate. Optionally, the orthographic projection of the partition layer PL on the base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) the orthographic projection of the anode layer ADL on the base substrate.
In some embodiments, an orthographic projection of the partition layer PL on a base substrate at least partially overlaps with an orthographic projection of the light emitting layer EL on the base substrate.
In some embodiments, an orthographic projection of the partition layer PL on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of a respective partition groove of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition layer PL on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the respective partition groove of the plurality of partition grooves PG on the base substrate.
In some embodiments, the partition layer PL includes a plurality of partition blocks PB and a plurality of bridges Br connecting multiple partition blocks of the plurality of partition blocks PB. In some embodiments, an orthographic projection of a respective partition block of the plurality of partition blocks PB on a base substrate at least partially overlaps with an orthographic projection of a respective anode of a respective subpixel on the base substrate. Optionally, the orthographic projection of the respective partition block on the base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) the orthographic projection of the respective anode of the respective subpixel on the base substrate.
In some embodiments, an orthographic projection of a respective bridge of the plurality of bridges Br on a base substrate is at least partially non-overlapping with an orthographic projection of a respective anode of a respective subpixel on the base substrate. Optionally, the orthographic projection of the respective bridge on the base substrate is substantially non-overlapping with (e.g., at least 70%non-overlapping with, at least 75%non-overlapping with, at least 80%non-overlapping with, at least 85%non-overlapping with, at least 90%non-overlapping with, at least 95%non-overlapping with, at least 99%non-overlapping with, or completely non-overlapping with) the orthographic projection of the respective anode of the respective subpixel on the base substrate.
In some embodiments, the plurality of partition blocks PB and the plurality of bridges Br are parts of a unitary structure.
In some embodiments, the array substrate includes a plurality of first subpixels Sp1. Optionally, the plurality of first subpixels Sp1 are subpixels of a first color, e.g., a blue color. In some embodiments, an orthographic projection of a partition block in a respective first subpixel of the plurality of first subpixels Sp1 on a base substrate is non-overlapping with an orthographic projection of any of the plurality of partition grooves PG on the base substrate.
In some embodiments, the array substrate includes a plurality of second subpixels Sp2. Optionally, the plurality of second subpixels Sp2 are subpixels of a second color, e.g., a red color. In some embodiments, an orthographic projection of a partition block in a respective second subpixel of the plurality of second subpixels Sp2 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective second subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20%(e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds an orthographic projection of an anode in the respective second subpixel on the base substrate. In one particular example, the orthographic projection of the partition block in the respective second subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of an orthographic projection of edges of four partition grooves of the plurality of partition grooves PG on the base substrate. In another example, the orthographic projection of the edges of the four partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds the orthographic projection of the anode in the respective second subpixel on the base substrate, for example, on four sides of the orthographic projection of the anode in the respective second subpixel on the base substrate, respectively.
In some embodiments, the array substrate includes a plurality of third subpixels Sp3. Optionally, the plurality of third subpixels Sp3 are subpixels of a third color, e.g., a green color. In some embodiments, an orthographic projection of a partition block in a respective third subpixel of the plurality of third subpixels Sp3 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective third subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds an orthographic projection of an anode in the respective third subpixel on the base substrate. In one particular example, the orthographic projection of the partition block in the respective third subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of an orthographic projection of edges of two partition grooves of the plurality of partition grooves PG on the base substrate. In another example, the orthographic projection of the edges of the two partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds the orthographic projection of the anode in the respective third subpixel on the base substrate, for example, on two sides of the orthographic projection of the anode in the respective third subpixel on the base substrate, respectively.
In some embodiments, the array substrate includes a plurality of fourth subpixels Sp4. Optionally, the plurality of fourth subpixels Sp4 are subpixels of a third color, e.g., a green color. In some embodiments, an orthographic projection of a partition block in a respective fourth subpixel of the plurality of fourth subpixels Sp4 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective fourth subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds an orthographic projection of an anode in the respective fourth subpixel on the base substrate. In one particular example, the orthographic projection of the partition block in the respective fourth subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of an orthographic projection of edges of two partition grooves of the plurality of partition grooves PG on the base substrate. In another example, the orthographic projection of the edges of the two partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds the orthographic projection of the anode in the respective fourth subpixel on the base substrate, for example, on two sides of the orthographic projection of the anode in the respective fourth subpixel on the base substrate, respectively.
FIG. 11 is a zoom-in view of a portion of an array substrate depicted in FIG. 7A. Referring to FIG. 7A to 7F, FIG. 8A, FIG. 9, FIG. 10A to FIG. 10C, and FIG. 11, in some embodiments, a respective spacer RS of the spacer layer SPL is in a region between a first subpixel of the plurality of first subpixels Sp1, a second subpixel of the plurality of second subpixels Sp2, a third subpixel of the plurality of third subpixels Sp3, and a fourth subpixel of the plurality of fourth subpixels Sp4. The first subpixel, the second subpixel, the third subpixel, and the fourth subpixel are adjacent to each other. Optionally, the respective spacer RS is spaced apart from the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. As discussed above, an orthographic projection of a partition block in a respective first subpixel of the plurality of first subpixels Sp1 on a base substrate is non-overlapping with an orthographic projection of any of the plurality of partition grooves PG on the base substrate.
FIG. 12 is a zoom-in view of a portion of an array substrate depicted in FIG. 11. Referring to FIG. 7A to 7F, FIG. 8A, FIG. 9, FIG. 10A to FIG. 10C, FIG. 11, and FIG. 12, in some embodiments, an orthographic projection of the respective spacer RS on a base substrate is partially surrounded by orthographic projections of one or more second partition grooves PG2, one or more third partition grooves PG3, and one or more fourth partition grooves PG4 on the base substrate. Optionally, the orthographic projection of the respective spacer RS on the base substrate is spaced apart from the orthographic projections of one or more second partition grooves PG2, one or more third partition grooves PG3, and one or more fourth partition grooves PG4 on the base substrate by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. Optionally, an orthographic projection of a partition block in the respective second subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more second partition grooves PG2 on the base substrate. Optionally, an orthographic projection of a partition block in the respective third subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more third partition grooves PG3 on the base substrate. Optionally, an orthographic projection of a partition block in the respective fourth subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more fourth partition grooves PG4 on the base substrate. In one example, the respective spacer RS is partially surrounded by two second partition grooves, one third partition groove, and one fourth partition groove.
In some embodiments, the respective spacer RS has a cylindrical shape. In some embodiments, a cross-section of the respective spacer RS along a plane parallel to a surface of the planarization layer PLN has a round shape, e.g., a circular shape or an elliptical shape. The inventors of the present disclosure discover that this particular structure of the respective spacer RS is conducive to saving space. In one particular example, the respective spacer RS has a diameter of 10 μm.
In some embodiments, an orthographic projection of the respective spacer RS on a base substrate is substantially non-overlapping with (e.g., at least 70%non-overlapping with, at least 75%non-overlapping with, at least 80%non-overlapping with, at least 85%non-overlapping with, at least 90%non-overlapping with, at least 95%non-overlapping with, at least 99%non-overlapping with, or completely non-overlapping with) an orthographic projection of the partition layer PL on the base substrate.
In some embodiments, a minimum distance between two adjacent subpixel apertures of two adjacent subpixels is denoted as dp. In some embodiments, the minimum distance dp is greater than 1.5 times of the diameter of the respective spacer RS and less than 2 times of the diameter of the respective spacer RS. In one particular example, the minimum distance dp is 19 μm.
In some embodiments, a minimum distance between the respective spacer RS and an adjacent partition groove is denoted as dm. In some embodiments, a sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than one half of the minimum distance dp. Optionally, the sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than two third of the minimum distance dp.
In some embodiments, the minimum distance dm is equal to or greater than one fifth of the diameter of the respective spacer RS. In one particular example, the minimum distance dm is equal to or greater than 2.0 μm. In another example, the diameter of the respective spacer RS is 10 μm.
In alternative embodiments, the minimum distance dm is equal to or less than 37.5%of the diameter of the respective spacer RS. In one particular example, the minimum distance dm is equal to or less than 3.0 μm. In another example, the diameter of the respective spacer RS is 8 μm.
FIG. 13A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure. FIG. 13B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 13C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 13D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 13E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 13F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 14 is a cross-sectional view along a B-B’ line in FIG. 13A. FIG. 15 is a cross-sectional view along a B-B’ line in FIG. 13A when a charge generation layer and a cathode layer are formed in the array substrate. FIG. 16A is a schematic diagram illustrating the structure of a partition layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 16B is a schematic diagram illustrating the structure of an anode layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 16C is a schematic diagram illustrating the structure of an anode layer and a partition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 17 is a zoom-in view of a portion of an array substrate depicted in FIG. 13A. FIG. 18 is a zoom-in view of a portion of an array substrate depicted in FIG. 17.
Referring to FIG. 13A to 13F, FIG. 14, FIG. 15, FIG. 16A to FIG. 16C, FIG. 17, and FIG. 18, in some embodiments, a respective spacer RS of the spacer layer SPL is in a region between a first subpixel of the plurality of first subpixels Sp1, a second subpixel of the plurality of second subpixels Sp2, a third subpixel of the plurality of third subpixels Sp3, and a fourth subpixel of the plurality of fourth subpixels Sp4. The first subpixel, the second subpixel, the third subpixel, and the fourth subpixel are adjacent to each other. Optionally, the respective spacer RS is spaced apart from the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. As discussed above, an orthographic projection of a partition block in a respective first subpixel of the plurality of first subpixels Sp1 on a base substrate is non-overlapping with an orthographic projection of any of the plurality of partition grooves PG on the base substrate.
In some embodiments, an orthographic projection of the respective spacer RS on a base substrate is partially surrounded by orthographic projections of one or more second partition grooves PG2, one or more third partition grooves PG3, and one or more fourth partition grooves PG4 on the base substrate. Optionally, the orthographic projection of the respective spacer RS on the base substrate is spaced apart from the orthographic projections of one or more second partition grooves PG2, one or more third partition grooves PG3, and one or more fourth partition grooves PG4 on the base substrate by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. Optionally, an orthographic projection of a partition block in the respective second subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more second partition grooves PG2 on the base substrate. Optionally, an orthographic projection of a partition block in the respective third subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more third partition grooves PG3 on the base substrate. Optionally, an orthographic projection of a partition block in the respective fourth subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more fourth partition grooves PG4 on the base substrate. In one example, the respective spacer RS is partially surrounded by two second partition grooves, one third partition groove, and one fourth partition groove.
In some embodiments, the respective spacer RS has a cylindrical shape. In some embodiments, a cross-section of the respective spacer RS along a plane parallel to a surface of the planarization layer PLN has a round shape, e.g., a circular shape or an elliptical shape. The inventors of the present disclosure discover that this particular structure of the respective spacer RS is conducive to saving space. In one particular example, the respective spacer RS has a diameter of 10 μm.
In some embodiments, an orthographic projection of the respective spacer RS on a base substrate at least partially overlaps with an orthographic projection of the partition layer PL on the base substrate. In some embodiments, the orthographic projection of the partition layer PL on the base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) the orthographic projection of the respective spacer RS on the base substrate. Optionally, the orthographic projection of the respective spacer RS on the base substrate at least partially overlaps with an orthographic projection of a respective bridge of a plurality of bridges on the base substrate. Optionally, the orthographic projection of the respective bridge of the plurality of bridges on the base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) the orthographic projection of the respective spacer RS on the base substrate.
In some embodiments, a first anode of the respective first subpixel includes a first connecting portion CP1 connected to a transistor through a first via v1 extending through the planarization layer PLN. A third anode of the respective third subpixel includes a second connecting portion CP2 connected to a transistor through a second via v2 extending through the planarization layer PLN. In some embodiments, an orthographic projection of the respective spacer RS on the base substrate is partially surrounded by orthographic projections of the first connecting portion CP1 and the second connecting portion CP2 on the base substrate. Optionally, the orthographic projection of the respective spacer RS on the base substrate is spaced apart from the orthographic projections of the first connecting portion CP1 and the second connecting portion CP2 on the base substrate by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. Optionally, orthographic projections of the first connecting portion CP1, the second connecting portion CP2, and the respective spacer RS on the base substrate are partially surrounded by orthographic projections of edges of the one or more second partition grooves PG2, the one or more third partition grooves PG3, and the one or more fourth partition grooves PG4 on the base substrate. Optionally, the orthographic projections of the first connecting portion CP1, the second connecting portion CP2, and the respective spacer RS on the base substrate are spaced apart from the orthographic projections of edges of the one or more second partition grooves PG2, the one or more third partition grooves PG3, and the one or more fourth partition grooves PG4 on the base substrate by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate.
In some embodiments, a minimum distance between two adjacent subpixel apertures of two adjacent subpixels is denoted as dp. In some embodiments, the minimum distance dp is greater than 1.5 times of the diameter of the respective spacer RS and less than 2 times of the diameter of the respective spacer RS. In one particular example, the minimum distance dp is 19 μm. In some embodiments, a minimum distance between the respective spacer RS and an adjacent partition groove is denoted as dm. In some embodiments, a sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than one half of the minimum distance dp. Optionally, the sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than two third of the minimum distance dp. In some embodiments, the minimum distance dm is equal to or greater than one fifth of the diameter of the respective spacer RS. In one particular example, the minimum distance dm is equal to or greater than 2.0 μm. In another example, the diameter of the respective spacer RS is 10 μm.
In alternative embodiments, a minimum distance between two adjacent subpixel apertures of two adjacent subpixels is denoted as dp. In some embodiments, the minimum distance dp is greater than 1.5 times of the diameter of the respective spacer RS and less than 2 times of the diameter of the respective spacer RS. In one particular example, the minimum distance dp is 13.5 μm. In some embodiments, a minimum distance between the respective spacer RS and an adjacent partition groove is denoted as dm. In some embodiments, a sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than one half of the minimum distance dp. Optionally, the sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than two third of the minimum distance dp. In some embodiments, the minimum distance dm is equal to or greater than one fifth of the diameter of the respective spacer RS. In one particular example, the minimum distance dm is equal to or greater than 2.0 μm. In another example, the diameter of the respective spacer RS is 8 μm.
In some embodiments, an orthographic projection of the respective spacer RS on a base substrate is spaced apart from an orthographic projection of the first connecting portion CP1 on the base substrate by a first distance dv1. An orthographic projection of the respective spacer RS on a base substrate is spaced apart from an orthographic projection of the second connecting portion CP2 on the base substrate by a second distance dv2. Optionally, the first distance dv1 is equal to or greater than half of the minimum distance dm. Optionally, the second distance dv2 is equal to or greater than half of the minimum distance dm. In one particular example, the first distance dv1 is equal to or greater than 1.0 μm. In another particular example, the second distance dv2 is equal to or greater than 1.0 μm.
FIG. 19A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure. FIG. 19B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 19C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 19D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 19E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 19F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 20 is a cross-sectional view along a C-C’ line in FIG. 19A. FIG. 21 is a cross-sectional view along a C-C’ line in FIG. 19A when a charge generation layer and a cathode layer are formed in the array substrate. FIG. 22A is a schematic diagram illustrating the structure of a partition layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 22B is a schematic diagram illustrating the structure of an anode layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 22C is a schematic diagram illustrating the structure of an anode layer and a partition layer in a portion of an array substrate in some embodiments according to the present disclosure.
Referring to FIG. 19A to 19F, FIG. 20, FIG. 21, and FIG. 22A to FIG. 22C, in some embodiments, a respective spacer RS of the spacer layer SPL is in a region between a first subpixel of the plurality of first subpixels Sp1, a second subpixel of the plurality of second subpixels Sp2, a third subpixel of the plurality of third subpixels Sp3, and a fourth subpixel of the plurality of fourth subpixels Sp4. The first subpixel, the second subpixel, the third subpixel, and the fourth subpixel are adjacent to each other. Optionally, the respective spacer RS is spaced apart from the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. As discussed above, an orthographic projection of a partition block in a respective first subpixel of the plurality of first subpixels Sp1 on a base substrate is non-overlapping with an orthographic projection of any of the plurality of partition grooves PG on the base substrate.
In some embodiments, an orthographic projection of the respective spacer RS on a base substrate is partially surrounded by orthographic projections of one or more second partition grooves PG2, one or more third partition grooves PG3, and one or more fourth partition grooves PG4 on the base substrate. Optionally, the orthographic projection of the respective spacer RS on the base substrate is spaced apart from the orthographic projections of one or more second partition grooves PG2, one or more third partition grooves PG3, and one or more fourth partition grooves PG4 on the base substrate by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. Optionally, an orthographic projection of a partition block in the respective second subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more second partition grooves PG2 on the base substrate. Optionally, an orthographic projection of a partition block in the respective third subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more third partition grooves PG3 on the base substrate. Optionally, an orthographic projection of a partition block in the respective fourth subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more fourth partition grooves PG4 on the base substrate. In one example, the respective spacer RS is partially surrounded by two second partition grooves, one third partition groove, and one fourth partition groove.
In some embodiments, the respective spacer RS has a cylindrical shape. In some embodiments, a cross-section of the respective spacer RS along a plane parallel to a surface of the planarization layer PLN has a round shape, e.g., a circular shape or an elliptical shape. The inventors of the present disclosure discover that this particular structure of the respective spacer RS is conducive to saving space. In one particular example, the respective spacer RS has a diameter of 10 μm.
In some embodiments, an orthographic projection of the respective spacer RS on a base substrate at least partially overlaps with an orthographic projection of the partition layer PL on the base substrate. In some embodiments, the orthographic projection of the partition layer PL on the base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) the orthographic projection of the respective spacer RS on the base substrate. Optionally, the orthographic projection of the respective spacer RS on the base substrate at least partially overlaps with an orthographic projection of a respective bridge of a plurality of bridges on the base substrate. Optionally, the orthographic projection of the respective bridge of the plurality of bridges on the base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) the orthographic projection of the respective spacer RS on the base substrate.
In some embodiments, a first anode of the respective first subpixel includes a first connecting portion CP1 connected to a transistor through a first via v1 extending through the planarization layer PLN. A third anode of the respective third subpixel includes a second connecting portion CP2 connected to a transistor through a second via v2 extending through the planarization layer PLN. In some embodiments, an orthographic projection of the respective spacer RS on the base substrate is partially surrounded by orthographic projections of the first connecting portion CP1 and the second connecting portion CP2 on the base substrate. Optionally, the orthographic projection of the respective spacer RS on the base substrate is spaced apart from the orthographic projections of the first connecting portion CP1 and the second connecting portion CP2 on the base substrate by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. Optionally, orthographic projections of the first connecting portion CP1, the second connecting portion CP2, and the respective spacer RS on a base substrate are partially surrounded by orthographic projections of edges of the one or more second partition grooves PG2, the one or more third partition grooves PG3, and the one or more fourth partition grooves PG4 on the base substrate. Optionally, the orthographic projections of the first connecting portion CP1, the second connecting portion CP2, and the respective spacer RS on the base substrate are spaced apart from the orthographic projections of edges of the one or more second partition grooves PG2, the one or more third partition grooves PG3, and the one or more fourth partition grooves PG4 on the base substrate by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate.
In some embodiments, a minimum distance between two adjacent subpixel apertures of two adjacent subpixels is denoted as dp. In some embodiments, the minimum distance dp is greater than 1.5 times of the diameter of the respective spacer RS and less than 2 times of the diameter of the respective spacer RS. In one particular example, the minimum distance dp is in a range of 13.5 μm to 25 μm. In some embodiments, a minimum distance between the respective spacer RS and an adjacent partition groove is denoted as dm. In some embodiments, a sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than one half of the minimum distance dp. Optionally, the sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than two third of the minimum distance dp. In some embodiments, the minimum distance dm is equal to or greater than one fifth of the diameter of the respective spacer RS. In one particular example, the minimum distance dm is equal to or greater than 2.0 μm. In another example, the diameter of the respective spacer RS is 8 μm.
The array substrate depicted in FIG. 19A to 19F, FIG. 20, FIG. 21, and FIG. 22A to FIG. 22C differs from the array substrate depicted in FIG. 13A to 13F, FIG. 14, FIG. 15, FIG. 16A to FIG. 16C, FIG. 17, and FIG. 18 in that a distribution density of spacers in the array substrate depicted in FIG. 19A to 19F, FIG. 20, FIG. 21, and FIG. 22A to FIG. 22C is higher than a distribution density of spacers in the array substrate depicted in FIG. 13A to 13F, FIG. 14, FIG. 15, FIG. 16A to FIG. 16C, FIG. 17, and FIG. 18. The inventors of the present disclosure discover that the spacer in the present array substrate is at a position in close proximity to the partition grooves. Due to the presence of the partition grooves in close proximity, an organic material disposed at the position during the process of forming the spacer is prone to flowing toward the partition grooves. The spacer formed in this process is prone to a reduced thickness, for example, after development in a patterning process. A spacer with a reduced thickness may not have sufficient thickness to support the fine metal mask for subsequent fabrication process. By having an increased distribution density of spacers, the present array substrate has an increased number of spacers for supporting the fine metal mask, preventing light emitting materials in the subpixel region from being scraped by the fine metal mask, effectively preventing color mixing or an increased occurrence of dark spots. In one example, a distribution density of spacers is one spacer per eight subpixels (as shown in FIG. 19A) . In another example, a distribution density of spacers is one spacer per sixteen subpixels (as shown in FIG. 13A) .
FIG. 23A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure. FIG. 23B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 23C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 23D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 23E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 23F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 23G is a schematic diagram illustrating the structure of light emitting layers in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 24 is a cross-sectional view along a D-D’ line in FIG. 23A. FIG. 25A is a schematic diagram illustrating the structure of a partition layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 25B is a schematic diagram illustrating the structure of an anode layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 25C is a schematic diagram illustrating the structure of an anode layer and a partition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 26 is a zoom-in view of a portion of an array substrate depicted in FIG. 23A without showing a plurality of light emitting layers. FIG. 27 is a zoom-in view of a portion of an array substrate depicted in FIG. 26 without showing a plurality of light emitting layers. FIG. 28 illustrates a layout of a respective spacer relative to adjacent light emitting layers in a portion of an array substrate in some embodiments according to the present disclosure.
Referring to FIG. 23A to FIG. 23G, FIG. 24, FIG. 25A to FIG. 25C, and FIG. 26 to FIG. 28, the array substrate in some embodiments includes a planarization layer PLN, a partition layer PL on the planarization layer PLN, an anode layer ADL on a side of the partition layer PL away from the planarization layer PLN, a pixel definition layer PDL on a side of the anode layer ADL away from the planarization layer PLN, a spacer layer SPL on a side of the pixel definition layer PDL away from the planarization layer PLN, and a plurality of light emitting layers (e.g., a first light emitting layer EL1 in a respective first subpixel of a plurality of first subpixels Sp1, a second light emitting layer EL2 in a respective second subpixel of a plurality of second subpixels Sp2, a third light emitting layer EL3 in a respective third subpixel of a plurality of third subpixels Sp3, and a fourth light emitting layer EL4 in a respective fourth subpixel of a plurality of fourth subpixels Sp4) on a side of the anode layer ADL away from the planarization layer PLN. The array substrate in some embodiments further includes a plurality of subpixel apertures SA extending through the pixel definition layer PDL. A respective light emitting layer of the plurality of light emitting layers is at least partially in a respective subpixel aperture of the plurality of subpixel apertures.
The array substrate in some embodiments further includes a plurality of partition grooves PG. In a region outside the plurality of partition grooves PG, the planarization layer PLN has a first thickness t1. In a region having the respective partition groove of the plurality of partition grooves PG, the planarization layer PLN has a second thickness t2. The second thickness t2 is less than the first thickness t1. In some embodiments, an edge of a portion of the partition layer PL partially extends into a respective partition groove of the plurality of partition grooves PG.
In some embodiments, the array substrate includes a partition structure PS. The partition structure PS includes a portion of the planarization layer PLN and a portion of the partition layer PL on the portion of the planarization layer PLN. The partition structure PS in some embodiments further includes a recess RS recessing into portion of the planarization layer PLN underneath an edge portion of the partition layer PL.
When one or more common layers are deposited on the substrate, the one or more common layers are at least partially segregated by the partition structure PS. In some embodiments, the array substrate further includes one or more residual common layers in a respective partition groove of the plurality of partition grooves PG. The inventors of the present disclosure discover that, by having the partition structure PS, subpixel crosstalk between adjacent subpixels in the array substrate is significantly reduced.
In some embodiments, an orthographic projection of the partition layer PL on a base substrate at least partially overlaps with an orthographic projection of the anode layer ADL on the base substrate. Optionally, the orthographic projection of the partition layer PL on the base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) the orthographic projection of the anode layer ADL on the base substrate.
In some embodiments, an orthographic projection of the partition layer PL on a base substrate at least partially overlaps with an orthographic projection of the anode layer ADL on the base substrate.
In some embodiments, an orthographic projection of the partition layer PL on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of a respective partition groove of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition layer PL on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the respective partition groove of the plurality of partition grooves PG on the base substrate.
In some embodiments, the partition layer PL includes a plurality of partition blocks PB and a plurality of bridges Br connecting multiple partition blocks of the plurality of partition blocks PB. In some embodiments, an orthographic projection of a respective partition block of the plurality of partition blocks PB on a base substrate at least partially overlaps with an orthographic projection of a respective anode of a respective subpixel on the base substrate. Optionally, the orthographic projection of the respective partition block on the base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) the orthographic projection of the respective anode of the respective subpixel on the base substrate.
In some embodiments, an orthographic projection of a respective bridge of the plurality of bridges Br on a base substrate is at least partially non-overlapping with an orthographic projection of a respective anode of a respective subpixel on the base substrate. Optionally, the orthographic projection of the respective bridge on the base substrate is substantially non-overlapping with (e.g., at least 70%non-overlapping with, at least 75%non-overlapping with, at least 80%non-overlapping with, at least 85%non-overlapping with, at least 90%non-overlapping with, at least 95%non-overlapping with, at least 99%non-overlapping with, or completely non-overlapping with) the orthographic projection of the respective anode of the respective subpixel on the base substrate.
In some embodiments, the plurality of partition blocks PB and the plurality of bridges Br are parts of a unitary structure.
In some embodiments, the array substrate includes a plurality of first subpixels Sp1. Optionally, the plurality of first subpixels Sp1 are subpixels of a first color, e.g., a blue color. In some embodiments, an orthographic projection of a partition block in a respective first subpixel of the plurality of first subpixels Sp1 on a base substrate is non-overlapping with an orthographic projection of any of the plurality of partition grooves PG on the base substrate.
In some embodiments, the array substrate includes a plurality of second subpixels Sp2. Optionally, the plurality of second subpixels Sp2 are subpixels of a second color, e.g., a red color. In some embodiments, an orthographic projection of a partition block in a respective second subpixel of the plurality of second subpixels Sp2 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective second subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds an orthographic projection of an anode in the respective second subpixel on the base substrate. In one particular example, the orthographic projection of the partition block in the respective second subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of an orthographic projection of edges of four partition grooves of the plurality of partition grooves PG on the base substrate. In another example, the orthographic projection of the edges of the four partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds the orthographic projection of the anode in the respective second subpixel on the base substrate, for example, on four sides of the orthographic projection of the anode in the respective second subpixel on the base substrate, respectively.
In some embodiments, the array substrate includes a plurality of third subpixels Sp3. Optionally, the plurality of third subpixels Sp3 are subpixels of a third color, e.g., a green color. In some embodiments, an orthographic projection of a partition block in a respective third subpixel of the plurality of third subpixels Sp3 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective third subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds an orthographic projection of an anode in the respective third subpixel on the base substrate. In one particular example, the orthographic projection of the partition block in the respective third subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of an orthographic projection of edges of two partition grooves of the plurality of partition grooves PG on the base substrate. In another example, the orthographic projection of the edges of the two partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds the orthographic projection of the anode in the respective third subpixel on the base substrate, for example, on two sides of the orthographic projection of the anode in the respective third subpixel on the base substrate, respectively.
In some embodiments, the array substrate includes a plurality of fourth subpixels Sp4. Optionally, the plurality of fourth subpixels Sp4 are subpixels of a third color, e.g., a green color. In some embodiments, an orthographic projection of a partition block in a respective fourth subpixel of the plurality of fourth subpixels Sp4 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective fourth subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds an orthographic projection of an anode in the respective fourth subpixel on the base substrate. In one particular example, the orthographic projection of the partition block in the respective fourth subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of an orthographic projection of edges of two partition grooves of the plurality of partition grooves PG on the base substrate. In another example, the orthographic projection of the edges of the two partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds the orthographic projection of the anode in the respective fourth subpixel on the base substrate, for example, on two sides of the orthographic projection of the anode in the respective fourth subpixel on the base substrate, respectively.
In some embodiments, a respective spacer RS of the spacer layer SPL is in a region between a first subpixel of the plurality of first subpixels Sp1, a second subpixel of the plurality of second subpixels Sp2, a third subpixel of the plurality of third subpixels Sp3, and a fourth subpixel of the plurality of fourth subpixels Sp4. The first subpixel, the second subpixel, the third subpixel, and the fourth subpixel are adjacent to each other. Optionally, the respective spacer RS is spaced apart from the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. As discussed above, an orthographic projection of a partition block in a respective first subpixel of the plurality of first subpixels Sp1 on a base substrate is non-overlapping with an orthographic projection of any of the plurality of partition grooves PG on the base substrate.
In some embodiments, an orthographic projection of the respective spacer RS on a base substrate is partially surrounded by orthographic projections of one or more second partition grooves PG2, one or more third partition grooves PG3, and one or more fourth partition grooves PG4 on the base substrate. Optionally, the orthographic projection of the respective spacer RS on the base substrate is spaced apart from the orthographic projections of one or more second partition grooves PG2, one or more third partition grooves PG3, and one or more fourth partition grooves PG4 on the base substrate by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. Optionally, an orthographic projection of a partition block in the respective second subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more second partition grooves PG2 on the base substrate. Optionally, an orthographic projection of a partition block in the respective third subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more third partition grooves PG3 on the base substrate. Optionally, an orthographic projection of a partition block in the respective fourth subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more fourth partition grooves PG4 on the base substrate. In one example, the respective spacer RS is partially surrounded by two second partition grooves, one third partition groove, and one fourth partition groove.
In some embodiments, the respective spacer RS has a cylindrical shape. In some embodiments, a cross-section of the respective spacer RS along a plane parallel to a surface of the planarization layer PLN has a round shape, e.g., a circular shape or an elliptical shape. The inventors of the present disclosure discover that this particular structure of the respective spacer RS is conducive to saving space. In one particular example, the respective spacer RS has a diameter of 10 μm.
In some embodiments, an orthographic projection of the respective spacer RS on a base substrate is substantially non-overlapping with (e.g., at least 70%non-overlapping with, at least 75%non-overlapping with, at least 80%non-overlapping with, at least 85%non-overlapping with, at least 90%non-overlapping with, at least 95%non-overlapping with, at least 99%non-overlapping with, or completely non-overlapping with) an orthographic projection of the partition layer PL on the base substrate.
In some embodiments, a minimum distance between two adjacent subpixel apertures of two adjacent subpixels is denoted as dp. In some embodiments, the minimum distance dp is greater than 1.5 times of the diameter of the respective spacer RS and less than 2 times of the diameter of the respective spacer RS. In one particular example, the minimum distance dp is 19 μm.
In some embodiments, a minimum distance between the respective spacer RS and an adjacent partition groove is denoted as dm. In some embodiments, a sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than one half of the minimum distance dp. Optionally, the sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than two third of the minimum distance dp.
In some embodiments, the minimum distance dm is equal to or greater than one fifth of the diameter of the respective spacer RS. In one particular example, the minimum distance dm is equal to or greater than 2.0 μm. In another example, the diameter of the respective spacer RS is 10 μm.
In alternative embodiments, the minimum distance dm is equal to or less than 37.5%of the diameter of the respective spacer RS. In one particular example, the minimum distance dm is equal to or less than 3.0 μm. In another example, the diameter of the respective spacer RS is 8 μm.
In some embodiments, an orthographic projection of the respective spacer RS on a base substrate is at least partially surrounded by orthographic projections of a first light emitting layer EL1 in a first subpixel of a plurality of first subpixels Sp1, a second light emitting layer EL2 in a second subpixel of a plurality of second subpixels Sp2, a third light emitting layer EL3 in a third subpixel of a plurality of third subpixels Sp3, and a fourth light emitting layer EL4 in a fourth subpixel of a plurality of fourth subpixels Sp4 on the base substrate. Optionally, the orthographic projection of the respective spacer RS on the base substrate is spaced apart from the orthographic projections of the first light emitting layer EL1, the second light emitting layer EL2, the third light emitting layer EL3, and the fourth light emitting layer EL4 on the base substrate by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate.
FIG. 29 is a schematic diagram illustrating the structure of a first light emitting layer in some embodiments according to the present disclosure. Referring to FIG. 29, the array substrate in some embodiments includes a notch NT recessing into the first light emitting layer EL1.
FIG. 30 illustrates a relative position of a respective spacer with respect to a mask plate for depositing a first light emitting material in some embodiments according to the present disclosure. Referring to FIG. 30, in some embodiments, an orthographic projection of the mask plate MK for depositing a first light emitting material on a base substrate at least partially overlaps with an orthographic projection of the respective spacer on the base substrate. Optionally, the orthographic projection of the mask plate MK for depositing a first light emitting material on the base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) the orthographic projection of the respective spacer on the base substrate. The inventors of the present disclosure discover that, by having this structure, the respective spacer RS can sufficiently support the mask plate during the depositing process.
In some embodiments, referring to FIG. 23A to FIG. 23G, FIG. 24, FIG. 25A to FIG. 25C, and FIG. 26 to FIG. 30, an orthographic projection of the respective spacer RS on a base substrate is substantially non-overlapping with (e.g., at least 70%non-overlapping with, at least 75%non-overlapping with, at least 80%non-overlapping with, at least 85%non-overlapping with, at least 90%non-overlapping with, at least 95%non-overlapping with, at least 99%non-overlapping with, or completely non-overlapping with) an orthographic projection of the first light emitting layer EL1 on the base substrate. In some embodiments, the orthographic projection of the respective spacer RS on the base substrate is substantially non-overlapping with (e.g., at least 70%non-overlapping with, at least 75%non-overlapping with, at least 80% non-overlapping with, at least 85%non-overlapping with, at least 90%non-overlapping with, at least 95%non-overlapping with, at least 99%non-overlapping with, or completely non-overlapping with) orthographic projections of the first light emitting layer EL1, the second light emitting layer EL2, the third light emitting layer EL3, and the fourth light emitting layer EL4 on the base substrate.
In some embodiments, an edge of the first light emitting layer EL1 along the notch NT has a shape conforming to a shape of the respective spacer RS. In some embodiments, a minimum distance between the respective spacer RS and the edge of the first light emitting layer EL1 is denoted as de. Optionally, the minimum distance de is equal to or greater than one third of the minimum distance dm. Optionally, the minimum distance de is equal to or greater than one half of the minimum distance dm. In one particular example, the minimum distance de is equal to or greater than 2.0 μm.
In the array substrate depicted in FIG. 23A to FIG. 23G, FIG. 24, FIG. 25A to FIG. 25C, and FIG. 26 to FIG. 30, the plurality of first subpixels Sp1 includes first subpixels in close proximity to the plurality of spacers, and first subpixels distal to the plurality of spacers. The first subpixels in close proximity to the plurality of spacers are each spaced apart from the plurality of spacers by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. The first subpixels distal to the plurality of spacers are each spaced apart from the plurality of spacers by a distance greater than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. In some embodiments, the array substrate includes a notch recessing into a respective first light emitting layer of a respective one of the first subpixels in close proximity to the plurality of spacers. In some embodiments, the array substrate does not include a notch recessing into a respective first light emitting layer of a respective one of the first subpixels distal to the plurality of spacers. In the first subpixels distal to the plurality of spacers, the respective first light emitting layer has a round corner.
FIG. 31A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure. FIG. 31B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 31C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 31D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 31E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 31F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 31G is a schematic diagram illustrating the structure of light emitting layers in a portion of an array substrate in some embodiments according to the present disclosure.
In the array substrate depicted in FIG. 31A to FIG. 31G, in some embodiments, the array substrate includes a respective notch recessing into a respective first light emitting layer of a respective first subpixel of the plurality of first subpixels Sp1. By having this structure, the uniformity of the array substrate can be enhanced.
FIG. 32A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure. FIG. 32B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 32C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 32D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 32E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 32F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 33 is a cross-sectional view along a E-E’ line in FIG. 32A. FIG. 34A is a schematic diagram illustrating the structure of a partition layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 34B is a schematic diagram illustrating the structure of an anode layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 34C is a schematic diagram illustrating the structure of an anode layer and a partition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 35 is a zoom-in view of a portion of an array substrate depicted in FIG. 32A.
Referring to FIG. 32A to FIG. 32F, and FIG. 33, the array substrate in some embodiments includes a planarization layer PLN, a partition layer PL on the planarization layer PLN, an anode layer ADL on a side of the partition layer PL away from the planarization layer PLN, a pixel definition layer PDL on a side of the anode layer ADL away from the planarization layer PLN, and a spacer layer SPL on a side of the pixel definition layer PDL away from the planarization layer PLN. The array substrate in some embodiments further includes a plurality of subpixel apertures SA extending through the pixel definition layer PDL.
The array substrate in some embodiments further includes a plurality of partition grooves PG. In a region outside the plurality of partition grooves PG, the planarization layer PLN has a first thickness t1. In a region having the respective partition groove of the plurality of partition grooves PG, the planarization layer PLN has a second thickness t2. The second thickness t2 is less than the first thickness t1. In some embodiments, an edge of a portion of the partition layer PL partially extends into a respective partition groove of the plurality of partition grooves PG.
In some embodiments, the array substrate includes a partition structure PS. The partition structure PS includes a portion of the planarization layer PLN and a portion of the partition layer PL on the portion of the planarization layer PLN. The partition structure PS in some embodiments further includes a recess RS recessing into portion of the planarization layer PLN underneath an edge portion of the partition layer PL.
When one or more common layers are deposited on the substrate, the one or more common layers are at least partially segregated by the partition structure PS. In some embodiments, the array substrate further includes one or more residual common layers in a respective partition groove of the plurality of partition grooves PG. The inventors of the present disclosure discover that, by having the partition structure PS, subpixel crosstalk between adjacent subpixels in the array substrate is significantly reduced.
In some embodiments, an orthographic projection of the partition layer PL on a base substrate at least partially overlaps with an orthographic projection of the anode layer ADL on the base substrate. Optionally, the orthographic projection of the partition layer PL on the base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) the orthographic projection of the anode layer ADL on the base substrate.
In some embodiments, an orthographic projection of the partition layer PL on a base substrate at least partially overlaps with an orthographic projection of the light emitting layer on the base substrate.
In some embodiments, an orthographic projection of the partition layer PL on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of a respective partition groove of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition layer PL on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the respective partition groove of the plurality of partition grooves PG on the base substrate.
In some embodiments, the partition layer PL includes a plurality of partition blocks PB and a plurality of bridges Br connecting multiple partition blocks of the plurality of partition blocks PB. In some embodiments, an orthographic projection of a respective partition block of the plurality of partition blocks PB on a base substrate at least partially overlaps with an orthographic projection of a respective anode of a respective subpixel on the base substrate. Optionally, the orthographic projection of the respective partition block on the base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) the orthographic projection of the respective anode of the respective subpixel on the base substrate.
In some embodiments, an orthographic projection of a respective bridge of the plurality of bridges Br on a base substrate is at least partially non-overlapping with an orthographic projection of a respective anode of a respective subpixel on the base substrate. Optionally, the orthographic projection of the respective bridge on the base substrate is substantially non-overlapping with (e.g., at least 70%non-overlapping with, at least 75%non-overlapping with, at least 80%non-overlapping with, at least 85%non-overlapping with, at least 90%non-overlapping with, at least 95%non-overlapping with, at least 99%non-overlapping with, or completely non-overlapping with) the orthographic projection of the respective anode of the respective subpixel on the base substrate.
In some embodiments, an orthographic projection of a respective spacer RS on a base substrate at least partially overlaps with an orthographic projection of a bridge of the plurality of bridges Br on the base substrate. Optionally, the orthographic projection of the bridge on the base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) the orthographic projection of the respective spacer RS on the base substrate. Optionally, the orthographic projection of the respective spacer RS on the base substrate at least partially overlaps with an orthographic projection of a bridge of the plurality of bridges Br connecting two adjacent partition blocks in two adjacent first subpixels of the plurality of first subpixels Sp1 on the base substrate.
In some embodiments, the array substrate includes a plurality of first subpixels Sp1. Optionally, the plurality of first subpixels Sp1are subpixels of a first color, e.g., a blue color. In some embodiments, an orthographic projection of a partition block in a respective first subpixel of the plurality of first subpixels Sp1 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective first subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds an orthographic projection of an anode in the respective first subpixel on the base substrate.
In some embodiments, the array substrate includes a plurality of second subpixels Sp2. Optionally, the plurality of second subpixels Sp2 are subpixels of a second color, e.g., a red color. In some embodiments, an orthographic projection of a partition block in a respective second subpixel of the plurality of second subpixels Sp2 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective second subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds an orthographic projection of an anode in the respective second subpixel on the base substrate.
In some embodiments, the array substrate includes a plurality of third subpixels Sp3. Optionally, the plurality of third subpixels Sp3 are subpixels of a third color, e.g., a green color. In some embodiments, an orthographic projection of a partition block in a respective third subpixel of the plurality of third subpixels Sp3 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective third subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds an orthographic projection of an anode in the respective third subpixel on the base substrate.
In some embodiments, a respective spacer RS of the spacer layer SPL is in a region between two first subpixels of the plurality of first subpixels Sp1, two second subpixels of the plurality of second subpixels Sp2, and two third subpixels of the plurality of third subpixels Sp3. The two first subpixels, the two second subpixels, and the two third subpixels are adjacent to each other. Optionally, the respective spacer RS is spaced apart from the two first subpixels, the two second subpixels, and the two third subpixels by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate.
In some embodiments, an orthographic projection of the respective spacer RS on a base substrate is partially surrounded by orthographic projections of one or more first partition grooves PG1, one or more second partition grooves PG2, and one or more third partition grooves PG3 on the base substrate. Optionally, the orthographic projection of the respective spacer RS on the base substrate is spaced apart from the orthographic projections of one or more first partition grooves PG1, one or more second partition grooves PG2, and one or more third partition grooves PG3 on the base substrate by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. Optionally, an orthographic projection of a partition block in the respective first subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more first partition grooves PG1 on the base substrate. Optionally, an orthographic projection of a partition block in the respective second subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more second partition grooves PG2 on the base substrate. Optionally, an orthographic projection of a partition block in the respective third subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more third partition grooves PG3 on the base substrate. In one example, the respective spacer RS is partially surrounded by two first partition grooves, one second partition groove, and two third partition grooves.
In some embodiments, the respective spacer RS has a cuboid shape. In some embodiments, a cross-section of the respective spacer RS along a plane parallel to a surface of the planarization layer PLN has a rectangular shape or a square shape. Optionally, the cross-section of the respective spacer RS along the plane parallel to the surface of the planarization layer PLN has a length or a width in a range of 8 μm to 13 μm. In one particular example, the cross-section of the respective spacer RS along the plane parallel to the surface of the planarization layer PLN has a length or a width of 10 μm.
In some embodiments, a minimum distance between two adjacent subpixel apertures of two adjacent subpixels is denoted as dp. In some embodiments, the minimum distance dp is greater than 1.5 times of the diameter of the respective spacer RS and less than 2 times of the diameter of the respective spacer RS. In one particular example, the minimum distance dp is 19 μm.
In some embodiments, a minimum distance between the respective spacer RS and an adjacent partition groove is denoted as dm. In some embodiments, a sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than one half of the minimum distance dp. Optionally, the sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than two third of the minimum distance dp.
In some embodiments, the minimum distance dm is equal to or greater than one fifth of the diameter of the respective spacer RS. In one particular example, the minimum distance dm is equal to or greater than 2.0 μm. In another example, the diameter of the respective spacer RS is 10 μm.
In alternative embodiments, the minimum distance dm is equal to or less than 37.5%of the diameter of the respective spacer RS. In one particular example, the minimum distance dm is equal to or less than 3.0 μm. In another example, the diameter of the respective spacer RS is 8 μm.
FIG. 36A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure. FIG. 36B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 36C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 36D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 36E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 36F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure.
The array substrate depicted in FIG. 36A to 36F differs from the array substrate depicted in FIG. 32A to 32F in that the respective spacer RS in the array substrate depicted in FIG. 36A to 36F has a cylindrical shape. In some embodiments, a cross-section of the respective spacer RS along a plane parallel to a surface of the planarization layer PLN has a round shape, e.g., a circular shape or an elliptical shape. Optionally, the cross-section of the respective spacer RS along the plane parallel to the surface of the planarization layer PLN has a diameter in a range of 8 μm to 13 μm. In one particular example, the cross-section of the respective spacer RS along the plane parallel to the surface of the planarization layer PLN has a diameter of 10 μm.
FIG. 37A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure. FIG. 37B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 37C is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 37D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 37E is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 37F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 38 is a cross-sectional view along an F-F’ line in FIG. 37A. FIG. 39 is a cross-sectional view along an F-F’ line in FIG. 37A when a charge generation layer and a cathode layer are formed in the array substrate. FIG. 40A is a schematic diagram illustrating the structure of a partition layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 40B is a schematic diagram illustrating the structure of an anode layer and a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 40C is a schematic diagram illustrating the structure of an anode layer and a partition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 41 is a zoom-in view of a portion of an array substrate depicted in FIG. 37A. FIG. 42 is a zoom-in view of a portion of an array substrate depicted in FIG. 41.
Referring to FIG. 37A to FIG. 37F, FIG. 38, FIG. 39, FIG. 40A to FIG. 40C, FIG. 41, and FIG. 42 the array substrate in some embodiments includes a planarization layer PLN, a partition layer PL on the planarization layer PLN, an anode layer ADL on a side of the partition layer PL away from the planarization layer PLN, a pixel definition layer PDL on a side of the anode layer ADL away from the planarization layer PLN, and a spacer layer SPL on a side of the pixel definition layer PDL away from the planarization layer PLN. The array substrate in some embodiments further includes a plurality of subpixel apertures SA extending through the pixel definition layer PDL. The array substrate further includes a light emitting layer EL at least partially in a respective subpixel aperture of the plurality of subpixel apertures.
The array substrate in some embodiments further includes a plurality of partition grooves PG. In a region outside the plurality of partition grooves PG, the planarization layer PLN has a first thickness t1. In a region having the respective partition groove of the plurality of partition grooves PG, the planarization layer PLN has a second thickness t2. The second thickness t2 is less than the first thickness t1. In some embodiments, an edge of a portion of the partition layer PL partially extends into a respective partition groove of the plurality of partition grooves PG.
In some embodiments, the array substrate includes a partition structure PS. The partition structure PS includes a portion of the planarization layer PLN and a portion of the partition layer PL on the portion of the planarization layer PLN. The partition structure PS in some embodiments further includes a recess RS recessing into portion of the planarization layer PLN underneath an edge portion of the partition layer PL.
When one or more common layers (e.g., a charge generation layer CGL and a cathode layer CD) are deposited on the substrate, the one or more common layers are at least partially segregated by the partition structure PS. In some embodiments, the array substrate further includes one or more residual common layers (e.g., a residual charge generation layer RCGL and a residual cathode layer RCD) in a respective partition groove of the plurality of partition grooves PG. The inventors of the present disclosure discover that, by having the partition structure PS, subpixel crosstalk between adjacent subpixels in the array substrate is significantly reduced.
In some embodiments, an orthographic projection of the partition layer PL on a base substrate at least partially overlaps with an orthographic projection of the anode layer ADL on the base substrate. Optionally, the orthographic projection of the partition layer PL on the base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) the orthographic projection of the anode layer ADL on the base substrate.
In some embodiments, an orthographic projection of the partition layer PL on a base substrate at least partially overlaps with an orthographic projection of the light emitting layer EL on the base substrate.
In some embodiments, an orthographic projection of the partition layer PL on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of a respective partition groove of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition layer PL on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the respective partition groove of the plurality of partition grooves PG on the base substrate.
In some embodiments, the partition layer PL includes a plurality of partition blocks PB. In some embodiments, an orthographic projection of a respective partition block of the plurality of partition blocks PB on a base substrate at least partially overlaps with an orthographic projection of a respective anode of a respective subpixel on the base substrate. Optionally, the orthographic projection of the respective partition block on the base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) the orthographic projection of the respective anode of the respective subpixel on the base substrate.
In some embodiments, the array substrate includes a plurality of first subpixels Sp1. Optionally, the plurality of first subpixels Sp1 are subpixels of a first color, e.g., a blue color. In some embodiments, an orthographic projection of a partition block in a respective first subpixel of the plurality of first subpixels Sp1 on a base substrate is non-overlapping with an orthographic projection of any of the plurality of partition grooves PG on the base substrate.
In some embodiments, the array substrate includes a plurality of second subpixels Sp2. Optionally, the plurality of second subpixels Sp2 are subpixels of a second color, e.g., a red color. In some embodiments, an orthographic projection of a partition block in a respective second subpixel of the plurality of second subpixels Sp2 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective second subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds an orthographic projection of an anode in the respective second subpixel on the base substrate. In one particular example, the orthographic projection of the partition block in the respective second subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of an orthographic projection of edges of two partition grooves of the plurality of partition grooves PG on the base substrate. In another example, the orthographic projection of the edges of the two partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds the orthographic projection of the anode in the respective second subpixel on the base substrate, for example, on two sides of the orthographic projection of the anode in the respective second subpixel on the base substrate, respectively.
In some embodiments, the array substrate includes a plurality of third subpixels Sp3. Optionally, the plurality of third subpixels Sp3 are subpixels of a third color, e.g., a green color. In some embodiments, an orthographic projection of a partition block in a respective third subpixel of the plurality of third subpixels Sp3 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective third subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds an orthographic projection of an anode in the respective third subpixel on the base substrate. In one particular example, the orthographic projection of the partition block in the respective third subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of an orthographic projection of edges of two partition grooves of the plurality of partition grooves PG on the base substrate. In another example, the orthographic projection of the edges of the two partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds the orthographic projection of the anode in the respective third subpixel on the base substrate, for example, on two sides of the orthographic projection of the anode in the respective third subpixel on the base substrate, respectively.
In some embodiments, the array substrate includes a plurality of fourth subpixels Sp4. Optionally, the plurality of fourth subpixels Sp4 are subpixels of a third color, e.g., a green color. In some embodiments, an orthographic projection of a partition block in a respective fourth subpixel of the plurality of fourth subpixels Sp4 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective fourth subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds an orthographic projection of an anode in the respective fourth subpixel on the base substrate. In one particular example, the orthographic projection of the partition block in the respective fourth subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of an orthographic projection of edges of two partition grooves of the plurality of partition grooves PG on the base substrate. In another example, the orthographic projection of the edges of the two partition grooves of the plurality of partition grooves PG on the base substrate partially surrounds the orthographic projection of the anode in the respective fourth subpixel on the base substrate, for example, on two sides of the orthographic projection of the anode in the respective fourth subpixel on the base substrate, respectively.
In some embodiments, a respective spacer RS of the spacer layer SPL is in a region between a first subpixel of the plurality of first subpixels Sp1, a second subpixel of the plurality of second subpixels Sp2, a third subpixel of the plurality of third subpixels Sp3, and a fourth subpixel of the plurality of fourth subpixels Sp4. The first subpixel, the second subpixel, the third subpixel, and the fourth subpixel are adjacent to each other. Optionally, the respective spacer RS is spaced apart from the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel by a distance less than a maximum width of an anode in the array substrate. As discussed above, an orthographic projection of a partition block in a respective first subpixel of the plurality of first subpixels Sp1 on a base substrate is non-overlapping with an orthographic projection of any of the plurality of partition grooves PG on the base substrate.
In some embodiments, an orthographic projection of the respective spacer RS on a base substrate is partially surrounded by orthographic projections of one or more second partition grooves PG2, one or more third partition grooves PG3, and one or more fourth partition grooves PG4 on the base substrate. Optionally, the orthographic projection of the respective spacer RS on the base substrate is spaced apart from the orthographic projections of one or more second partition grooves PG2, one or more third partition grooves PG3, and one or more fourth partition grooves PG4 on the base substrate by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. Optionally, an orthographic projection of a partition block in the respective second subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more second partition grooves PG2 on the base substrate. Optionally, an orthographic projection of a partition block in the respective third subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more third partition grooves PG3 on the base substrate. Optionally, an orthographic projection of a partition block in the respective fourth subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more fourth partition grooves PG4 on the base substrate. In one example, the respective spacer RS is partially surrounded by one second partition groove, one third partition groove, and one fourth partition groove.
In some embodiments, the respective spacer RS has a cylindrical shape. In some embodiments, a cross-section of the respective spacer RS along a plane parallel to a surface of the planarization layer PLN has a round shape, e.g., a circular shape or an elliptical shape. The inventors of the present disclosure discover that this particular structure of the respective spacer RS is conducive to saving space. In one particular example, the respective spacer RS has a diameter of 10 μm.
In some embodiments, an orthographic projection of the respective spacer RS on a base substrate is substantially non-overlapping with (e.g., at least 70%non-overlapping with, at least 75%non-overlapping with, at least 80%non-overlapping with, at least 85%non-overlapping with, at least 90%non-overlapping with, at least 95%non-overlapping with, at least 99%non-overlapping with, or completely non-overlapping with) an orthographic projection of the partition layer PL on the base substrate.
In some embodiments, a minimum distance between two adjacent subpixel apertures of two adjacent subpixels is denoted as dp. In some embodiments, the minimum distance dp is greater than 1.5 times of the diameter of the respective spacer RS and less than 2 times of the diameter of the respective spacer RS. In one particular example, the minimum distance dp is 19 μm.
In some embodiments, a minimum distance between the respective spacer RS and an adjacent partition groove is denoted as dm. In some embodiments, a sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than one half of the minimum distance dp. Optionally, the sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than two third of the minimum distance dp.
In some embodiments, the minimum distance dm is equal to or greater than one fifth of the diameter of the respective spacer RS. In one particular example, the minimum distance dm is equal to or greater than 2.0 μm. In another example, the diameter of the respective spacer RS is 10 μm.
In alternative embodiments, the minimum distance dm is equal to or less than 37.5%of the diameter of the respective spacer RS. In one particular example, the minimum distance dm is equal to or less than 3.0 μm. In another example, the diameter of the respective spacer RS is 8 μm.
FIG. 43A is a schematic diagram illustrating the structure of a portion of an array substrate in some embodiments according to the present disclosure. FIG. 43B is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 43C is a schematic diagram illustrating the structure of an anode layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 43D is a schematic diagram illustrating the structure of a pixel definition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 43E is a schematic diagram illustrating the structure of a partition layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 43F is a schematic diagram illustrating the structure of a spacer layer in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 44 is a cross-sectional view along a G-G’ line in FIG. 43A. FIG. 45 is a zoom-in view of a portion of an array substrate depicted in FIG. 43A. FIG. 46 is a zoom-in view of a portion of an array substrate depicted in FIG. 45.
Referring to FIG. 43A to FIG. 43F, and FIG. 44, the array substrate in some embodiments includes a planarization layer PLN, an anode layer ADL on the planarization layer PLN, a pixel definition layer PDL on a side of the anode layer ADL away from the planarization layer PLN, a partition layer PL on a side of the pixel definition layer PDL away from the planarization layer PLN, and a spacer layer SPL on a side of the pixel definition layer PDL away from the planarization layer PLN. The array substrate in some embodiments further includes a plurality of subpixel apertures SA extending through the pixel definition layer PDL. The array substrate further includes a light emitting layer at least partially in a respective subpixel aperture of the plurality of subpixel apertures.
The array substrate in some embodiments further includes a plurality of partition grooves PG. In a region outside the plurality of partition grooves PG, the pixel definition layer PDL has a first thickness t1. In a region having the respective partition groove of the plurality of partition grooves PG, the pixel definition layer PDL has a second thickness t2. The second thickness t2 is less than the first thickness t1.
In some embodiments, the partition layer PL includes a plurality of partition blocks PB. A respective partition block of the plurality of partition blocks PB is limited in a partition groove of the plurality of partition grooves PG. An orthographic projection of the plurality of partition blocks PB on a base substrate is non-overlapping with an orthographic projection of the anode layer ADL on the base substrate. An orthographic projection of the partition layer PL on a base substrate is non-overlapping with an orthographic projection of a light emitting layer on the base substrate. An orthographic projection of a portion of the pixel definition layer PDL having the second thickness t2 on a base substrate substantially covers (e.g., covers at least 70%of, covers at least 75%of, covers at least 80%of, covers at least 85%of, covers at least 90%of, covers at least 95%of, covers at least 99%of, or completely covers) an orthographic projection of the partition layer PL on the base substrate.
When one or more common layers (e.g., a charge generation layer and a cathode layer) are deposited on the substrate, the one or more common layers are at least partially segregated by the respective partition block. In some embodiments, the array substrate further includes one or more residual common layers (e.g., a residual charge generation layer and a residual cathode layer) in a respective partition groove of the plurality of partition grooves PG. The inventors of the present disclosure discover that, by having the partition structure PS, subpixel crosstalk between adjacent subpixels in the array substrate is significantly reduced.
In some embodiments, the array substrate includes a plurality of first subpixels Sp1. Optionally, the plurality of first subpixels Sp1 are subpixels of a first color, e.g., a blue color. In some embodiments, an orthographic projection of an anode in a respective first subpixel of the plurality of first subpixels Sp1 on a base substrate is non-overlapping with an orthographic projection of any of the plurality of partition grooves PG on the base substrate. In some embodiments, the array substrate lacks any partition groove that surrounds the anode in the respective first subpixel.
In some embodiments, the array substrate includes a plurality of second subpixels Sp2. Optionally, the plurality of second subpixels Sp2 are subpixels of a second color, e.g., a red color. In some embodiments, an orthographic projection of an anode in a respective second subpixel of the plurality of second subpixels Sp2 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective second subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate at least partially surrounds an orthographic projection of an anode in the respective second subpixel on the base substrate.
In some embodiments, the array substrate includes a plurality of third subpixels Sp3. Optionally, the plurality of third subpixels Sp3 are subpixels of a third color, e.g., a green color. In some embodiments, an orthographic projection of a partition block in a respective third subpixel of the plurality of third subpixels Sp3 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective third subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate at least partially surrounds an orthographic projection of an anode in the respective third subpixel on the base substrate.
In some embodiments, the array substrate includes a plurality of fourth subpixels Sp4. Optionally, the plurality of fourth subpixels Sp4 are subpixels of a third color, e.g., a green color. In some embodiments, an orthographic projection of a partition block in a respective fourth subpixel of the plurality of fourth subpixels Sp4 on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves PG on the base substrate. Optionally, the orthographic projection of the partition block in the respective fourth subpixel on the base substrate covers at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , and is non-overlapping with at least 20% (e.g., at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%) , of the orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate. The orthographic projection of the one or more edges of the one or more partition grooves of the plurality of partition grooves PG on the base substrate at least partially surrounds an orthographic projection of an anode in the respective fourth subpixel on the base substrate.
In some embodiments, a respective spacer RS of the spacer layer SPL is in a region between a first subpixel of the plurality of first subpixels Sp1, a second subpixel of the plurality of second subpixels Sp2, a third subpixel of the plurality of third subpixels Sp3, and a fourth subpixel of the plurality of fourth subpixels Sp4. The first subpixel, the second subpixel, the third subpixel, and the fourth subpixel are adjacent to each other. Optionally, the respective spacer RS is spaced apart from the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. As discussed above, an orthographic projection of an anode in a respective first subpixel of the plurality of first subpixels Sp1 on a base substrate is non-overlapping with an orthographic projection of any of the plurality of partition grooves PG on the base substrate.
In some embodiments, an orthographic projection of the respective spacer RS on a base substrate is partially surrounded by orthographic projections of one or more second partition grooves PG2, one or more third partition grooves PG3, and one or more fourth partition grooves PG4 on the base substrate. Optionally, the orthographic projection of the respective spacer RS on the base substrate is spaced apart from the orthographic projections of one or more second partition grooves PG2, one or more third partition grooves PG3, and one or more fourth partition grooves PG4 on the base substrate by a distance less than a maximum width (e.g., half of a maximum width) of an anode in the array substrate. Optionally, an orthographic projection of an anode in the respective second subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more second partition grooves PG2 on the base substrate. Optionally, an orthographic projection of an anode in the respective third subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more third partition grooves PG3 on the base substrate. Optionally, an orthographic projection of an anode in the respective fourth subpixel on a base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of the one or more fourth partition grooves PG4 on the base substrate. In one example, the respective spacer RS is partially surrounded by one second partition groove, one third partition groove, and one fourth partition groove.
In some embodiments, the respective spacer RS has a cylindrical shape. In some embodiments, a cross-section of the respective spacer RS along a plane parallel to a surface of the planarization layer PLN has a round shape, e.g., a circular shape or an elliptical shape. The inventors of the present disclosure discover that this particular structure of the respective spacer RS is conducive to saving space. In one particular example, the respective spacer RS has a diameter of 10 μm.
In some embodiments, an orthographic projection of the respective spacer RS on a base substrate is substantially non-overlapping with (e.g., at least 70%non-overlapping with, at least 75%non-overlapping with, at least 80%non-overlapping with, at least 85%non-overlapping with, at least 90%non-overlapping with, at least 95%non-overlapping with, at least 99%non-overlapping with, or completely non-overlapping with) an orthographic projection of the partition layer PL on the base substrate.
In some embodiments, a minimum distance between two adjacent subpixel apertures of two adjacent subpixels is denoted as dp. In some embodiments, the minimum distance dp is greater than 1.5 times of the diameter of the respective spacer RS and less than 2 times of the diameter of the respective spacer RS. In one particular example, the minimum distance dp is 19 μm.
In some embodiments, a minimum distance between the respective spacer RS and an adjacent partition groove is denoted as dm. In some embodiments, a sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than one half of the minimum distance dp. Optionally, the sum of the diameter of the respective spacer RS and two times the minimum distance dm is less than the minimum distance dp, and greater than two third of the minimum distance dp.
In some embodiments, the minimum distance dm is equal to or greater than one fifth of the diameter of the respective spacer RS. In one particular example, the minimum distance dm is equal to or greater than 2.0 μm. In another example, the diameter of the respective spacer RS is 10 μm.
In alternative embodiments, the minimum distance dm is equal to or less than 37.5%of the diameter of the respective spacer RS. In one particular example, the minimum distance dm is equal to or less than 3.0 μm. In another example, the diameter of the respective spacer RS is 8 μm.
FIG. 47 illustrates a detailed structure in a display area in an array substrate in some embodiments according to the present disclosure. Referring to FIG. 47, the array substrate in some embodiments includes a semiconductor material layer SML, a first conductive layer CT1, a second conductive layer CT2, a first signal line layer SL1, and a second signal line layer SL2. The array substrate further includes an insulating layer IN between the first conductive layer CT1 and the second conductive layer CT2; an inter-layer dielectric layer ILD between the second conductive layer CT2 and the first signal line layer SL1; and at least a passivation layer PVX or a first planarization layer PLN1 between the first signal line layer SL1 and the second signal line layer SL2.
In some embodiments, the array substrate in the display area includes a base substrate BS; an active layer ACT of a respective one of a plurality of thin film transistors TFT on the base substrate BS; a gate insulating layer GI on a side of the active layer ACT away from the base substrate BS; a gate electrode G and a first capacitor electrode Ce1 (both are parts of the first conductive layer CT1) on a side of the gate insulating layer GI away from the base substrate BS; an insulating layer IN on a side of the gate electrode G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (a part of the second conductive layer CT2) on a side of the insulating layer IN away from the gate insulating layer GI; an inter-layer dielectric layer ILD on a side of the second capacitor electrode Ce2 away from the gate insulating layer GI; a source electrode S and a drain electrode D (parts of the first signal line layer SL1) on a side of the inter-layer dielectric layer ILD away from the gate insulating layer GI; a passivation layer PVX on a side of the source electrode S and the drain electrode D away from the inter-layer dielectric layer ILD; a first planarization layer PLN1 on a side of the passivation layer PVX away from the inter-layer dielectric layer ILD; a relay electrode RE (part of the second signal line layer SL2) on a side of the first planarization layer PLN1 away from the passivation layer PVX; a second planarization layer PLN2 on side of the relay electrode RE away from the first planarization layer PLN1; a partition layer PL on side of the second planarization layer PLN2 away from the base substrate BS; a pixel definition layer PDL defining a subpixel aperture and on a side of the second planarization layer PLN2 away from the base substrate BS; and a light emitting element LE at least partially in the subpixel aperture. The light emitting element LE includes an anode AD on a side of the second planarization layer PLN2 away from the first planarization layer PLN1; a light emitting layer EL on a side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD on a side of the light emitting layer EL away from the anode AD. The array substrate in the display area further includes an encapsulating layer EN encapsulating the light emitting element LE, and on a side of the cathode layer CD away from the base substrate BS. The encapsulating layer EN in some embodiments includes a first inorganic encapsulating sub-layer CVD1 on a side of the cathode layer CD away from the base substrate BS, an organic encapsulating sub-layer IJP on a side of the first inorganic encapsulating sub-layer CVD1 away from the base substrate BS, and a second inorganic encapsulating sub-layer CVD2 on a side of the organic encapsulating sub-layer IJP away from the first inorganic encapsulating sub-layer CVD1. The array substrate in the display area further includes a buffer layer BUF on a side of the encapsulating layer EN away from the base substrate BS; a plurality of second electrode bridges BR2 on a side of the buffer layer BUF away from the encapsulating layer EN; a touch insulating layer TI on a side of the plurality of second electrode bridges BR2 away from the buffer layer BUF; a plurality of first touch electrodes TE1 on a side of the touch insulating layer TI away from the buffer layer BUF; and an overcoat layer OC on a side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI. Optionally, the array substrate in the display area does not include the passivation layer PVX, e.g., the inter-layer dielectric layer ILD is in direct contact with the first planarization layer PLN1.
Referring to FIG. 47, the plurality of first touch electrodes TE1 are in a second metal layer ML2, and the plurality of second electrode bridges BR2 are in a first metal layer ML1. In some embodiments, the plurality of first touch electrode lines and the plurality of second touch electrode lines are in the second metal layer ML2. In alternative embodiments, the plurality of first touch electrode lines and the plurality of second touch electrode lines are in the first metal layer ML1. In alternative embodiments, the plurality of first touch electrode lines and the plurality of second touch electrode lines are partially in the first metal layer ML1 and partially in the second metal layer ML2.
The second planarization layer PLN2 depicted in FIG. 47 is equivalent to the planarization layer PLN depicted in FIG. 7B, FIG. 13B, FIG. 19B, FIG. 23B, FIG. 31B, FIG. 32B, FIG. 36B, FIG. 37B, and FIG. 43B.
In another aspect, the present invention provides a display apparatus, including the array substrate described herein or fabricated by a method described herein, and one or more integrated circuits connected to the array substrate. Examples of appropriate display apparatuses include, but are not limited to, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital album, a GPS, etc. Optionally, the display apparatus is an organic light emitting diode display apparatus. Optionally, the display apparatus is a micro light emitting diode display apparatus. Optionally, the display apparatus is a mini light emitting diode display apparatus.
In another aspect, the present disclosure provides a method of fabricating an array substrate. In some embodiments, the method includes forming a planarization layer; forming a partition layer on the planarization layer; forming an anode layer on a side of the partition layer away from the planarization layer; forming a pixel definition layer on a side of the anode layer away from the planarization layer; forming a spacer layer on a side of the pixel definition layer away from the planarization layer; and forming a plurality of partition grooves extending through the pixel definition layer. Optionally, an orthographic projection of the partition layer on a base substrate at least partially overlaps with an orthographic projection of the anode layer on the base substrate. Optionally, the orthographic projection of the partition layer on the base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of a respective partition groove of the plurality of partition grooves on the base substrate.
The foregoing description of the embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. Therefore, the term “the invention” , “the present invention” or the like does not necessarily limit the claim scope to a specific embodiment, and the reference to exemplary embodiments of the invention does not imply a limitation on the invention, and no such limitation is to be inferred. The invention is limited only by the spirit and scope of the appended claims. Moreover, these claims may refer to use “first” , “second” , etc. following with noun or element. Such terms should be understood as a nomenclature and should not be construed as giving the limitation on the number of the elements modified by such nomenclature unless specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.

Claims

An array substrate, comprising:

a planarization layer;

a partition layer on the planarization layer;

an anode layer on a side of the partition layer away from the planarization layer;

a pixel definition layer on a side of the anode layer away from the planarization layer;

a spacer layer on a side of the pixel definition layer away from the planarization layer; and

a plurality of partition grooves extending through the pixel definition layer;

wherein an orthographic projection of the partition layer on a base substrate at least partially overlaps with an orthographic projection of the anode layer on the base substrate; and

the orthographic projection of the partition layer on the base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of a respective partition groove of the plurality of partition grooves on the base substrate.
The array substrate of claim 1, wherein the orthographic projection of the partition layer on the base substrate covers at least 20%, and is non-overlapping with at least 20%, of the orthographic projection of the respective partition groove of the plurality of partition grooves on the base substrate.
The array substrate of claim 1, wherein the partition layer comprises a plurality of partition blocks;

wherein an orthographic projection of a respective partition block of the plurality of partition blocks on the base substrate at least partially overlaps with an orthographic projection of a respective anode of a respective subpixel on the base substrate.
The array substrate of claim 3, wherein the partition layer further comprises a plurality of bridges connecting multiple partition blocks of the plurality of partition blocks;

wherein an orthographic projection of a respective bridge of the plurality of bridges on the base substrate is at least partially non-overlapping with the orthographic projection of the respective anode of a respective subpixel on the base substrate.
The array substrate of any one of claims 1 to 4, wherein an orthographic projection of a partition block in at least one subpixel on the base substrate is non-overlapping with an orthographic projection of any of the plurality of partition grooves on the base substrate; and

an orthographic projection of a partition block in one or more subpixels on the base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of one or more edges of one or more partition grooves of the plurality of partition grooves on the base substrate.
The array substrate of any one of claims 1 to 4, wherein a respective spacer of the spacer layer is in a region between four adjacent subpixels; and

an orthographic projection of the respective spacer on the base substrate is partially surrounded by orthographic projections of one or more second partition grooves, one or more third partition grooves, and one or more fourth partition grooves on the base substrate.
The array substrate of any one of claims 1 to 5, wherein a cross-section of a respective spacer of the spacer layer along a plane parallel to a surface of the planarization layer has a maximum width; and

a minimum distance between two adjacent subpixel apertures of two adjacent subpixels is greater than the maximum width.
The array substrate of any one of claims 1 to 5, wherein a cross-section of a respective spacer of the spacer layer along a plane parallel to a surface of the planarization layer has a maximum width; and

a sum of the maximum width and two times a minimum distance between a respective spacer of the spacer layer and an adjacent partition groove is less than the minimum distance between two adjacent subpixel apertures of two adjacent subpixels, and greater than one half of the minimum distance between two adjacent subpixel apertures of two adjacent subpixels.
The array substrate of any one of claims 1 to 5, wherein an orthographic projection of a respective spacer of the spacer layer on the base substrate is substantially non-overlapping with an orthographic projection of the partition layer on the base substrate.
The array substrate of any one of claims 1 to 5, wherein an orthographic projection of a respective spacer of the spacer layer on the base substrate at least partially overlaps with an orthographic projection of the partition layer on the base substrate.
The array substrate of claim 4, wherein an orthographic projection of a respective spacer of the spacer layer on the base substrate at least partially overlaps with an orthographic projection of a respective bridge of a plurality of bridges on the base substrate.
The array substrate of claim 6, wherein an anode of at least one subpixel comprises a first connecting portion connected to a transistor through a first via extending through the planarization layer;

an anode of at least another subpixel comprises a second connecting portion connected to a transistor through a second via extending through the planarization layer;

an orthographic projection of the respective spacer on the base substrate is spaced apart from an orthographic projection of the first connecting portion on the base substrate by a first distance;

an orthographic projection of the respective spacer on the base substrate is spaced apart from an orthographic projection of the second connecting portion on the base substrate by a second distance;

the first distance is equal to or greater than 1.0 μm; and

the second distance is equal to or greater than 1.0 μm.
The array substrate of any one of claims 1 to 12, further comprising a plurality of light emitting layers on a side of the anode layer away from the planarization layer;

wherein a respective light emitting layer of the plurality of light emitting layers is at least partially in a respective subpixel aperture of a plurality of subpixel apertures; and

an orthographic projection of a respective spacer of the spacer layer on the base substrate is at least partially surrounded by orthographic projections of four adjacent subpixels on the base substrate.
The array substrate of claim 13, further comprising a notch recessing into the first light emitting layer;

wherein an orthographic projection of the respective spacer on the base substrate is substantially non-overlapping with orthographic projections of the first light emitting layer, the second light emitting layer, the third light emitting layer, and the fourth light emitting layer on the base substrate.
The array substrate of claim 14, wherein a minimum distance between the respective spacer and the edge of the first light emitting layer is equal to or greater than one third of a minimum distance between the respective spacer and an adjacent partition groove.
The array substrate of any one of claims 1 to 4, wherein a respective spacer of the spacer layer is in a region between six adjacent subpixels; and

an orthographic projection of the respective spacer on the base substrate is partially surrounded by orthographic projections of one or more first partition grooves, one or more second partition grooves, and one or more third partition grooves on the base substrate.
The array substrate of any one of claims 1 to 16, wherein, in a region outside the plurality of partition grooves, the planarization layer has a first thickness;

in a region having a respective partition groove of the plurality of partition grooves, the planarization layer has a second thickness;

the second thickness is less than the first thickness; and

an edge of a portion of the partition layer partially extends into the respective partition groove.
The array substrate of any one of claims 1 to 17, comprising a partition structure;

wherein the partition structure comprises:

a portion of the planarization layer;

a portion of the partition layer on the portion of the planarization layer; and

a recess recessing into portion of the planarization layer underneath an edge portion of the partition layer.
The array substrate of claim 18, wherein a portion of the pixel definition layer on the partition layer and between a partition groove of the plurality of partition grooves and a subpixel aperture of the plurality of subpixel apertures has a first slope angle on a side abutting the partition groove and a second slope angle on a side abutting the subpixel aperture; and

the first slope angle is different from the second slope angle.
An array substrate, comprising:

a planarization layer;

an anode layer on the planarization layer;

a pixel definition layer on a side of the anode layer away from the planarization layer;

a partition layer on a side of the pixel definition layer away from the planarization layer;

a spacer layer on a side of the pixel definition layer away from the planarization layer; and

a plurality of partition grooveswherein the partition layer comprises a plurality of partition blocks;

a respective partition block of the plurality of partition blocks is limited in a partition groove of the plurality of partition grooves;

an orthographic projection of the plurality of partition blocks on a base substrate is non-overlapping with an orthographic projection of the anode layer on the base substrate; and

the orthographic projection of the anode layer on the base substrate at least partially overlaps with, and is at least partially non-overlapping with, an orthographic projection of a respective partition groove of the plurality of partition grooves on the base substrate.
A display apparatus, comprising the array substrate of any one of claims 1 to 19, and one or more integrated circuits connected to the array substrate.