EP4681238A1

EP4681238A1 - Switch circuit and power arrangement

Info

Publication number: EP4681238A1
Application number: EP24711879.7A
Authority: EP
Inventors: Kenan Askan
Original assignee: Eaton Intelligent Power Ltd
Current assignee: Eaton Intelligent Power Ltd
Priority date: 2023-03-14
Filing date: 2024-03-13
Publication date: 2026-01-21
Also published as: GB2628123A; WO2024189102A1; GB202303720D0

Abstract

A switch circuit (11) comprises a first and a second switch unit (20, 30), a first circuit output (12) and a controller (13). The first switch unit (20) comprises a first mechanical switch (21), a first semiconductor switch (22), a first input (23) and a first output (24). The second switch unit (30) comprises a second mechanical switch (31), a second semiconductor switch (32), a second input (33) and a second output (34). The controller (13) has a control output (14) coupled to control terminals of the first and the second mechanical switch (21, 31) and of the first and the second semiconductor switch (22, 32). The first mechanical switch (21) and the first semiconductor switch (22) are coupled to each other in a parallel circuit. The second mechanical switch (31) and the second semiconductor switch (32) are coupled to each other in a parallel circuit.

Description

Description SWITCH CIRCUIT AND POWER ARRANGEMENT The present disclosure is related to a switch circuit and a power arrangement with a switch circuit. A power arrangement comprises for example a transformer and a switch circuit. The transformer has a primary and a secondary side. The secondary side of the transformer comprises more than two taps. The switch circuit couples one of the taps to a first circuit output. In case the switch circuit is implemented as an electromechanical switch, electromechanical contactor or electromechanical relay, the number of switching cycles of an electromechanical device of the switch circuit is typically limited due to a high switching current and long arcing periods during tap changing under current. It is an object to provide a switch circuit with reduced arcing. This object is achieved by the subject-matter of the independent claim. Further developments and embodiments are described in the dependent claims. A switch circuit is provided which comprises a first and a second switch unit, a first circuit output and a controller. The first switch unit comprises a first mechanical switch, a first semiconductor switch, a first input and a first output. The second switch unit comprises a second mechanical switch, a second semiconductor switch, a second input and a second output. The controller comprises a control output coupled to control terminals of the first and the second mechanical switch and of the first and the second semiconductor switch. The first mechanical switch and the first semiconductor switch are coupled to each other in a parallel circuit. The first mechanical switch is coupled to the first input and to the first output. The first semiconductor switch is coupled to the first input and to the first output. Correspondingly, the second mechanical switch and the second semiconductor switch are coupled to each other in a parallel circuit. The second mechanical switch is coupled to the second input and to the second output. The second semiconductor switch is coupled to the second input and to the second output. The first and the second output are coupled to the first circuit output. Advantageously, the parallel circuit of the first mechanical switch and of the first semiconductor switch allows to keep a current flowing through the first switch unit even in case the current path switches from the first mechanical switch to the first semiconductor switch. After switching of the current, the first mechanical switch can be set in a non- conducting state without arcing or with only a short period of arcing. A similar switching of current can be performed from the second mechanical switch to the second semiconductor switch. In an embodiment, the switch circuit is implemented as tap changer, circuit breaker or contactor. In an embodiment of the switch circuit, for transfer of a current from the first switch unit to the second switch unit, the controller is configured - to set or keep the first semiconductor switch in a conducting state, - then to set the first mechanical switch in a non- conducting state, ^ then to set the second semiconductor switch in a conducting state and the first semiconductor switch in a non-conducting state, and ^ then to set the second mechanical switch in a conducting state. In a further development of the switch circuit, the controller is configured to implement a delay time after setting the second semiconductor switch in the conducting state before setting the first semiconductor switch in the non-conducting state in the sequence described above. In a further development of the switch circuit, the controller is configured to set the second semiconductor switch in a non-conducting state after setting the second mechanical switch in a conducting state. Conducting state means that a switch is on and non-conducting state means that the switch is off. In an embodiment, the switch circuit comprises a current sensor which is coupled on a first side to the first output of the first switch unit and on a second side to the first circuit output. The current sensor comprises an output coupled to an input of the controller. In an embodiment of the switch circuit, in case a current that flows through the current sensor is above a first threshold and in case the first mechanical switch is in a conducting state, the controller is configured - to set or keep the first semiconductor switch in a conducting state, - then to set the first mechanical switch in a non- conducting state, and - then to set the first semiconductor switch in a non- conducting state. A current that is above the first threshold results e.g. from a short circuit of a load connected to the first circuit output. Advantageously, the switching off procedure is performed with no arcing or only a short period of arcing inside the first mechanical switch. In an embodiment of the switch circuit, in case a current that flows through the current sensor is above a first threshold and during an operation for a current transfer from the first switch unit to the second switch unit, the controller is configured - to set or keep at least one of the first and the second semiconductor switch in a conducting state, - then to set or keep the first mechanical switch in a non- conducting state and to set or keep the second mechanical switch in a non-conducting state, and - then to set the first and the second semiconductor switch in a non-conducting state. In an embodiment of the switch circuit, the first and the second mechanical switch comprises an electromechanical relay, an electromechanical contactor, an electromechanical switch or a bypass relay. The electromechanical relay is e.g. a bypass relay and/or a high-speed relay. For example, the first and the second mechanical switch are realized as high speed bypass relays, high speed arcing switches or high speed electromechanical switches. Thus, the first and the second mechanical switch are configured for a high speed operation. In an embodiment of the switch circuit, the first and the second semiconductor switch are implemented as a full- controllable semiconductor switch or a full-controllable bidirectional switch. For example, the first and the second semiconductor switch are implemented as IGBTs that are connected in common source or as IGBTs that are connected on common drain or as an IGBT that is embedded in a diode rectifier bridge. In an embodiment of the switch circuit, the full-controllable semiconductor switch comprises: - a first and a second field-effect transistor, - a first anti-parallel circuit of a first diode and a first insulated-gate bipolar transistor and a second anti- parallel circuit of a second diode and a second insulated- gate bipolar transistor, - a diode rectifier bridge and a bridge insulated-gate bipolar transistor embedded in the diode rectifier bridge, or - a diode rectifier bridge and a bridge field-effect transistor embedded in the diode rectifier bridge. In an embodiment of the switch circuit, the first switch unit comprises a first overvoltage protection device which is coupled to the first input and to the first output. An overvoltage protection device is e.g. abbreviated as OVP. The second switch unit comprises a second OVP which is coupled to the second input and to the second output. Examples for the first and the second OVP are described below. Once the first or the second semiconductor switch semiconductor is turned off, the current always commutates to the OVP once the voltage increase due to energy stored in an inductor clamped by the OVP; the current decreases to zero as clamping voltage is higher than source voltage. In an embodiment, the switch circuit comprises a first output relay which is coupled on a first side to the first output of the first switch unit and on a second side to the first circuit output. In an example, the first output relay is realized e.g. as a galvanic separation relay, abbreviated GSR, a safety relay or disconnecting relay. In an embodiment, the switch circuit comprises a third switch unit comprising a third mechanical switch, a third semiconductor switch, a third input and a third output. The control output of the controller is coupled to control terminals of the third mechanical switch and the third semiconductor switch. The third mechanical switch and the third semiconductor switch are coupled to each other in a parallel circuit. The third mechanical switch is coupled to the third input and to the third output. The third semiconductor switch is coupled to the third input and to the third output. The third output is coupled to the first circuit output. In an embodiment of the switch circuit, the third mechanical switch comprises an electromechanical relay or an electromechanical contactor. The electromechanical relay is e.g. a bypass relay and/or a high-speed relay. In an embodiment of the switch circuit, the third semiconductor switch is implemented as a full-controllable semiconductor switch. The full-controllable semiconductor switch is implemented e.g. as described above. In an embodiment of the switch circuit, the third switch unit comprises a third OVP which is coupled to the third input and to the third output. In an embodiment, the switch circuit comprises at least a further switch unit comprising a further mechanical switch, a further semiconductor switch, a further input and a further output. The at least a further switch unit is realized such as the first to the third switch unit. In an embodiment, the switch circuit comprises a second circuit output and a reference potential line coupled to the second circuit output. In an example, the switch circuit is realized for a three phase or four phase tap changer, abbreviated 3P/4P tap changer. In an embodiment, the switch circuit comprises an internal load comprising a series circuit of a resistor and a parallel load circuit. The series circuit is coupled on a first end or at a first side to the reference potential line and on a second end or at a second side to a node between the first output of the first switch unit and the first circuit output. The parallel load circuit comprises a further OVP as described below, and a further semiconductor switch. For example, at a start of operation and/or in case the first output relay is in a non-conducting state, the further semiconductor switch is set in a conducting state. Thus, the internal load, mainly the resistor of the internal load, has the function of a load at the secondary side of the transformer. This helps to stabilize the currents and voltages at both sides of the transformer. In an embodiment of the switch circuit, the first, second, third and further OVP is realized e.g. as one of a group consisting of a transient voltage suppressor diode (abbreviated TVS diode), voltage dependent resistor, varistor, metal oxide varistor (abbreviated MOV) or RC snubber network. In an embodiment of the switch circuit, the further semiconductor switch is realized as a full-controllable semiconductor switch, as described above. In an embodiment of the switch circuit, the first input is not directly connected to the second input. The first input is not directly connected to the third input. The second input is not directly connected to the third input. In an embodiment, the switch circuit comprises a second output relay which is inserted in the reference potential line. The second output relay is realized e.g. as a galvanic separation relay, abbreviated GSR, a safety relay or a disconnecting relay In an embodiment, the switch circuit comprises an output voltage detector which is coupled on a first side to the reference potential line and on a second side to a node between the first output of the first switch unit and the first circuit output. In an embodiment, a power arrangement comprises the switch circuit and a transformer with a primary side and a secondary side. The secondary side of the transformer comprises a first tap coupled or connected to the first input of the first switch unit, a second tap coupled or connected to the second input of the second switch unit and a reference tap coupled or connected to the reference potential line. In an example, a third tap of the secondary side is coupled to the third input of the third switch unit. The switch circuit described above is particularly suitable for the power arrangement. Features described in connection with the switch circuit can therefore be used for the power arrangement and vice versa. In an example, the switch circuit is configured to switch on and off a load or more than one load. The switching occurs e.g. under normal conditions. In an example, the switch circuit is implemented as an active-on load switch circuit. The switch circuit comprises a circuit breaker. The switch circuit comprises a hybrid circuit breaker. In an example, the hybrid switching realizes the switching between taps on the load condition with quasi arc-free switching or total arc-free switching increasing the number of possible switching cycles during a life time of the switch circuit. In an example, the switch circuit uses hybrid switching. The tap changing can be realized under quasi arc-free conditions resulting in an increase of the lifetime under load of the switch circuit. The tap changing can be realized faster by the switch circuit in comparison to a switch circuit with only electromechanical devices. A solid-state circuit breaker, abbreviated SSCB, obtains fairly high on-state losses, whereas at a hybrid circuit breaker, abbreviated HCB, on-state losses are comparable with standard mechanical circuit breakers die to the fact that in steady state condition, the current flows through the bypass relay. In an example, the switch circuit can automatically change from one tap to another tap with current and voltage measurement. In an example, the switch circuit also integrates a circuit breaker function and/or a galvanic isolation function. In an example, the switch circuit realizes a contactor function. The switch circuit can also be used for normal switch on and off with galvanic separation function. In an example, the switch circuit realizes a transformer powering without high inrush current by avoiding powering of the transformer without load condition even if there is no load connected. In an example, during tap changing, a high-speed relay is turned off first. Once the current has commutated to the semiconductor switch, the semiconductor switch is also turned off to transfer the current to the next hybrid switch. The following description of figures of embodiments may further illustrate and explain aspects of the switch circuit and power arrangement. Parts, structures and devices with the same structure and the same effect, respectively, appear with equivalent reference symbols. In so far as parts, structures or devices correspond to one another in terms of their function in different figures, the description thereof is not repeated for each of the following figures. Figure 1 shows an embodiment of a power arrangement with a switch circuit, Figures 2A to 2C show embodiments of details of a switch circuit, and Figures 3A to 3C show embodiments of signals of a power arrangement with a switch circuit. Figure 1 shows an embodiment of a power arrangement 10 with a switch circuit 11. The switch circuit 11 comprises a first switch unit 20 comprising a first mechanical switch 21, a first semiconductor switch 22, a first input 23 and a first output 24. Moreover, the switch circuit 11 comprises a second switch unit 30 comprising a second mechanical switch 31, a second semiconductor switch 32, a second input 33 and a second output 34. The switch circuit 11 comprises a first circuit output 12 and a controller 13 with a control output 14 coupled to control terminals of the first and the second mechanical switch 21, 31 and of the first and the second semiconductor switch 22, 32. The first mechanical switch 21 and the first semiconductor switch 22 are coupled or connected to each other in a parallel circuit. The first mechanical switch 21 is coupled or connected to the first input 23 and to the first output 24. The first semiconductor switch 22 is coupled or connected to the first input 23 and to the first output 24. The second mechanical switch 31 and the second semiconductor switch 32 are coupled or connected to each other in a parallel circuit. The second mechanical switch 31 is coupled or connected to the second input 33 and to the second output 34. The second semiconductor switch 32 is coupled or connected to the second input 33 and to the second output 34. The first and the second output 24, 34 are coupled to the first circuit output 12. The first output 24 is connected to the second output 34. The switch circuit 11 comprises a current sensor 15 which is arranged between the first output 24 of the first switch unit 20 and the first circuit output 12. The current sensor 15 comprises an output coupled to an input of the controller 13. The first and the second mechanical switch 21, 31 each comprise a relay or a contactor. The first and the second mechanical switch 21, 31 each comprise an electromechanical relay or an electromechanical contactor. The first and the second semiconductor switch 22, 32 are implemented as a full- controllable semiconductor switch 70 (as shown e.g. in Figures 2A and 2B). The first switch unit 20 comprises a first overvoltage protection device 25 which is coupled or connected to the first input 23 and to the first output 24. An overvoltage protection device can be abbreviated OVP. The second switch unit 30 comprises a second OVP 35 which is coupled or connected to the second input 33 and to the second output 34. The switch circuit 11 comprises a first output relay 16 which is arranged between the first output 23 of the first switch unit 20 and the first circuit output 12. The first output relay 16 is realized e.g. as a galvanic separation relay, abbreviated GSR, a safety relay or a disconnecting relay. The switch circuit 11 comprises a third switch unit 40 comprising a third mechanical switch 41, a third semiconductor switch 42, a third input 43 and a third output 44. The control output 14 of the controller 13 is coupled to control terminals of the third mechanical switch 41 and the third semiconductor switch 42. The third mechanical switch 41 and the third semiconductor switch 42 are coupled or connected to each other in a parallel circuit. The third mechanical switch 41 is coupled or connected to the third input 43 and to the third output 44. The third semiconductor switch 42 is coupled or connected to the third input 43 and to the third output 44. The third output 44 is coupled to the first circuit output 12. The third output 44 is connected to the first and the second output 24, 34. The control output 14 of the controller 13 is a bus output. Thus, the controller 13 generates for each of the switches 21, 22, 31, 32, 41, 42 its own signal. The signals applied to these switches 21, 22, 31, 32, 41, 42 are different. The switch circuit 11 comprises a second circuit output 17. The switch circuit 11 comprises a reference potential line 18 coupled to the second circuit output 17. The switch circuit 11 comprises a second output relay 19 which is inserted in the reference potential line 18. The second output relay 19 is realized such as the first output relay 16. During switching on first the second output relay 19 is closed and then the first output relay 16. In switching off, first the first output relay 16 is opened and then the second output relay 16 is opened. The switch circuit 11 comprises an internal load 50 comprising a series circuit of a resistor 51 and a parallel load circuit 52. The series circuit is couples the reference potential line 18 to a node between the first output 24 of the first switch unit 20 and the first circuit output 12. Advantageously, the internal load 50 reduces an inrush current when the power arrangement 10 is switched on. The parallel load circuit 52 comprises a further OVP 53 and a further semiconductor switch 54. The further semiconductor switch 54 is realized as a full-controllable semiconductor switch. The first, second and third OVP 25, 35, 45 and the further OVP 53 are realized e.g. as one of a group consisting of a transient voltage suppressor diode (abbreviated TVS diode), voltage dependent resistor, varistor, metal oxide varistor (abbreviated MOV), RC snubber network or Zener diode. The first input 23 is not directly connected to the second input 33. The switch circuit 11 comprises an output voltage detector 59 which couples the reference potential line 18 to a node between the first output 23 of the first switch unit 20 and the first circuit output 12. The output voltage detector 59 detects an output voltage VOUT and provides an output voltage signal to an input of the controller 13. The power arrangement 10 additionally comprises a transformer 60 with a primary side 61 and a secondary side 62. The secondary side 62 of the transformer 60 comprises a number N of taps 63-66. The number N of taps 63-66 include a reference tap 66. Thus, the number N is e.g. 3, 4 or 5. The number N is e.g. larger than 2, larger than 3 or larger than 4. In the example shown in Figure 1, the number N is 4. Thus, the secondary side 62 of the transformer 60 comprises a first tap 63 coupled or connected to the first input 23 of the first switch unit 20, a second tap 64 coupled or connected to the second input 33 of the second switch unit 30 and the reference tap 66 coupled or connected to the reference potential line 18. The secondary side 62 of the transformer 60 optionally comprises a third tap 65 coupled or connected to the third input 43 of the third switch unit 40. The primary side 61 comprises a number LP of windings. The secondary side 62 comprises a first number L1 of windings 67 which couple the first tap 63 to the second tap 64. The secondary side 62 comprises a second number L2 of windings 68 which couple the second tap 64 to the third tap 65. The secondary side 62 comprises a third number L3 of windings 69 which couple the third tap 65 to the reference tap 66. The power arrangement 10 comprises an input voltage detector 81 which is coupled to a first tap of the primary side 61 and to a second tap of the primary side 62. The input voltage detector 81 detects an input voltage VIN and provides an input voltage signal to an input of the controller 13. The power arrangement 10 comprises a load 80 coupled to the first and the second circuit output 12, 17. Figure 2A shows an embodiment of details of a switch circuit 10 which is a further development of the embodiment shown in Figure 1. The first and the second semiconductor switch 22, 32 are implemented as a full-controllable semiconductor switch 70. The full-controllable semiconductor switch 70 comprises a first anti-parallel circuit of a first insulated- gate bipolar transistor 71, abbreviated IGBT, and a first diode 72 and a second anti-parallel circuit of a second IGBT 73 and a second diode 74. The full-controllable semiconductor switch 70 is realized as bidirectional switch or full-controllable bidirectional switch. The first diode 72 and the first IGBT 71 form an anti-parallel circuit. A collector of the first IGBT 71 is connected e.g. to a cathode of the first diode 72. An emitter of the first IGBT 71 is connected to e.g. an anode of the first diode 72. The first IGBT 71 is an n-channel IGBT or a p-channel IGBT. The first IGBT 71 is e.g. an enhancement mode IGBT. The first diode 72 and the first IGBT 71 form the first anti- parallel circuit. The second diode 74 and the second IGBT 73 form the second anti-parallel circuit. A collector of the second IGBT 73 is connected to a cathode of the first diode 74. An emitter of the second IGBT 73 is connected to an anode of the second diode 74. The first anti-parallel circuit and the second anti-parallel circuit are connected in series. The second anti-parallel circuit and the first anti-parallel circuit are oriented anti-serial. The emitter of the second IGBT 73 is connected to the emitter of the first IGBT 71. Therefore, the anode of the second diode 74 is connected to the anode of the first diode 72. In an alternative embodiment, not shown, the collector of the second IGBT 73 is connected to the collector of the first IGBT 71. Therefore, the cathode of the second diode 74 is connected to the cathode of the first diode 72. The second anti-parallel circuit and the first anti-parallel circuit are oriented anti-serial also in this configuration. Figure 2B shows an embodiment of details of a switch circuit which is a further development of the embodiments shown in Figures 1 and 2A. The full-controllable semiconductor switch 70 comprises a first and a second field-effect transistor 75, 78. Field-effect transistor can be abbreviated FET. The first FET 75 comprises a first intrinsic body diode 76. The second FET 77 comprises a second intrinsic body diode 78. A controlled section of the first FET 75 and a controlled section of the second FET 77 are connected in series. The first FET 75 and the second FET 77 are oriented anti-serial. Thus, a source of the first FET 75 is connected to a source of the second FET 77. Correspondingly, the first intrinsic body diode 76 and the second intrinsic body diode 78 are oriented anti-serial. The anode of the first intrinsic body diode 76 is connected to an anode of the second intrinsic body diode 78. The FETs that form the first FET 75 and the second FET 78 are only operated in the first and the third quadrant. For example, the first and the second FET 75, 77 can be realized both as silicon FETs (abbreviated Si FET) or both as gallium nitride FETs (abbreviated GaN FET). A GaN FET typically is free from an intrinsic body diode but shows a “reverse conduction” from a source to a drain of the first FET 75 and of the second FET 77. The first and the second FET 75, 77 have the same channel type. The first and the second FET 75, 77 are both n-channel FETs or are both p-channel FETs. The first and the second FETs 75, 77 are e.g. enhancement mode FETs. The first and the second FETs 75, 77 are e.g. implemented both as metal-oxide-semiconductor FETs, abbreviated MOSFETs, or both as metal-isolator-semiconductor FETs, abbreviated MISFETs. The first and the second FETs 75, 77 are power transistors. Alternatively, the full-controllable semiconductor switch 70 comprises the first FET 75 and a first diode 76. The first FET 75 and the first diode 76 form an anti-parallel circuit. The first diode 76 is external to the first FET 75. The first diode 76 is designed such that e.g. the first diode 76 has a superior characteristic in comparison to an intrinsic body diode or to the reverse conduction in case of a GaN FET. Furthermore, the full-controllable semiconductor switch 70 comprises the second FET 77 and a second diode 78 realized such as the first diode 76. In an alternative embodiment, not shown, a drain of the first FET 75 is connected to a drain of the second FET 77. The cathode of the first intrinsic body diode 76 is connected to a cathode of the second intrinsic body diode 78. Also in this case, the first FET 75 and the second FET 85 are oriented anti-serial and the first intrinsic body diode 76 and the second intrinsic body diode 78 are oriented anti-serial. Figure 2C shows an embodiment of details of a switch circuit which is a further development of the embodiments shown in Figures 1, 2A and 2B. The full-controllable semiconductor switch 70 comprises a diode rectifier bridge 85 and a bridge IGBT 84. The diode rectifier bridge 85 comprise a first to a fourth bridge diode 86 to 89. Two taps of the diode rectifier bridge 85 are connected to the first input 23 and to the first output 24. Two further taps of the diode rectifier bridge 85 are connected to an emitter and a collector of the bridge IGBT 84. A current can IT1 flow from the first input 23 via a first bridge diode 86, the bridge IGBT 84 and a second bridge diode 87 to the first output 24. Alternatively, a current IT1 can flow from the first output 24 via a third bridge diode 88, the bridge IGBT 84 and a fourth bridge diode 89 to the first input 23. The full-controllable semiconductor switch 70 is bidirectional. In an alternative, not shown embodiment, the full- controllable semiconductor switch 70 comprises the diode rectifier bridge 85 (as shown in figure 2C) and a bridge FET. The bridge FET replaces the bridge IGBT 86. Figure 3A to 3C show an embodiment of signals of a power arrangement 10 with a switch circuit 11 which is a further development of the embodiments shown in Figures 1 and 2A to 2C. The signals are received by a simulation. In Figure 3A, the following signals are shown as a function of a time t: - A first control signal SCS1 that is provided to the first mechanical switch 21, - a further first control signal SCT1 that is provided to the first semiconductor switch 22, - a second control signal SCS2 that is provided to the second mechanical switch 31, and - a further second control signal SCT2 that is provided to the second semiconductor switch 32. In Figure 3B, the following signals are shown as a function of the time t: - A first current IS1 that flows through the first mechanical switch 21, - a further first current IT1 that flows through the first semiconductor switch 22, - a second current IS2 that flows through the second mechanical switch 31, - a further second current IT2 that flows through the second semiconductor switch 32, and - a current I that flows through the current sensor 15 and flows to the load 80. In Figure 3C, the following signals are shown as a function of the time t: - the output voltage Vout which is detected by the output voltage detector 59 and is provided to the load 80, and - the current I that flows to the load 80. The timescale in Figure 3C is different from the timescale in Figures 3A and 3B. Figures 3A and 3B only show the signals and currents before and after the peak of the output voltage Vout and of the current I at about t = 0.06 s. At 35 ms (milliseconds), a source voltage rises to a threshold value that is e.g. 1.2 x Vn. Vn is a nominal value. At t=60 ms the system detects the crossing of the threshold, and activates the tap changing. As the output voltage Vout increases, the load current I increases too. After tap changing the load current I decreases to its nominal value. The controller 13 sets the following phases P1 to P4 of operation A current I flows through the first switch unit 20. In a first phase P1, the controller 13 sets or keeps the first mechanical switch 21 in a conducting state and the current I is equal to the first current IS1. The first mechanical switch 21 is set in a conducting state means that the first mechanical switch 21 is on and current can flow through the first mechanical switch 21. The first mechanical switch 21 is in a non-conducting state means that the first mechanical switch 21 is off and no current can flow through the first mechanical switch 21. The controller 13 sets the first semiconductor switch 22 in a conducting state. For transfer of a current I from the first switch unit 20 to the second switch unit 30, the controller 13 performs the following phases: In a second phase P2, the controller 13 sets or keeps the first semiconductor switch 22 in a conducting state and sets the first mechanical switch 21 in a non-conducting state. Thus, the first current IS1 decreases to zero and the further first current IT1 increases. The current I flows now only through the first semiconductor switch 22. In a third phase P3, the controller 13 sets the second semiconductor switch 32 in a conducting state and sets the first semiconductor switch 22 in a non-conducting state. Thus, the further first current IT1 decreases and the further second current IT2 increases. The further second current IT2 at the end of the third phase P3 may be different from (e.g. smaller than) the further first current IT1 at the end of the second phase P2 or at the start of the third phase P3. This reduction of the current I is a reason for the tap change. In a fourth phase P4, the controller 13 sets the second mechanical switch 31 in a conducting state. The controller 13 keeps the second semiconductor switch 32 in a conducting state (as shown in Figure 3A) or alternatively sets the second semiconductor switch 32 in a non-conducting state. Thus, the further second current IT2 decreases to approximately 0and the second current IS2 increases. Since a resistance of the second semiconductor switch 32 is higher than a resistance of the second mechanical switch 31, the second current IS2 is higher than the further second current IT2 in the fourth phase P4. Thus, the current I is identical or approximately identical with the second current IS2. The fourth phase P4 follows the third phase P3. The third phase P3 follows the second phase P2. The second phase P2 follows the first phase P1. Since a resistance of the first semiconductor switch 22 is typically higher than a resistance of the first mechanical switch 21, the first current IS1 is higher than the further first current IT1 in the first phase P1. In the first semiconductor switch 22 as shown in Figure 2A, the further first current IT1 flows through one of the two IGBTs 71, 73 and one of the diodes 72, 74. An IGBT and a diode each has a pn-junction. Each of the pn-junctions has a turn-on voltage of 0.5-0.7 V; thus in total 1-1.4 V. Therefore, the further first current IT1 is only non-zero in case an amount of the voltage difference across the first semiconductor switch 22 is larger than 1-1.4 V. In the first semiconductor switch 22 as shown in Figure 2B, the further first current IT1 flows through both FETs 75, 77. Due to the unipolar structure of the FETs 75, 77, there is no 0.5-0.7V turn-on voltage. If the FETs 75, 77 are kept on, the further first current IT1 still flows through the FETs 75, 77. Optionally, at the transition from the second phase P2 to the third phase P3, the controller 13 sets the first semiconductor switch 22 in a non-conducting state after setting the second semiconductor switch 32 in a conducting state. Thus, there is a time delay between the further second control signal SCT2 applied to the second semiconductor switch 32 and the further first control signal SCT1 applied to the first semiconductor switch 22. Optionally, in the fourth phase P4, the controller 13 sets the second semiconductor switch 32 in a non-conducting state after setting the second mechanical switch 31 in a conducting state period. Thus, there is a time delay between the second control signal SCS2 applied to the second mechanical switch 31 and the further second control signal SCT2 applied to the second semiconductor switch 32. Alternatively, the controller 13 performs steps for transfer of the current I - from the second switch unit 30 to the first switch unit 20, - from the second switch unit 30 to the third switch unit 40, - from the third switch unit 40 to the second switch unit 30, or - from the third switch unit 40 to the first switch unit 20. The transfer is performed similarly as described above. The switch circuit 11 performs these transfers to reduce or increase the output voltage VOUT and/or the current I that flows through the first circuit output 12. In case the current I that flows through the current sensor 15 is above a first threshold and in case the first mechanical switch 21 is in a conducting state, the controller 13 performs the following operation: ^ the controller 13 sets or keeps the first semiconductor switch 22 in a conducting state, ^ then the controller 13 sets the first mechanical switch 21 in a non-conducting state, and ^ then the controller 13 sets the first semiconductor switch 22 in a non-conducting state, and ^ optionally, then the controller 13 sets the first output relay 16 in a non-conducting state. A high current value results e.g. from a short circuit of the load 80 or a short circuit inside a cable that connects the switch circuit 11 to the load 80. A fault current detection is realized by detecting that the current I that flows through the current sensor 15 is above a first threshold. In case the current I that flows through the current sensor 15 is above a first threshold and during an operation for a current transfer from the first switch unit 20 to the second switch unit 30, the controller 13 performs the following operation: ^ the controller 13 sets or keeps at least one of the first and the second semiconductor switch 22, 32 in a conducting state, ^ then the controller 13 sets or keeps the first mechanical switch 21 in a non-conducting state and sets or keeps the second mechanical switch 31 in a non-conducting state, ^ then the controller 13 sets the first and the second semiconductor switch 22, 32 in a non-conducting state, and ^ optionally, then the controller 13 sets the first output relay 16 in a non-conducting state. Alternatively in case of the fault current detection, all semiconductor switches 22, 32, 42 are set in a conducting state (are on) and all bypass relays 21, 31, 41 are controlled to open contacts. After successful current commutation and conduction, all semiconductor switches 22, 32, 42 are set in a non-conducting state (are off). Once the current I measured by the current sensor 15 is zero, the galvanic separation relays 16, 19 are controlled to open. Advantageously, for a circuit breaker operation, the galvanic separation relays 16, 19 provide an air gap after the switching event for safe isolation (e.g. in case of fault current detection). The embodiments shown in Figures 1 to 3 as stated represent examples of the improved switch circuit 11 and power arrangement 10, they do not constitute a complete list of all embodiments according to the improved switch circuit and power arrangement. An actual switch circuit and power arrangement may vary from the embodiments shown in terms of parts, structures and devices, for example.

Reference numerals 10 power arrangement 11 switch circuit 12 first circuit output 13 controller 14 control output 15 current sensor 16 first output relay 17 second tape changer output 18 reference potential line 19 second output relay 20, 30, 40 switch unit 21, 31, 41 mechanical switch 22, 32, 42 semiconductor switch 23, 33, 43 input 24, 34, 44 output 25, 35, 45 overvoltage protection device 50 internal load 51 resistor 52 parallel load circuit 53 further overvoltage protection device 54 further semiconductor switch 59 output voltage detector 60 transformer 61 primary side 62 secondary side 63 to 65 tap 66 reference tap 67 to 69 windings 70 full-controllable semiconductor switch 71, 73 insulated gate type bipolar transistor 72, 74 diode 75, 77 field-effect transistor 76, 78 diode 80 load 81 input voltage detector 84 bridge insulated gate type bipolar transistor 85 diode rectifier bridge 86 to 89 bridge diode I, IS1, IT1 current IS2, IT2 current IS3, IT3 current P1 to P4 phase SCS1, SCT1 control signal SCS2, SCT2 control signal VOUT output voltage

Claims

Claims 1. A switch circuit (11), comprising: - a first switch unit (20) comprising a first mechanical switch (21), a first semiconductor switch (22), a first input (23) and a first output (24), - a second switch unit (30) comprising a second mechanical switch (31), a second semiconductor switch (32), a second input (33) and a second output (34), - a first circuit output (12), and - a controller (13) with a control output (14) coupled to control terminals of the first and the second mechanical switch (21, 31) and of the first and the second semiconductor switch (22, 32), wherein the first mechanical switch (21) and the first semiconductor switch (22) are coupled to each other in a parallel circuit, the first mechanical switch (21) is coupled to the first input (23) and to the first output (24) and the first semiconductor switch (22) is coupled to the first input (23) and to the first output (24), wherein the second mechanical switch (31) and the second semiconductor switch (32) are coupled to each other in a parallel circuit, the second mechanical switch (31) is coupled to the second input (33) and to the second output (34) and the second semiconductor switch (32) is coupled to the second input (33) and to the second output (34), and wherein the first and the second output (24, 34) are coupled to the first circuit output (12), wherein the switch circuit (11) comprises a current sensor (15) which is coupled on a first side to the first output (24) of the first switch unit (20) and on a second side to the first circuit output (12), wherein the current sensor (15) comprises an output coupled to the controller (13), and wherein in case a current (I) that flows through the current sensor (15) is above a first threshold and in case the first mechanical switch (21) is in a conducting state, the controller (13) is configured ^ to set or keep the first semiconductor switch (22) in a conducting state, ^ then to set the first mechanical switch (21) in a non- conducting state, and ^ then to set the first semiconductor switch (22) in a non- conducting state, wherein in case a current (I) that flows through the current sensor (15) is above a first threshold and during an operation for a current transfer from the first switch unit (20) to the second switch unit (30), the controller (13) is configured ^ to set or keep at least one of the first and the second semiconductor switch (22, 32) in a conducting state, ^ then to set or keep the first mechanical switch (21) in a non-conducting state and to set or keep the second mechanical switch (31) in a non-conducting state, and then to set the first and the second semiconductor switch (22, 32) in a non-conducting state. 2. The switch circuit (11) of claim 1, wherein for transfer of a current (I) from the first switch unit (20) to the second switch unit (30), the controller (13) is configured ^ to set or keep the first semiconductor switch (22) in a conducting state, ^ then to set the first mechanical switch (21) in a non- conducting state, ^ then to set the second semiconductor switch (32) in a conducting state and the first semiconductor switch (22) in a non-conducting state, and ^ then to set the second mechanical switch (31) in a conducting state. 3. The switch circuit (11) of claim 2, wherein the controller (13) is configured to set the second semiconductor switch (32) in a non-conducting state after setting the second mechanical switch (31) in a conducting state. 4. The switch circuit (11) of one of claims 1 to 3, wherein the first and the second mechanical switch (21, 31) each comprises an electromechanical relay, an electromechanical contactor, an electromechanical switch or a bypass relay. 5. The switch circuit (11) of one of claims 1 to 4, wherein the first and the second semiconductor switch (22, 32) are implemented both as a full-controllable semiconductor switch (70). 6. The switch circuit (11) of claim 5, wherein the full-controllable semiconductor switch (70) comprises: - a first and a second field-effect transistor (75, 77), - a first anti-parallel circuit of a first insulated-gate bipolar transistor (71) and a first diode (72) and a second anti-parallel circuit of a second insulated-gate bipolar transistor (73) and a second diode (74), - a diode rectifier bridge (85) and a bridge insulated-gate bipolar transistor (84) embedded in the diode rectifier bridge (85), or - a diode rectifier bridge (85) and a field-effect transistor embedded in the diode rectifier bridge (85). 7. The switch circuit (11) of one of claims 1 to 6, wherein the first switch unit (20) comprises a first overvoltage protection device (25) which is coupled to the first input (23) and to the first output (24), and wherein the second switch unit (30) comprises a second overvoltage protection device (35) which is coupled to the second input (33) and to the second output (34). 8. The switch circuit (11) of one of claims 1 to 7, wherein the switch circuit (11) comprises a first output relay (16) which is coupled on a first side to the first output (23) of the first switch unit (20) and on a second side to the first circuit output (12). 9. The switch circuit (11) of one of claims 1 to 8, wherein the switch circuit (11) comprises a third switch unit (40) comprising a third mechanical switch (41), a third semiconductor switch (42), a third input (43) and a third output (44), wherein the control output (14) of the controller (13) is coupled to control terminals of the third mechanical switch (41) and the third semiconductor switch (42), wherein the third mechanical switch (41) and the third semiconductor switch (42) are coupled to each other in a parallel circuit, the third mechanical switch (41) is coupled to the third input (43) and to the third output (44) and the third semiconductor switch (42) is coupled to the third input (43) and to the third output (44), and wherein the third output (44) is coupled to the first circuit output (12). 10. The switch circuit (11) of one of claims 1 to 9, wherein the switch circuit (11) comprises a second circuit output (17) and a reference potential line (18) coupled to the second circuit output (17). 11. The switch circuit (11) of claim 10, wherein the switch circuit (11) comprises an internal load (50) comprising a series circuit, wherein the series circuit comprises a resistor (51) and a parallel load circuit (52), wherein the series circuit is coupled on a first end to the reference potential line (18) and on a second end to a node between the first output (24) of the first switch unit (20) and the first circuit output (12), and wherein the parallel load circuit (52) comprises a further overvoltage protection device (53) and a further semiconductor switch (54). 12. The switch circuit (11) of claim 10 or 11, wherein the switch circuit (11) comprises a second output relay (19) which is inserted in the reference potential line (18). 13. The switch circuit (11) of one of claims 10 to 12, wherein the switch circuit (11) comprises an output voltage detector (59) which is coupled on a first side to the reference potential line (18) and on a second side to a node between the first output (23) of the first switch unit (20) and the first circuit output (12). 14. A power arrangement (10), comprising ^ the switch circuit (11) of one of claims 10 to 13, and ^ a transformer (60) with a primary side (61) and a secondary side (62), wherein the secondary side (62) of the transformer (60) comprises a first tap (63) coupled to the first input (23) of the first switch unit (20), a second tap (64) coupled to the second input (33) of the second switch unit (30) and a reference tap (66) coupled to the reference potential line (18).