EP4677391A1

EP4677391A1 - Configurable photon sensing device

Info

Publication number: EP4677391A1
Application number: EP24712569.3A
Authority: EP
Inventors: Robert Henderson
Original assignee: University of Edinburgh
Current assignee: University of Edinburgh
Priority date: 2023-03-08
Filing date: 2024-03-08
Publication date: 2026-01-14
Also published as: WO2024184653A1; JP2026508898A; CN120826623A; GB202303367D0; KR20250159230A

Abstract

A photon sensing device for photon sensing comprising: a plurality of photon detectors coupled to a plurality of shift registers, wherein the plurality of photon detectors and shift registers are provided as part of a configurable circuitry configurable to combine two or more of the plurality of shift registers and to combine two or more photon detectors to form one or more combined shift registers and one or more combined photon detectors, respectively.

Description

Configurable Photon Sensing Device

Field

The present invention relates to a photon sensing device for photon sensing, in particular, a configurable photon sensing device.

Background

Single photon sensing devices, in particular, Single Photon Avalanche Detector (SPAD) based sensors may typically be implemented in a variety of applications including, for example, LiDAR, time-of-flight (ToF) and 3D imaging applications.

Characteristics and operation of SPADs may be influenced by a number of factors, such as the underlying semiconductor technology used to implement the SPADs and also by associated circuitry for controlling and sensing SPAD operation and recording SPAD events, e.g. photon strikes. In some examples, circuitry required to readout and/or store a state of a SPAD may substantially influence a size, cost, power consumption, and general performance of the SPAD-based device. Use of SPAD- based pixels in applications such as image sensing has been limited to some extent by such characteristics of SPAD-based pixels and their operation.

Summary

In accordance with a first aspect, there is provided a photon sensing device for photon sensing comprising: a plurality of photon detectors coupled to a plurality of shift registers, wherein the plurality of photon detectors and shift registers are provided as part of a configurable circuitry configurable to combine two or more of the plurality of shift registers and to combine two or more photon detectors to form one or more combined shift registers and one or more combined photon detectors, respectively.

At least the combining of two or more of the plurality of shift registers and combining of two or more photon detectors may provide an exchange of a temporal range and/or a depth range with a spatial resolution. At least the combining of two or more of the plurality of shift registers and combining of two or more photon detectors may provide an exchange of a temporal resolution and/or a depth resolution with a spatial resolution. At least the combining of two or more of the plurality of shift registers and combining of two or more photon detectors may provide a selection of one or more of: a3 temporal range; a depth range; a temporal resolution; a depth resolution; and a spatial resolution.

The temporal range and/or depth range and/or temporal resolution and/or depth resolution may be adjustable by selecting a property of one or more clock signals, for example, a speed and/or frequency and/or period, provided to the plurality of shift registers

The temporal or depth range may comprise the maximum available temporal or depth range. The temporal or depth range may be dependent on the number of shift register elements of the combined shift register. The temporal or depth range may comprise the maximum available temporal or depth range. The temporal range may comprises a time period over which histogram bins are defined and/or photon detection events are registered within a laser cycle. The depth range may comprises a depth over which histogram bins are defined and/or photon detection events are registered, within a laser cycle.

One or more clock signals may be provided to the plurality of shift registers. A temporal or depth resolution may be adjusted by selecting a property of a clock signal provided to the plurality of shift registers. The property of the clock signal may comprise speed and/or frequency and/or period.

The temporal range of each combined shift register may comprise the number of shift register elements of the combined shifted register multiplied by a clock period. The depth range of each combined shift register may depend on the number of shift register elements of the combined shifted register multiplied by a clock period.

Combining the two or more shift registers while maintaining a clock period may increase the temporal range and/or depth range. Combining the two or more shift registers while reducing the clock period may at least maintain the temporal and/or depth resolution, optionally increase the temporal and/or depth resolution.

At least the combining of two or more of the plurality of shift registers and combining of two or more photon detectors may provide an exchange of a temporal and/or a depth resolution with a spatial resolution. The configurable circuitry may be controllable by one or more configuration signals to combine the plurality of photon detector and/or the plurality of shift registers. Combining the two or more photon detectors may comprise providing one or more configurations signals to the plurality of photon detectors. Combining the two or more shift registers may comprise providing one or more configuration signals to the plurality of shift registers.

The plurality of photon detectors may comprise a plurality of single photon detectors. The plurality of photon detectors may comprise a plurality of single photon avalanche diodes (SPADs).

The combined photon detector may comprise a group of photon detectors operating together as a single photon detector. The group of photon detectors may be operated together as a single photon detector to detect photons over a larger spatial area than each individual photon detector of the group of photon detectors. The combined photon detectors may comprise a common electrode, for example an anode, formed in response to one or more configuration signal. Combining the two or more photon detectors may comprise shorting a connection between the two or more photon detectors to form a common anode such that a photon detection event from any of the photon detectors is detected at the common anode.

The combined shift register may comprise a group of shift registers operating together as a single shift register. The single shift register may provide a longer acquisition compared to each individual shift register of the group of shift registers. Combining the two or more shift registers while maintaining a clock period may increase the temporal range and/or depth range. Combining the two or more shift registers while reducing a clock period may at least maintain or increase the temporal resolution and/or depth resolution.

The configurable circuitry may comprise signal routing circuity for the plurality of shift registers wherein the signal routing circuitry is selectively operable to route signals for the shift registers thereby to combine output signals from the one or more of the plurality of shift registers. The signal routing circuitry may comprise one or more multiplexers. Combining of the two or more shift registers may comprise selectively operating signal routing circuitry to combine output signals from the one or more of the plurality of shift registers.

The shift registers may be provided in a linear or serial arrangement. The output of a first shift register may be selectively provided to an input of a further shift register. The first shift register may be connected to a further shift register and configured to selectively provide an input of a further shift register.

The plurality of shift registers may be arranged in a chaining arrangement configurable to selectively chain two or more of the shift registers together thereby to form the one or more combined shift registers. Combining of the two or more shift registers may comprise chaining two or more of the shift registers together.

The plurality of shift registers may comprise a shift register. The plurality of shift registers may comprise a dynamic shift register.

The photon sensing device may comprise shared photon detection circuitry configurable to perform a shared recharge and/or quenching operation for each combined photon detector. Combining the two or more photon detectors may comprise operating shared photon detection circuitry to perform a shared recharge and/or quenching operation.

The photon detection circuitry may comprise at least one shared electrode. The photon detection circuitry may comprise at least one shared anode. The photon detection circuitry may comprise at least one recharge transistor between photon detectors.

The photon detection circuitry may comprise or form part of a front end for the photon detector. The shift registers are connected to the photon detection circuitry and/or front end.

The sensing device may further comprise: a shared memory module. The shared memory module may be shared between at least part of the configurable circuit. The shared memory module may be configured to store data representing spatial and/or timing and/or count information from the at least part of the configurable circuit. The shared memory module may comprise an SRAM or DRAM memory module. At least two of the plurality of shift registers may be coupled to the shared memory module, preferably at least three of the plurality of shift registers.

The shared memory module is configurable to select a data structure for storing spatial and/or timing and/or count information from the at least part of the reconfigurable circuit, wherein the data structure is selected to correspond to the temporal and/or depth resolution and/or spatial resolution of the at least part of the reconfigurable circuit

The plurality of shift registers may comprise a dynamic memory and the shared memory module comprises a static memory.

The plurality of photon detectors, plurality of shift registers and/or the shared memory block may be provided in a layered structure.

At least one of the plurality of photon detection devices and at least one of the plurality of shift registers may be provided together as part of an arrayable pixel element. The arrayable pixel element may comprise one photon detector and a corresponding shift register.

The device may further comprise a plurality of further arrayable macro-pixel elements, each macro-pixel element comprising a plurality of arrayable pixel elements together with a shared memory module.

The sensing device may further comprise further shared resources shared between two or more of the macro-pixels, for example, a gated ring oscillator.

The plurality of photon detectors and shift registers may be in a spatial distribution wherein the sensing device comprises signalling circuitry configured to provide one or more signals to the plurality of shift registers and/or the plurality of photon detectors over the spatial distribution, wherein the signalling circuitry is in an H-tree arrangement. The signalling circuitry may comprise timing signalling circuitry. The signalling circuitry may be configured to provide one or more configuration signals. The configurable circuitry may be configurable into at least a first configuration and a second configuration. In the first configuration, each combined photon detector may be coupled to a corresponding combined shift register such that combined photon detector is configured to modify the coupled combined shift register in response to a photon detection event such that the coupled combined shift register stores photon detection event information. In the second configuration, each photon detector may be coupled to a corresponding shift register such that the photon detector is configure to modify the coupled shift register in response to a photon detection event such that the coupled combined shift register stores photon detection event information.

The first configuration may comprises a first temporal resolution and a first spatial resolution. The second configuration may comprise configuration having a second temporal resolution and a second spatial resolution, wherein the first spatial resolution is lower than the second spatial resolution and the first temporal resolution is higher than a second temporal resolution.

In the first configuration two or more SPADs and/or shift registers may be combined. In the first and second configuration, the device may be configured to obtain a time of flight signal. The first configuration may be a first longer range LIDAR configuration relative to a shorter range LIDAR configuration of the second configuration.

The first configuration may be a time resolved Raman configuration. In the first configuration, the state of each shift register may represent timing and/or count information for the corresponding photon detector. The second configuration may be a fluorescence lifetime configuration. In the second configuration, the state of each combined shift register may represent timing and/or count information for the corresponding combined photon detector.

The configurable circuitry may be operable to be reconfigured within a single clock laser cycle to allow data acquisition at a pre-determined depth-related spatial and temporal resolution.

The sensing device may comprise an image sensor. The sensing device may comprises a time-of-flight sensor. The sensing device may comprise a proximity sensor. The sensing device may comprise a sensor. In accordance with a second aspect, that may be provided independently, there is provided a method of operating a photon sensing device comprising: configuring the photon sensing device, wherein configuring the photon sensing device comprises: combining two or more of a plurality of shift registers and combining two or more of a plurality of photon detectors to form one or more combined shift registers and one or more combined photon detectors, respectively. The method may further comprise operating the photon sensing device to perform a photon sensing process. The sensing device may be provided in accordance with the first aspect.

In accordance with a third aspect, there is provided a photon sensing device for photon sensing comprising: a plurality of photon detectors coupled to a plurality of data shifting circuits, wherein the plurality of photon detectors and data shifting circuits are provided as part of a configurable circuitry configurable to combine two or more of the plurality of data shifting circuits and to combine two or more photon detectors to form one or more combined data shifting circuits and one or more combined photon detectors, respectively.

The data shifting circuits are configured to be updated and/or shift data in response to a clock signal. The data shifting circuits are configured to represent count and/or timing information for one or more photon detection events. Each data shifting circuit may comprise a shift register. The data shifting circuits may be configured to adopt a state representing count and/or timing information. The data shifting circuits may be configured to adopt a state representing temporary or transitory data. The data shifting circuits may be configured to be combined by chaining together.

The plurality of shift registers may be connected to a front end of the photon sensing devices. The plurality of shift registers may be configurable to be chained and/or function together, for example, as one or more larger shift registers. The plurality of shift registers are operable to act together. The plurality of shift registers and optionally the associated signal routing circuitry may be operable to act together in a parallel in serial out (PISO) or serial in parallel out (SIPO) mode or parallel in parallel out (PIPO) mode. The plurality of shift registers may be configurable to be chained together and used in a parallel or serial loadable fashion. The plurality of shift registers may be connected to corresponding front ends of the plurality of photon detectors. The device may further comprise a shared memory, for example, a SRAM device. The shared memory may be coupled to the one or more shift registers.

The device may be operable in a number of imaging modes, including high dynamic range (HDR), direct time of flight (dToF) and gated imaging.

In accordance with a further aspect, there is provide a device comprising a plurality of photon detectors, a shared memory module, for example, a SRAM device and one or more clocked shift registers configured to be chained and used in a parallel or serial loadable fashion.

In accordance with a further aspect there is provided a photon sensing device for photon sensing comprising a plurality of shift registers connected to a photon sensing device front end, for example, a SPAD front end, wherein the plurality of shift registers are operable to act together in a parallel in serial out (PISO) or serial in parallel out (SIPO) mode or parallel in parallel out (PIPO) mode. The device may further comprise a shared memory. The shared memory may be coupled to the one or more shift registers.

The device may be operable in a number of imaging modes, including HDR, dToF and gated imaging.

Features in one aspect may be provided as features in any other aspect as appropriate. For example, features of the device may be provided as features of a method and vice versa. Any feature or features in one aspect may be provided in combination with any suitable feature or features in any other aspect. Brief description of Drawings

Various aspects of the invention will now be described by way of example only, and with reference to the accompanying drawings, of which:

Figure 1 is a schematic diagram of a sensing device, in accordance with an embodiment;

Figure 2 is a schematic diagram of part of the sensing device of Figure 1;

Figures 3 to 6 are circuit diagrams of part of a sensing device, in accordance with embodiments;

Figure 7 is a schematic diagram of combining circuitry for a plurality of photon detectors, in accordance with an embodiment;

Figures 8(a) and 8(b) are schematic diagrams of a 4x4 photon detector array, in a first and a second configuration, in accordance with an embodiment;

Figure 9 is a schematic diagram of a pixel architecture of a sensing device, in accordance with a further embodiment;

Figure 10 is a schematic diagram of a photon sensing device, in accordance with a further embodiment;

Figure 11 is a diagram of a circuit layout for signalling circuitry, in accordance with an embodiment;

Figures 12 to 16 are timing signal diagrams for operation of the sensing device, in accordance with embodiments, and

Figures 17 to 20 are circuit diagrams of part of a sensing device, in accordance with embodiments.

Specific Description

Figure 1 is a schematic diagram of a photon sensing device 10, in accordance with an embodiment. The sensing device 10 is a configurable sensing device. The sensing device may be referred to as a sensor. The sensing device 10 can be considered to be formed by arrayable elements arranged in a hierarchy. In this embodiment, the sensing device is formed by a first type of arrayable element, referred to as a macro-pixel and the macro-pixel itself may be considered to be formed of a second, smaller, type of arrayable element, referred to as a single photon avalanche diode (SPAD) pixel or simply a pixel. As described in the following, the sensing device 10 can therefore be considered as a hierarchy of modules/arrays from a pixel/SPAD level to a macro-pixel level and shared circuity may be provided at the different levels of the hierarchy (for example, shared circuitry may be provided per-pixel, per-macro-pixel or shared between groups of macro-pixels).

Figure 1 depicts the sensing device 10 having a plurality of macro-pixels 11 arranged in an array. Figure 2 is a schematic diagram of a typical macro-pixel 12 of the sensing device 10. While only two macro-pixels 12a and 12p of the plurality of macro-pixels 11 are labelled in Figure 1 , it will be understood that each macro-pixel of the device substantially corresponding to macro-pixel 12. The macro-pixel 12 has a number of SPADs provided together with per-SPAD circuitry (the SPAD and per-SPAD circuitry is also referred to together as a SPAD pixel, or simply as a pixel). It will be understood that each SPAD pixel 14a, .. 14n has the same components and circuitry and therefore, for brevity, only the first pixel 14a is described in the following.

In detail, pixel 14a has a single photon avalanche diode (SPAD) 16a and associated circuitry 18a. The associated circuitry 18a may comprise circuitry for sampling and holding a voltage level, circuitry for resetting the SPAD, circuitry for quenching the SPAD, and/or the like. In addition, the pixel 14a has a per-SPAD state memory circuitry 20a. In the described embodiments, the state memory circuitry 20a for each SPAD includes a dynamic shift register. The state memory circuitry may also be referred to as a state memory element. The collection of dynamic shift registers for the device may be considered to form a dynamic memory.

The plurality of SPADs, at least part of their associated circuitries and the state memory circuitries of the device are provided as part of a configurable circuitry that is a circuitry controllable using one or more control signals to place the SPADs and state memory circuitries into one of a number of configurations. The configurable circuitry is controllable to combine the plurality of SPADs and state memory circuities to allow for an exchange of temporal and/or depth range and/or resolution with a spatial resolution.

In further detail, the configurable circuitry has SPAD combining circuitry 22 operable to combine one or more SPADs and optionally part of their associated circuitry, to from one or more combined SPADs. The configurable circuitry also has state memory circuitry combining circuitry 24 operable to combine one or more memory circuitries to form one or combined memory circuitries. The combining circuitries extend between the different pixels of the macro-pixel to allow for reconfiguration of the SPADs and memory circuitries across the macro-pixel. It will be understood that, in the present embodiment, the configuration of pixels is performed during before sensing (i.e. before data acquisition/detection). The combining circuitries 22 and 24 are described in further detail with reference to the remaining Figures. The macro-pixel also has a controlling circuitry for receiving configuration signals and for controlling the combining circuitry 20 thereby to reconfigure the SPADs/memory elements. The configurations signals may also be referred to as control signals.

Other examples of temporary or transitory memory circuits may be used in further embodiments. For example, a data shifting circuit configured to shift data, for example, in response to a clock signal and configured to be combined by chaining may be suitable. Such data shifting circuits may be configured to represent count and/or timing information for one or more photon detection events, for example, the data shifting circuits may be configured to adopt a state representing count and/or timing information. The data shifting circuits may be configured to adopt a state representing temporary or transitory data. The data shifting circuits may be configured to be combined by chaining together.

In the present embodiment, the combining circuitries extend between the different pixels of the macro-pixel to allow for reconfiguration of the SPADs and memory circuitries across the macro-pixel. In alternative embodiments, the combining of SPADs and memory circuitries is not limited to a macro-pixel and the combining circuitries may be provided across the device.

For the purposes of the following description a combined SPAD can be considered to be a group of SPADs that operate collectively such that during a detection period, any one of the group of SPADs can detect a photon. Combining a group of SPADs into a larger combined SPAD will increase the detection area of the combined SPAD (the combined SPAD will be operable to detect photons across a greater spatial area than the individual SPADs) thus leading to a decrease in spatial resolution for the macro- pixel/device. Together with the combining of SPADs, their corresponding state memories are also combinable into a combined state memory. When the SPADs are combined, the common anode will fire when a first photon hits any one of the combined detectors. All VSPAD voltages will respond with a simultaneous pulse no matter which of the SPADs that have been combined receives that photon. When the SPADs are used individually each SPAD responds in an uncorrelated way to the photon striking its own active area.

In embodiments in which the state memory is a shift register, in a configuration in which each individual shift register is paired to its associated pixel SPAD, each individual dynamic shift register is configured such that, in operation, the associated SPAD or another SPAD coupled to the shift register is configured to provide a signal to the shift register in response to a photon detection event, such that the shift registers captures event count or event timing information for the photon detection event. The count or timing information for the photon detection event is represented by the final state of the shift register after a period of time. By combining two or more shift registers together, a combined or extended shift register is formed thus allowing collection of photon detection event information with a greater time resolution and/or over a longer range.

For example, the shift register will contain or represent a binary string pattern (for example, a pattern such as “111000”) where the position of the transition from a 1 (SPAD fired in response to a photon) to a 0 (SPAD didn’t yet detect a photon and still in reset state) represents the time from the start of the clock operating the shift register which is synchronised to the laser pulse. The time offset of the photon event from the start of clocking can be calculated by multiplying the number of 1s in the binary string pattern times the clock period is the time offset of the photon event from the start of clocking.

As an example, a group of SPADs are combined together to form a combined SPAD and their corresponding shift registers are combined to form a corresponding combined shift register. In operation, a signal from the combined SPAD is directed to the combined shift register such that the state of the combined shift register at the end of a period of time (also referred to as an acquisition period) represents the timing/event information for a photon detection event detected by the combined SPAD.

The macro-pixel 12 also has a shared memory 26 and associated circuitry including memory addressing and readout circuitry 28 and memory incrementing circuitry 30. The memory addressing and readout circuitry includes overflow circuitry and precharge read and write circuitry, described in detail with reference to Figure 9. The shared memory may be referred to as a shared memory module. The shared memory 26 is a static memory, in the present embodiment, a SRAM. The shared memory 26 may comprise an array of SRAM elements. The shared memory 26 is configured to store photon detection event information or other photon timing information transferred from the memory circuitries of the pixels after an initial event acquisition process. Alternative memory implementations may be employed. While the above embodiment uses SRAM, 1T1C or Gain Cell DRAM is also possible necessitating refresh cycles which can be readily implemented by forcing update of all circuitries at a chosen repetition rate. Memory using Phase Change, STT-RAM, MRAM, FeRAM is also possible.

In some embodiments, the shared memory module is configurable to select a data structure for storing spatial and/or timing and/or count information from the at least part of the reconfigurable circuit. The data structure may be selected to correspond to the operational mode of the sensing device, for example, to have a data structure corresponding to the temporal and/or depth resolution or range and/or spatial resolution of the at least part of the reconfigurable circuit.

Turning back to Figure 1, the sensing device 10 has an array of such macro-pixels. The macro-pixels are arranged in sub-arrays. Figure 1 depicts four sub-arrays (40a, 40b, 40c, 40d). Each sub-array has associated circuitry shared between its macro-pixels. For clarity, Figure 1 depicts, the shared circuitry for the first sub-array 40a and it will be understood that each sub-array has associated circuitry. Sub-array 40a has sixteen macro-pixels (12a, ... , 12p) each macro-pixel substantially corresponding to the macropixel 12 described with reference to Figure 1. The sub-array 40a also has associated circuitry, for example, memory addressing circuitry 41 and clock management circuitry 42.

The sensing device 10 also has device circuitry including a serial control interface 44, stop clock and gate generation circuitry 46, addressing control circuitry 48, readout control circuitry 50 and processing and readout circuitry 52. The device circuitry can be considered to be shared between the sub-arrays of macro-pixels.

While Figure 1 depicts 16 macro-pixels in each sub-array and 64 macro-pixels in total, it will be understood that such an arrangement is a non-limiting example and different numbers and configurations of macro-pixels may be used in alternative embodiments. In addition, it will be understood that each macro-pixel can have a different total numbers of SPADs and pixels and such pixels can be arranged in alternative configurations.

Figure 3 depicts an SPAD pixel 200 in accordance with an embodiment. It will be understood that the SPAD pixel 200 forms part of a sensing device such as sensing device 10 descried with reference to Figure 1 and 2. As described with reference to Figures 1 and 2, the pixel is an arrayable element that forms part of a sensing device and may form part of a larger arrayable element, for example, a macro-pixel. In the embodiment of Figure 3, the pixel 200 is one of N pixels forming a macro-pixel.

The example pixel 200 comprises a SPAD 202. As is known in the art, operation of the SPAD 202 is based on a p-n junction of the SPAD 202 being biased beyond its breakdown region, known as operation within a ‘Geiger’ region. A high reverse bias voltage generates a sufficient magnitude of electric field such that a single charge carrier introduced into a depletion layer of the SPAD 202 may induce development of a self-sustaining avalanche current, due to impact ionization caused by one or more incident photons. In use, the avalanche may be ‘quenched’ by a quench circuit to allow the SPAD 202 to then be reset, thereby enabling further detection of photons.

In the example pixel 200, a cathode of the SPAD 202 is coupled to a high voltage supply line, denoted VHV. An anode of the SPAD 202 is coupled to a recharge transistor 204 configurable by a signal Vcas coupled to a gate of the recharge transistor 204 to recharge the SPAD 202. A clamp diode 206 is provided to limit an excess bias voltage generated across the SPAD 202, preventing damage to the SPAD 202 in use. The clamp diode 206 is provided with a voltage signal Vclamp.

The recharge transistor 204 is gated by a first quench transistor 208 and a second quench transistor 210 arranged in series. A common anode connection 212 is provided between the first and second transistors. A gate of the first quench transistor 208 is controlled by a quench signal referred to as a “Recharge” signal. A gate of the second quench transistor 210 is controlled by a “common recharge” signal. The quench resistors may also be referred to as recharge transistors. By controlling the Common signal, quenching of the SPAD can be performed using either the first or the second quench transistor. In a first mode, the first quench transistor is used to allow individual quenching of each SPAD. In a second mode, the second quench transistor is used to allow simultaneous quenching of two or more SPADS (thus forming a combined SPAD). In some embodiments, a common electrode is provided.

Recharge transistor 204 is a cascode transistor aimed at extending the excess bias at which the SPAD can operate by shielding the transistors at its source from the high voltage excursions (equal to the excess bias voltage) due to the SPAD firing. Higher excess bias voltages may be desirable as they allow the photon detection efficiency of the SPAD to be extended.

The pixel 200 also has a dynamic shift register 214 comprising a cascade of M D-type flip-flops (216a, ... , 216m). The flip flops can be considered to be state memory elements or shift register elements. The output of each flip-flop is connected to the input of the next flip-flop. Each flip flop is configured to receive a clock signal (Clk). The final flip-flop in the shift register is configured to receive a reset signal (RstN) to reset the shift register. The dynamic shift register shares a single clock signal causing the data stored to shift along the dynamic shift register. The RstN signal is generated globally for the whole array and synchronised to the laser pulse. This allows the shift register chain to be flushed or reset prior to each laser pulse ready to acquire a new laser return from a target. As described in the following, after each laser cycle the shift register contents are transferred and accumulated into the shared, SRAM memory. In the present embodiment, the maximum temporal range available for binning or registering photon detection events offered by a shift register is the number of shift register elements multiplied by the clock period. For a combined shift register the maximum temporal range is the number of combined shift register elements of the combined shift register multiplied by the clock period.

The shift register 214 is coupled to a 2:1 (two input, two outputs) multiplexer 218. The shift register provides one of the inputs to the multiplexer 218. The signal read from the each shift register (the ith shift register) is denoted Q<M,i> and is a word having an M size. In each SPAD pixel there is an M-bit shift register. When combined and chained into an N-pixel macropixel, the total length of the combined shift register is NxM. An SRAM memory word is provided for each of the bits in the combined shift register in the shared memory, and therefore the shared memory provides NxM per macropixel. The other input to the multiplexer 218 is provided from a further SPAD pixel provided in the macro-pixel. The further SPAD pixel (not shown) is provided in a chaining arrangement (an example chaining arrangement is depicted in Figures 8(a) and 8(b)) with the SPAD pixel 200. The input signal from the preceding SPAD pixel (the i-1 th pixel) to the multiplexer is denoted C<i-1>. The output signal from the multiplexer for this SPAD pixel (the ith pixel) is denoted C. A chain signal 220 is provided to the multiplexer.

Once configured and/or reconfigured, the sensing device is operable to perform a photon sensing process. Operation of the sensing device from of pixels such as pixel 200, may be described in terms of a first configuration phase and a second data acquisition phase. The data acquisition phase may in itself be described in three phases: an event detection phase, an event transfer phase and a data read phase.

In the configuration phase, control (or configuration) signals are provided to each macro-pixel to place the macro-pixel into one of a number of configurations. The configurations or control signals include the Recharge and Common signals described above. As an example, operation of the sensing device in two non-limiting configurations are described in the following. The configuration of the SPADs and shift registers is determined a-priori by external control signals depending on the type of photon events which are desired. For example, high temporal, high spatial frequency or low temporal, low spatial frequency sensing may be possible.

Other combinatorial combinations may be possible, for example: high temporal and low spatial frequency (HL) and low temporal and high spatial frequency (LH). As described above, the spatial frequency part is just controlled by operating with common SPAD anode/chained shift register or individual SPAD anode/unchained shift register thereby selecting spatial resolution. The temporal resolution is controlled by the frequency of the clock applied to the shift register. As a non-limiting example, a clock in 10GHz range (with 100ps time bin steps) may be suited for short range time of flight where total return time from a few meters is in few nanoseconds range. As a further nonlimiting example, for LIDAR application, the clock may be in 100s MHz range with bin steps in nanosecond range for return times in 100s nanosecond for 10 to 100s of metres distance. It will be understood that combinatorial cases can be created by combining SPADS and shift registers (by commoning or shorting electrodes and chaining shift registers) and applying high or low frequencies to shift register clocks.

It will be understood that there is a distinction between operation and configuration control that implements reconfiguration. For example, a photon detection event will triggers a sequence of moving of bits around during data acquisition. In addition, some bits move around when control signals change in order to reconfigure the hierarchy of pixels and shift registers when tuning the temporal versus spatial resolution. The data acquisition may therefore be understood as dependent on the configuration of the device. In addition, each configuration may therefore be considered as a separate state machine with the configuration being static during any particular operation.

The first configuration described is where each individual SPAD is paired to its corresponding shift register thereby to offer the maximum spatial resolution and, correspondingly, the minimum time resolution for the device.

By controlling a voltage level at the Common Anode (the Common signal) each SPAD of the pixel may be either recharged individually (using the combination of recharge transistor 204 and first quench transistor and 208) or collectively as part of a group of SPADs forming a combined SPAD (using the combination of recharge transistor 204 and second quench transistor 210).

In further detail, in the first configuration, the common anode coupling the SPAD circuitry together is at a voltage such that the first quench transistor, for each pixel, is grounded. In such a configuration, the second quench transistor is not used, and thus the recharge and first quench transistor are operable to recharge each SPAD individually.

For this mode, during the event detection period, in a configuration, when the SPAD 202 fires, the SPAD generates a voltage VSPAD. The signal VSPAD is provided to the input of the shift register thus registering as a digital bit in the first flip flop. As the detection period continues, the digital bit is successively moved along the shift register at successive clock signals. The state of the shift register at the end of the detection period therefore represents timing information for a photon detection event. It will be understood that each SPAD can fire only once during the event detection period, as the SPAD must be recharged by the recharge transistor.

As will be described with reference to Figures 12 to 16, a clock is generated at a high acquisition rate (10 Mhz) to capture the instant that the SPAD fires. As it is not possible to write information from the SPAD at this rate the timing information is, instead, collected in the shift register and written to the SRAM. Therefore, at the end of the event detection period, a chain signal is provided to each multiplexer to read out the individual information stored in each shift register. During the subsequent data write period, the timing and count information stored in each shift register is written to the SRAM.

In the first configuration, the SRAM is configured to store N words (one word for each SPAD), where each word has M bits. In some embodiments, the shared memory is configured to receive the counts from each individual SPAD and store the counts as words in the memory. In such an example, the memory is configured to store a first count associated with the first pixel, a second count associated with the second pixel up to a N count associated with the Nth pixel. As an example, there are an equivalent number of spaces in the SRAM memory for each SPAD/shift register, therefore, each SPAD writes one word in a specific time window. In such an operation, for each memory location, the state of each shift register corresponds to a SPAD event for each SPAD. The state of each shift register is then read in series and the state of each shift register is stored in SRAM. The adder is then incremented to then move to the next memory location.

During a third phase, the data stored in the SRAM is then transferred from the sensing device to an external device, by operation of the address controller.

The above description related to a configuration in which each individual SPAD and associated circuitry is coupled to a corresponding shift register. As described with reference to Figures 1 to 2, the SPADs may be combined into groups of two or more to form combined SPADs and respective combined shift registers. In the following, the operation of a non-limiting example configuration (the second configuration) in which all SPADs of a macro-pixel are combined is described. In this second example configuration, the spatial resolution is reduced however, the maximum temporal (or depth) range for the device is extended.

In the second configuration, the common anode is held at a voltage level such that the first quench transistor is effectively by-passed. In such a configuration, the first quench transistor is not used, and thus the recharge and second quench transistor are operable to recharge the SPADs collectively. In such a configuration, the shift registers of the macro-pixel are combined into a single combined shift register. When one SPAD of the group of SPADs fires, the firing SPAD generates a voltage VSPAD. This signal VSPAD is provided to the input of the combined shift register thus registering as a digital bit in the first flip flop of the combined shift register. As the detection period continues, the digital bit is successively moved along the shift register at successive clock signals. The state of the combined shift register at the end of the detection period therefore represents timing information for a photon detection event for the combined SPAD. The combined shift register thus stores timing and/or count and/or event information for the combined SPAD.

It will be understood that only one SPAD of the group of SPADs can fire in response to a photon detection event during the event detection period, and all SPADS forming the combined SPAD are recharged using the second quench transistor by provision of a Common signal to the second quench resistor.

At the end of the event detection period, a chain signal is provided to the multiplexers to obtain the timing and/or count and/or event information for the combined SPAD. During the data write period, the information stored in the combined shift register is written to the SRAM. As combined data is being obtained from the combined SPADs/shift registers the allocation of memory in the SRAM is different to the first configuration.

During a third phase, the data stored in the SRAM is transferred off device to an external device, via operation of an address controller.

Figures 4 to 6 are non-limiting examples of SPAD pixels, in accordance with further embodiments. Each of the SPAD pixel circuits depicted in Figure 4 to 6 operate substantially the same as the SPAD pixel circuit of Figure 3. In further detail, Figure 4 is a 4 bin indirect time of flight (iToF) example. Figure 5 is a 2 bin iToF example. Figure 6 is a pixel suitable for a photon counting image sensor.

Each of Figures 4 to 6 have a number of features common with Figure 3, in particular, the SPAD combining circuitry (for example, including the commonAnode and shared quenching circuitry) and the signal routing circuitry for the shift registers. It will be therefore be understood that each of the example pixels of Figures 4 to 6 can be arranged into larger macro-pixel arrays, substantially as described with reference to Figure 2.

In further detail, Figure 4 depicts a 4 bin indirect time of flight (iToF) embodiment. Figure 4 is a SPAD pixel 300 having a SPAD 302, a recharge transistor 304, a clamp diode 306, a first quench transistor 308, a second quench transistor 310, a common anode connection 312, a dynamic shift register 314 comprising a cascade of 4 D-type flip-flops (316a, ... , 316m) and a multiplexer 318. A chain signal 320 is provided to the multiplexer 318.

Figure 5 is a 2 bin iToF example. Figure 5 depicts a SPAD pixel 400 having a SPAD 402, a recharge transistor 404, a clamp diode 406, a first quench transistor 408, a second quench transistor 410, a common anode connection 412, a dynamic shift register 414 comprising a cascade of 2 D-type flip-flops (416a, ... , 416m) and a multiplexer 418. A chain signal 420 is provided to the multiplexer 418.

Figure 6 is a pixel suitable for a photon counting image sensor. Figure 6 depicts a SPAD pixel 500 having a SPAD 502, a recharge transistor 504, a clamp diode 506, a first quench transistor 508, a second quench transistor 510, a common anode connection 512, a dynamic shift register 514 comprising a D-type flip-flop 516a and a multiplexer 518. A chain signal 520 is provided to the multiplexer 518.

Figure 6 depicts a pixel suitable for a photon counting image sensor. In this example, only one D-type and a multiplexer required per SPAD. This allows for very small ~3pm pixel pitches matching latest SPAD technology without needing further logic scaling. This pixel can achieve simple gated time binning or quanta image sensor performance. It is also noted that, that direct Time of Flight implementation with large M is possible.

In some embodiments, direct time of flight implementation requires M=1 ,2,4 or 8.

Figure 7 depicts a sensing device with four SPAD pixels 700a, 700b, 700c, 700d, in accordance with an embodiment. It will be understood that Figure 7 does not depict the corresponding memory state elements of each pixel, for clarity. As can be observed in Figure 7, each SPAD 702a, 702b, 702c, 702d has a corresponding recharge transistor 704a, 704b, 704c, 704d, a corresponding clamp diode 706a, 706b, 706c, 706d, a corresponding first quench transistor 708a, 708b, 708c, 708d and second quench transistor 710a, 710b, 710c, 710d. Each SPAD circuit is coupled to the common anode 712 at a point between its respective first and second quench transistor.

With reference to Figure 7, to combine SPADs in this embodiment, the anodes of multiple SPADs are shorted together to from an effectively larger SPAD. In this embodiment, this is achieved by setting the Recharge signal to a logic high voltage and the Common signal is pulsed briefly at the beginning of a laser period to recharge (in the high-Z recharge mode) or set to a DC voltage slightly above the threshold voltage of the NMOS to place that device into a high impedance linear region for passive quenching. In the former case, the SPADs act as a single larger device and will fire on the first photon incident in any of the anodes. The voltage from the effectively larger device will appear identically at all VSPAD<0> to VSPAD<3> nodes. as they are now short circuited together by the constant high state of the Recharge signal.

Fig. 7 shows case of 4 SPADs in a macopixel. In the operating mode in which the SPADs are not combined but operate individually the Common signal is set to a logic high voltage shorting all the Common signals to ground and recharge signal is either pulsed (high Z recharge) or set to a de voltage slightly above threshold to bias the devices to act as per-SPAD passive quench transistors. In the latter case all SPADs are isolated from each other and can pulse individually from different photon arrivals,

Figures 8(a) and Figure 8(b) depicts a sensing device in accordance with a further embodiment, in a first and a second configuration. The sensing device of Figure 8(a) and 8(b) has 4x4 SPAD pixels. Each pixel has a SPAD and associated SPAD circuitry, as described above. Each pixel also has a memory state circuit in the form of a shift register (in this embodiment, the shift register is a single D-type flip flop). With regard to the shift register, each pixel is provided with part of a single routing circuitry, namely a multiplexer. Each multiplexer is operable by one or more control signals. Considered together, the multiplexers for each SPAD forms signal routing circuitry for the SPADs. As described in the following, the signal routing circuitry is configured to route signals for the shift registers thereby to combine output signals. With regard to the SPADs, each SPAD is provided together with first and second quenching transistors coupled via a common anode, providing part of a SPAD combining circuitry, as described above.

Figure 8(a) and 8(b) also illustrates the SPAD combining circuitry. In Figure 8(a), the common anode coupling the SPAD circuitry together is at a voltage such that the first quench transistor, for each pixel, is grounded and each SPAD is operable to be triggered independently from the rest. In Figure 8(b), the common anode coupling the SPAD circuitry together is at a voltage such that the first quench transistor, for each pixel, is effectively bypassed and the SPADS are operable to be triggered as a group.

As depicted in Figure 8(a) and 8(b), each shift register and its respective multiplexer is provided in a chaining arrangement to form a chained or combined shift register. The combined shift register is therefore operable to combine the shift registers into distinct groups. The shift registers can be considered to be in a serial arrangement in which each shift register is connected to its subsequent and preceding shift register. Such an arrangement may also be referred to as a linear arrangement as the shift registers may define a signal path through the array. The shift registers can be considered to be in a serial arrangement in which each shift register is connected to its subsequent and preceding shift register. In Figure 8(a) all sixteen shift registers are chained to form an extended or combined shift register. The output of the combined shift register is delivered to the shared memory. In this configuration, the shared memory is configured to have 1 bin per pixel. In the first configuration, the SPADs operate individually, such that, the output is attributable to the SPAD which fired.

In further detail, each SPAD is provided together with a respective shift register and multiplexer. While Figure 8(a) and 8(b) depicts a shift register having a single flip flop, it will be understood that other sizes of shift register may be provided for each SPAD. Each multiplexers is a 2 to 1 (two inputs, one output) multiplexers controllable using a single select line. The output of the shift register for each SPAD is connected to an input of the corresponding multiplexer for the SPAD. The output of the multiplexer is connected to the subsequent multiplexer in the series (the multiplexer for the subsequent SPAD in the array). The subsequent multiplexer in the series thus receives as an input from the preceding multiplexer and the shift register of the subsequent multiplexer.

While Figure 8(a) and 8(b) depicts the signal routing circuitry and SPAD combining circuitry connecting the pixels row-wise, it will be understood that, in other embodiments, the signal routing circuitry may connect the shift registers column-wise. In further embodiments, the signal routing circuitry and SPAD combining circuitry may be such that any group of SPADs can be combined.

Figure 9 depicts a pixel architecture for a sensing device in accordance with a further embodiment. Figure 9 depicts the sensing device in terms of three modules. The first module 102 relates to per-pixel circuitry. The second module 104 relates to circuitry provided per macro-pixel. The third module 106 relates to circuitry shared between a number of macro-pixels. It will be understood that a number of the elements of the sensing device 100 of Figure 9 correspond to the elements described with reference to Figure 1 and Figure 2.

The first module 102 has N SPADS (in the present embodiment, each SPAD is provided as part of a separate pixel). As described with reference to Figure 10, the SPADs are provided in a top-tier or layer of the sensing device.

The first module 102 also has associated circuitry for each SPAD, in particular, a Front end. The first module thus has N SPAD front-ends. The term “SPAD front-end” will be understood to refer to circuitry associated with a SPAD. For example, such associated circuitry may comprise circuitry for sampling and holding a voltage level, circuitry for resetting the SPAD, circuitry for quenching the SPAD, and/or the like, as described in more detail below. In the present embodiment, each front end may be considered to operate as a high-Z front end.

High-Z refers to the operation of the gate voltage of the quench or recharge transistor which can be either 208 or 210 here depending on the mode. When a SPAD is operated in High-Z mode a logic pulse is applied to the gate forcing the SPAD into a recharge condition (when high signal state) or into a high impedance state “High-Z” whereby the armed “low” state of the SPAD is memorised on its own capacitance. When the SPAD fires it fires to a “high” state whereby the fired state is memorised on the SPAD’s own capacitance and the SPAD cannot fire again until recharged by a pulse applied to the gate of the recharge transistor 208 or 210. This is in comparison to “passive” quenching or recharge whereby a de level is placed on the quench or recharge transistor allowing the SPAD to fire and quench independently and asynchronously of any clock and do so multiple times on reception of multiple photon arrivals at different times.

For an individual SPAD to produce a useful output, a component to quench or recharge is required, as described with reference to, for example, Figure 3. Further components can be added to gate the SPAD event and to memorise the state of the SPAD. It will be understood that, in the case of highest spatial resolution to have an individual output from each SPAD such components are not shared. However, they are combined when configured to operate a group of SPADs together as a combined SPAD (for example, all SPADs in a macro-pixel).

The first module also has N dynamic shift registers 112, such that each SPAD is provided together with a corresponding dynamic shift register. The shift registers are M stage shift registers (i.e. having M shift register elements). The first module also has signal routing circuitry including N multiplexers provided in a chaining arrangement 114. The signal routing circuitry can be considered to form part of the state memory combining circuitry described with reference to Figures 1 and 2.

In the described embodiments, shift register elements in the form of D-type flip flops are described. It will be understood that both dynamic and static flip-flops may be used. In some embodiments, alternative shift register elements configured to store a single bit may be used.

Turning to the second module 104, the second module 104 has a shared memory 118 (corresponding to shared memory 26 of Figure 2), overflow circuitry 116, precharge read and write circuitry 120 and readout tri-state circuitry 126 (together corresponding to memory addressing and readout circuitry 28) and incrementing circuitry 122 (corresponding to memory incrementing circuitry 32).

The most-significant bit of each SRAM word is considered an overflow bit. If any one of those bits is set then the SRAM integration scheme which is building the time of flight histogram is set to overflow and start wrapping around in the binary counting space. This may leading to corruption of the histogram and additional power consumption of the SPADs in the pixel array as they will continue to fire and cause pixel arithmetic and clocking operations to proceed. The D-type flip flop of the overflow circuitry 116, detects any single most significant SRAM word and memorises the condition of memory overflow causing the pixel recharge pulses to be inhibited until a global ExtRecharge signal is asserted at the beginning of a frame. This may offer power savings as the SPADs will not continue to be reset and draw charge on each photon from the high voltage bias.

In further detail, the shared memory 118 is depicted as an “N x M x k bit memory”. When data is transferred from the temporary storage in the shift register to the shared memory, the shift register is operated with a different clock signal (a different frequency) that is commensurate with the memory read-write-modify timing. In some embodiments, the output of the shift register may also optionally fed into a circuit which detects a toggled state of the SPAD and increments the state of a memory word. Each memory word corresponds to a SPAD (or a group thereof) and an element of the shift register (or time bin). K is the bit depth of each SRAM word. It allows 2 to the power k minus 1 photons to be counted at each time offset in the histogram range

The memory incrementing circuitry has an LFSR shifter and XOR feedback. The LFSR solution requires an external decoder but is more compact as provided with the macropixel thereby reducing need for sharing allowing smaller N. In alternative embodiments, the memory incrementing circuitry may be include a binary chain of half adders.

Turning to the third module 106, the third module has an address controller 128 (corresponding to memory addressing circuitry 41 of Figure 1) and a gated ring oscillator 130. The address controller 128 is configured to transmit an access signal (Access <N*M- 1 :0>) to the SRAM 118. The shared gate ring oscillator 130 generates clock signals for the pixels and forms part of a clock management circuitry (corresponding to clock management circuitry 42 of Figure 2).

With reference to Figure 2, Figure 9 does not depict device circuitry including serial control interface 44, stop clock and gate generation circuitry 46, addressing control circuitry 48, readout control circuitry 50 and processing and readout circuitry 52 is not shown.

As indicated in Figure 9, the first module is configured to receive a number of control signals. In particular, the front ends 110 receive a Common signal. The Common signal may also be referred to as a CommonRecharge signal. The dynamic shift registers are also configured to receive a clock signal from the clock management circuitry. The multiplexer arrangement is also configured to receive a chaining signal (“Chain”). The second module is further configured to receive a number of control signals. In particular, the memory is configured to receive an access signal. The increment circuitry 122 is configured to receive a clock signal from the clock management circuitry. Chain is a global signal for the pixel array which will be asserted when a lower spatial resolution and/or higher bin depth mode is desired. The pixel array will have a state controller (in some embodiments, the signal could also come from off- chip) which also needs to control the use of the Common and Recharge signals. In some embodiments, chain and common are applied at the same time.

The CommonRecharge signal may provide a wired OR of the SPAD signals, for example, in a direct time of flight mode. However, in some embodiments, similar functionality may be provided by connecting a N input OR gate to the outputs of the SPADs (i.e. signals SPAD<0:N-1>).

Not shown in Figure 9 is timing signal circuitry in the form of an H-tree arrangement. The timing signal circuitry is described in further detail with reference to Figure 11. The timing signal circuitry provides an external clock signal (ExtCIk) signal and a Win signal to the clock management circuitry. The clock management circuitry is configured to receive a ClkSel signal to select between an ExtCIk signal from the H-tree arrangement or a Clklnt signal from the gated ring oscillator. The clock management circuitry is controllable to operate in different modes as described in further detail in the following. For Raman applications, a shared gated ring oscillator is configured to generate the higher frequency clock signals required. For example, the shared gated ring oscillator provides 10GHz clocks required for 100ps bin resolution for Raman. Distribution of such high frequency clock signals may be difficult and power hungry via the H-tree arrangement. The gated ring oscillator is shared between P macro-pixels to reduce its power consumption per SPAD. For Raman applications, the gated ring oscillator is enabled for only very short time intervals (for example, a few ns) around the Raman signature allowing on-chip decoupling to absorb a lot of the inrush current preventing IR drops. In such embodiments, the lower frequency START, Chain and MemCIk signals are distributed by the timing balanced Fltree arrangement.

For indirect time of flight applications, the H-tree provides uniform sampling of the laser pulse information over the entire pixel array. An imager with a few shift register bits forms a compact indirect time of flight pixel for high resolution imagers without needing extreme logic scaling at advanced nodes. The pixel is laser power efficient as the shift registers are only operated to capture photons immediately after the laser pulse. The remainder of the time until the next laser pulse the data is being transferred from dynamic to static memory and the 1/r^A2 property means no returning photons are available from the laser.

Figure 10 depicts a sensing device 1000 in accordance with a further embodiment. Figure 10 shows the hierarchal structure of the device. It will be understood that Figure 10 depicts tiers of a hierarchy rather than a level in the sense of a layer in a stacked sensor. Bottom tier is a SPAD pixel, the next tier is a macropixel, next is group of P- macropixels sharing a common timing generator and next tier is whole pixel array and image sensor with readout.

On a first, upper level 1004 of the hierarchy (also referred to as a top-tier) the sensing device has a plurality of SPADs. The upper level may be considered as provided on an outer or external facing surface to allow detection of photons. In this embodiment, the SPADS are provided as part of a macro-pixel. At the lowest tier 1002 (also referred to as the bottom-tier) circuitry for the SPADs is provided. In particular, at the lowest level, SPAD pre-pixel circuitry (corresponding to associated circuitry 18a and state memory circuitry 20a of Figure 2). It will be understood that, the pixel circuitry includes individual recharge circuitry (including recharge transistors) and shift register D-types. Also provided at the lowest layer is shared macro-pixel circuitry (circuitry shared between the NxN SPADs at the corresponding position in the upper layer) including shared memory (corresponding to shared memory 26), memory read/write controller (corresponding to memory addressing circuitry 28) and incrementing circuitry (referred to as an arithmetic logic unit or ALU also corresponding to memory incrementing circuitry 30).

At an intermediate level 1006 (between the upper tier and lower tier) is provided an Fltree arrangement substantially as described with reference to Figure 11. The intermediate tier also includes circuitry shared between an array of P macro-pixels. This shared circuitry includes memory addressing circuitry (corresponding to the address controller 41 of Figure 2) and clock management circuitry (corresponding to clock management circuitry 44 including a shared gated ring oscillator). The clock management circuitry provides a memclock signal to the macro-pixels.

The device also has a serial control interface, STOP clock and gate generation circuitry, addressing control circuitry, readout control circuitry and processing and readout circuitry substantially as described with reference to Figure 2. These further components serve the operation of the sensing device. In the present embodiment, the array of SPADs are addressed row-wise and read column-wise. The STOP clock and gate generation circuitry and row addressing circuitry. The sensing device further includes column readout control and further processing circuitry and data pads. The device-wide serial control interface is provided for receiving and sensing external control signals.

It will be understood that each macro-pixel (having NxN SPADs) may be represented as having a width of X microns. Thus the pitch of the NxN SPADs is X/N microns. Typical, non-limiting values of X are 10 microns, however, it will be understood that smaller pitches may be achieved, such as 3 to 5 microns. As described above and, for example, with reference to Figure 10, the SPADs and associated shift registers are provided in a spatial distribution, for example, in an array. The operation of the sensing device is dependent on the delivery and the sampling of signals across the sensing device. In some embodiments, the sensing device has signal circuitry, for example, timing signal circuitry, configured to deliver signals to the shift registers and SPADs across their spatial distribution. Figure 11 depicts an arrangement of such signalling circuitry, in accordance with an embodiment, in which the signal circuitry is in an H-tree arrangement.

The H-tree arrangement allows for uniform sampling of laser pulse information across the pixel array. The H-tree signalling arrangement also provides for uniform delivery of timing signals across the pixel array. In particular, the timing signals include the clock signals to the shift registers and gating signals to the SPAD circuitry. Other timing signals that may be delivered by the H-tree arrangement include the START, Chain and MemCIk signals. In particular, the clock signals to each shift register, the gating signals including Common signal, describe above, and the chaining signals are provided by an H-tree signal. The Recharge signal may also be distributed by an H- tree, dependent on the operating mode. The chaining signal does not need to be distributed by an H-tree as the chain signal is only asserted at low rate at the beginning of a frame capture or series of frame captures. In the above-described embodiments, the signals that use the H-tree arrangement are the shift register clock (Clk), Recharge and Common signals (they will have a clock pulse on one of them depending on high or low spatial resolution mode).

The H-tree arrangement allows a 2-D SPAD image array to replace EMCCD and therefore may ease alignment with respect to the diffraction grating spectral line which can be post-processed in software. In addition, if time resolved Raman is to be captured the laser pulse may be shifted towards the active time bins by an on-chip DLL and the sensor is operated at full spatial/spectral resolution but short temporal resolution. If fluorescence lifetime is to be captured the SPADs/shift registers in the macro-pixel are chained, as described above, leading to a reduction reducing spatial/spectral resolution but increasing the number of time bins to capture the full exponential decay. In such embodiments, the lower frequency START, Chain and MemCIk signals would be distributed by a timing balanced H-tree arrangement. It will be understood that the H-tree provides uniform sampling of the laser pulse information over the entire pixel array. An imager with a few shift register bits forms a compact indirect time of flight pixel for high resolution imagers without needing extreme logic scaling at advanced nodes. The pixel is laser power efficient as the shift registers are only operated to capture photons immediately after the laser pulse. The remainder of the time until the next laser pulse the data is being transferred from dynamic to static memory and the 1/r^A2 property means no returning photons are available from the laser.

Figures 12 to 16 are timing diagrams for the operation of the sensing device. Figure 12 is a timing diagram for a first mode of operation. The timing diagram has two phases: a first data acquisition phase and a second data writing phase. A further phase, in which data is transferred from the device follows the data writing phase.

In Figure 12, a laser is fired while the plurality of SPADs are being recharged. The recharged SPADs are therefore primed to detect a photon detection event. During the data acquisition phase, the clock signal is generated at a first acquisition rate. One of the plurality of SPADs during the acquisition phase (registering a signal at SPAD <N- 1>). This triggers a change of state in the corresponding shift register(s) as described with reference to Figure 2.

At the end of the data acquisition phase the data writing phase starts. The clock signal changes from a higher rate to a slower rate for the data writing phase. The state of the shift register(s) represents the timing and/or event information acquired during the data acquisition phase. The signal Dout from the shift register(s) is then received from the signal routing circuitry. Depending on the configuration, this may comprise multiplexed signals from each individual shift register (per-pixel) or from one or more chained groups of the shift registers. The signal(s) from the shift registers(s) are then written into the shared memory. The address controller and/or incrementing circuitry act to access the SRAM memory and write the collected timing information into the memory in accordance with a pre-defined writing sequence.

In Figure 12, the signal Access<N*M-1 :0> indicates an SRAM word being addressed. This signal can be considered as a one-shot code from a shift register clocked by MemCIk which has same period as Clk during memory transfer. Photons are captured in the M previous cycles of Clk prior to the rising edge of Chain. The position of the laser edge may be adjusted to place the relevant photons inside this time interval.

Figures 13, 14 and 15 are timing diagrams for further non-limiting modes of operation of the sensing device. In Figure 13, a sum of SPAD counts is performed by modifying the clock rate of Memclk with respect to clock. In this example (for a 4-bin iToF) provides a photon count per SPAD and all 4 time bins are summed together together.

In Figure 14 is an example timing diagram for a macro-pixel of N SPADs when all N SPADs are combined. The summing of SPAD counts is performed by modifying the clock rate of Memclk wrt Clk. In this example, all photon counts are summed for all N SPADs into a single bin (N). This timing allows for photon counting over the full macro pixel.

Figure 15 depicts a 4-bin (M=4) iToF example in which all N SPAD bins are summed into a 4 bin histogram. In this example, the N SPADs are combined into a single SPAD. The timing diagram of Figure 15 allows aggregation of all N 4-bin shift registers into a single (4 bin) histogram. The SRAM thus has size Nx4 and each histogram therefore has size N.

Figure 16 depicts an example for M=1 (i.e. each SPAD has a corresponding shift register of size 1) for photon counting. In this example, the Recharge signal is placed after rising edge of Chain to allow each SPAD to sense photons for the whole cycle time (without using a laser pulse). In this example, the N clock cycles are used to update the N memory bins.

Further comments on potential, non-limiting applications of the sensing device are provided in the following.

Firstly, the sensing device may configured to operate as a time of flight sensor. The ability to reconfigure the pixel from high to low spatial resolution at the same time changing the time range and resolution would be a tradeoff, for example, in indirect time of flight imaging. High spatial/angular resolution is required at long range but larger bin times are acceptable for lower depth precision. Low spatial/angular resolution is required at short range and shorter bin widths are necessary for better precision. In a further example, the configurable circuitry may be configured in advance depending on whether to capture Raman photons or Fluorescence photons. In the former, the shift register is unchained with a high temporal resolution (fast clock) to capture fast Raman transient information (typically few 100ps). The spatial (equivalent to spectral) resolution would be high. In the latter, the shift register is chained and a low temporal resolution (slower clock) would be applied. This would give a low spectral resolution and a lower temporal resolution where the lifetime decay is typically over 10s of nanoseconds.

In the above-described embodiments, a configuration/re-configuration phase is described. It will be understood that, in some embodiments, a reconfiguration may be performed on the fly, in that the reconfiguration may be performed within a single clock laser cycle to allow data acquisition at a pre-determined depth-related spatial and temporal resolution.

In accordance with a further embodiment, a minimal viable SPAD macro-pixel is described. The minimal viable macro-pixel has N-SPADs with individual recharge transistors and multiple per-SPAD state memory elements (shift register D-types). A shared clock generator is also provided for the shift registers. Combining function (combining circuitry) between SPADs and memory cells is also provided and may include, for example, a multiplexing arrangement, an OR-tree combiner, and a memory address controller. An in-pixel memory bank (shared memory) is also provided and configured to store N words each M bits. Shared addressing and readout mechanism for memory is also provided (one shared per macro-pixel). A memory increment function (ALU - shared per macro-pixel) is also provided. Such a macro-pixel may reduce a readout rate reduced from E to log2(E) frames/sec where E is the maximal rate of events per second from each SPAD. In addition, no TDC is required, rather two phase burst accumulate, then transfer to memory (time-partitioned multi-event TDC) is performed.

It will be understood that the arrangements described above may be implemented in a variety of applications including, for example, LiDAR, time-of-flight (ToF) and 3D imaging applications. It will be understood the device in the above described embodiments, an exchange of temporal and/or depth range with a spatial resolution is described. The selection of spatial resolution results from combining photon detectors, such that a sensing device with groups of combined photon detectors operating as combined photon detectors will have a lower spatial resolution than the sensing device with photon detectors operating individually. Likewise, the maximum temporal (or depth) range is dependent on the corresponding combination of shift registers.

As an non-limiting example, the clock speed is kept the same, then two or more combined shift registers may detect photon detection events over a longer acquisition period than each of the shift registers operate individually. In other applications, the temporal and/or depth resolution may be exchanged with a spatial resolution by combining the shift registers together with a modification of the clock speed/frequency. For example, a combined shift register may offer the same maximum range than each individual shift register if the combination of shift registers is accompanied by a corresponding change in clock frequency (thus leading to an increase in temporal and/or depth resolution). For example, a doubling of shift register size offers double the temporal (or depth) range at the same clock frequency. However, a doubling of a shift register size would offer the same maximum temporal (or depth) range if the clock frequency was also doubled thus offering a doubling in the depth and/or temporal resolution possible. It will be understood that, depending on application the depth resolution of the sensing device relates to the temporal resolution.

In some embodiments, the temporal and depth ranges corresponds to the maximum temporal range or maximum depth range available using the combined shift register (as time is equivalent to depth in Time of Flight application). The temporal range may be considered as the total time range over which histogram bins are available to bin/register photon detection events within a laser cycle. In some embodiments, the temporal range is equivalent to the number of combined shift register elements (in the above embodiments, the flip flops of each shift register) multiplied by the clock period. In time of flight applications, for example, the depth range is equivalent to the temporal range and therefore is dependent on the number of combined shift register elements (in the above embodiments, the flip flops of each shift register) multiplied by the clock period. In the above-described embodiments, the terms static and dynamic are used. With reference to a flip flop, in embodiments, the term dynamic may refer to an ability to hold and retain its state on a parasitic capacitance and will leak away if not refreshed. In contrast, in embodiments, static may mean the ability to holding and retain its state by virtue of feedback with no need to refresh. These terms are the same as for a dynamic or static memory (DRAM/SRAM). In embodiments, the shift register may be composed of flip flops that are dynamic or static. In some embodiments, static flip flops may offer better performance because of the lack of leakage, however, these tend to be larger in circuit area.

In the above-described embodiments the multiplexer is provided after the D-type flipflops. In alternative embodiments, the multiplexer is provided before the dynamic shift register such that the multiplexer takes a first input from the SPAD (i.e. the signal VSPAD) and a second input from C<i-1>. The output of the multiplexer is then provided to the dynamic shift register. In such embodiments, a global chaining signal is still provided to obtain information from the shift registers. In particular, for each pixel, a chain signal is provided to the multiplexer to obtain information from the preceding shift register.

Figure 17 depicts a SPAD pixel 1200 in accordance with such an embodiment. It will be understood that the SPAD pixel 1200 corresponds to SPAD pixel 200. In particular, the pixel 1200 comprises a SPAD 1202, a recharge transistor 1204, a clamp diode 1206, a first quench transistor 1208, a second quench transistor 1210, a common anode connection 212, a dynamic shift register 1214 comprising a cascade of M D-type flipflops (1216a, ... , 1216m).

The SPAD and shift register are connected to an input of a 2:1 (two input, two outputs) multiplexer 1218. In contrast to Figure 3, in the embodiments of Figures 17 to 20, the first input to the multiplexer 1218 is the generated voltage VSAP. As described above, when one SPAD of the group of SPADs fires, the firing SPAD generates a voltage VSPAD. This signal VSPAD is provided to the input of the multiplexer 218. The other input to the multiplexer 1218 is provided from a further SPAD pixel provided in the macro-pixel. The further SPAD pixel (not shown) is provided in a chaining arrangement (an example chaining arrangement is depicted in Figures 8(a) and 8(b)) with the SPAD pixel 1200. The input signal from the preceding SPAD pixel (the i-1 th pixel) to the multiplexer is denoted C<i-1>. The output signal from the multiplexer is provided for this SPAD pixel (the ith pixel) is denoted C. The output of the multiplexer is provided to the shift register 1214. The signal read from the each shift register (the ith shift register) is denoted Q<M,i> and is a word having an M size. In each SPAD pixel there is an M-bit shift register. When combined and chained into an N-pixel macropixel, the total length of the combined shift register is NxM. An SRAM memory word is provided for each of the bits in the combined shift register in the shared memory, and therefore the shared memory provides NxM per macropixel.

Figure 18 to 20 correspond to embodiments. In particular, Figures 18 to 20 correspond to Figures 4 to 6 with the placement of the 2:1 (two input, two outputs) multiplexer 218 provided between the SPAD and the shift register, substantially as described with reference to Figure 17.

In further detail, Figure 18 depicts a 4 bin indirect time of flight (iToF) embodiment. Figure 4 is a SPAD pixel 1300 having a SPAD 302, a recharge transistor 1304, a clamp diode 1306, a first quench transistor 1308, a second quench transistor 1310, a common anode connection 1312, a dynamic shift register 1314 comprising a cascade of 4 D-type flip-flops (1316a, ... , 1316m) and a multiplexer 1318. A chain signal 1320 is provided to the multiplexer 1318.

Figure 19 is a 2 bin iToF example. Figure 175 depicts a SPAD pixel 1400 having a SPAD 1402, a recharge transistor 1404, a clamp diode 1406, a first quench transistor 1408, a second quench transistor 1410, a common anode connection 1412, a dynamic shift register 1414 comprising a cascade of 2 D-type flip-flops (1416a, ... , 1416m) and a multiplexer 1418. A chain signal 1420 is provided to the multiplexer 1418.

Figure 20 is a pixel suitable for a photon counting image sensor. Figure 20 depicts a SPAD pixel 1500 having a SPAD 1502, a recharge transistor 1504, a clamp diode 1506, a first quench transistor 1508, a second quench transistor 1510, a common anode connection 1512, a dynamic shift register 1514 comprising a D-type flip-flop 1516a and a multiplexer 1518. A chain signal 1520 is provided to the multiplexer 1518. In the above described embodiments, shift registers are described. It will be understood that the shift registers are combinable to form one or more larger shift registers. The shift registers may be operable to be loaded in a parallel or serial loadable fashion. For example, the shift registers may be loaded in parallel fashion in response to photon detection events. In some embodiments, the shift registers may be loaded in a serial fashion in response to photon detection events. The shift registers and corresponding multiplexers may be operable to operate in either a serial in parallel out (SIPO) or parallel in serial out (PISO) mode. Such devices may, in some embodiments, be provided together with a shared memory, for example, the SRAM or shared DRAM and configured to efficiently map or transfer data from the shift registers to the SRAM or DRAM. Such a device of shift registers, photon detectors and shared memory offer advantages in terms of density when forming an array, and may offer a higher density arrangement.

In some embodiments, the shift registers and corresponding multiplexers may be operable to operate in either a serial in parallel out (SIPO) or parallel in serial out (PISO) mode. In further embodiments, the device is configured to operate in a parallel in/parallel out mode (PIPO) with suitable logic to address shared module memory (for addressing the SRAM words).

In the above described embodiments, photons are sampled with the shift register and subsequently transferred to the shared memory. The sharing of the memory between shift registers may reduce the pixel area. Furthermore, sampling with a shift register may allow both a high dynamic range and direct time of flight modes in one sensing device.

A skilled person will appreciate that variations of the disclosed arrangements are possible without departing from the scope of the invention. Accordingly, the above description of the specific embodiment is made by way of example only and not for the purposes of limitation. It will be clear to the skilled person that minor modifications may be made without significant changes to the operation described.

Claims

CLAIMS:

1. A photon sensing device for photon sensing comprising: a plurality of photon detectors coupled to a plurality of shift registers, wherein the plurality of photon detectors and shift registers are provided as part of a configurable circuitry configurable to combine two or more of the plurality of shift registers and to combine two or more photon detectors to form one or more combined shift registers and one or more combined photon detectors, respectively.

2. The device as claimed in claim 1 , wherein at least the combining of the two or more of the plurality of shift registers and the combining of the two or more photon detectors provides an exchange of a temporal, or depth, range and/or resolution with a spatial resolution.

3. The device as claimed in any preceding claim, wherein the sensing device further comprises: a shared memory module, for example, an SRAM or DRAM memory module, wherein the shared memory module is shared between at least part of the configurable circuit and is configured to store data representing spatial and/or timing and/or count information from the at least part of the configurable circuit

4. The device as claimed in any preceding claim, wherein at least two of the plurality of shift registers are coupled to the shared memory module, preferably at least three of the plurality of shift registers.

5. The device as claimed in claim 3 or 4, wherein the shared memory module is configurable to select a data structure for storing spatial and/or timing and/or count information from the at least part of the reconfigurable circuit, wherein the data structure is selected to correspond to the temporal and/or depth resolution and/or acquisition period and/or spatial resolution of the at least part of the reconfigurable circuit

6. The device as claimed in any of claims 3 to 5, wherein the plurality of shift registers comprise a dynamic memory and wherein the shared memory module comprises a static memory

7. The device as claimed in any preceding claim, wherein the plurality of photon detectors, plurality of shift registers and/or the shared memory block are provided in a layered structure.

8. The device of any preceding claim, wherein the configurable circuitry is controllable by one or more configuration signals to combine the plurality of photon detector and/or the plurality of shift registers.

9. The device of any preceding claim, wherein the temporal, or depth, range or resolution is adjustable by selecting a property of one or more clock signals, for example, a speed and/or frequency, provided to the plurality of shift registers

10. The device of any preceding claim, wherein the plurality of photon detectors comprise a plurality of single photon detectors, for example, a plurality of SPADs.

11. The device of any preceding claim, wherein the combined photon detector comprises a group of photon detectors operating together as a single photon detector to detect photons over a larger spatial area than each individual photon detector of the group of photon detectors and/or wherein the combined shift register comprise a group of shift registers operating together as a single shift register to provide a longer acquisition period compared to each individual shift register of the group of shift registers

12. The device of any preceding claim, wherein the configurable circuitry comprises signal routing circuity for the plurality of shift registers wherein the signal routing circuitry is selectively operable to route signals for the shift registers thereby to combine output signals from the one or more of the plurality of shift registers.

13. The device of any preceding claim, wherein the shift registers are provided in a linear or serial arrangement, optionally wherein the output of a first shift register is selectively provided to an input of a further shift register

14. The device of any preceding claim, wherein the plurality of shift registers are arranged in a chaining arrangement configurable to selectively chain two or more of the shift registers together thereby to form the one or more combined shift registers.

15. The device wherein the plurality of shift registers comprise a shift register, for example, a dynamic shift register.

16. The device as claimed in any preceding claim, wherein the photon sensing device comprises shared photon detection circuitry configurable to perform a shared recharge and/or quenching operation for each combined photon detector.

17. The device as claimed in claim 16, wherein the photon detection circuitry comprises at least one shared anode and/or at least one recharge transistor between photon detectors.

18. The device as claimed in any preceding claim, wherein at least one of the plurality of photon detection devices and at least one of the plurality of shift registers are provided together as part of an arrayable pixel element, optionally wherein each arrayable pixel element comprises one photon detector and a corresponding shift register.

19. The device as claimed in any preceding claim, wherein the device further comprises a plurality of further arrayable macro-pixel elements, each macro-pixel element comprising a plurality of arrayable pixel elements together with a shared memory module.

20. The device of claim 19, wherein the sensing device further comprises further shared resources shared between two or more of the macro-pixels, for example, a gated ring oscillator.

21. The device of any preceding claim, wherein the plurality of photon detectors and shift registers are in a spatial distribution wherein the sensing device comprises signalling circuitry, for example, timing signalling circuitry, configured to provide one or more signals to the plurality of shift registers and/or the plurality of photon detectors over the spatial distribution, wherein the signalling circuitry is in an H-tree arrangement

22. The device of any preceding claim, wherein the configurable circuitry is configurable into at least a first configuration and a second configuration, wherein in the first configuration, each combined photon detector is coupled to a corresponding combined shift register such that combined photon detector is configured to modify the coupled combined shift register in response to a photon detection event such that the coupled combined shift register stores photon detection event information and wherein, in the second configuration, each photon detector is coupled to a corresponding shift register such that the photon detector is configure to modify the coupled shift register in response to a photon detection event such that the coupled combined shift register stores photon detection event information.

23. The device of any preceding claim, wherein the first configuration comprises a comprising a first temporal resolution and a first spatial resolution and wherein the second configuration having a second temporal resolution and a second spatial resolution, wherein the first spatial resolution is lower than the second spatial resolution and the first temporal resolution is higher than a second temporal resolution.

24. The device as claimed in any preceding claim, wherein the configurable circuitry is operable to be reconfigured within a single clock laser cycle to allow data acquisition at a pre-determined depth-related spatial and/or temporal resolution.

25. A method comprising: configuring a photon sensing device wherein configuring the photon sensing device comprises combining two or more of a plurality of shift registers and combine two or more of a plurality of photon detectors to form one or more combined shift registers and one or more combined photon detectors, respectively; operating the photon sensing device to perform a photon sensing process.