EP4676608A1

EP4676608A1 - Multi-frame architecture for gaming super-resolution

Info

Publication number: EP4676608A1
Application number: EP24713236.8A
Authority: EP
Inventors: Antoine Clement Mercier; Guillaume Jean Fernand Berger; Ruan Sybrand ERASMUS; Fatih Murat PORIKLI
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2023-03-07
Filing date: 2024-02-14
Publication date: 2026-01-14
Also published as: KR20250160426A; WO2024186456A1; CN120813413A

Abstract

A processor-implemented method for multi-frame gaming super-resolution includes receiving, by an artificial neural network (ANN), a set of inputs for a current frame of a video game and a recurrent input based on a previous frame of the video game. The current frame has a first resolution and the set of inputs for the current frame includes a jitter offset. The ANN estimates weights of convolution layers based on the jitter offset. The ANN reconstructs the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input. The second resolution is greater than the first resolution.

Description

MULTI-FRAME ARCHITECTURE FOR GAMING SUPER-RESOLUTION

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application claims the benefit of Greece Patent Application No. 20230100191, filed on March 7. 2023. and titled “MULTI-FRAME ARCHITECTURE FOR GAMING SUPER-RESOLUTION,” the disclosure of which is expressly incorporated by reference in its entirety.

FIELD OF THE DISCLOSURE

[0002] Aspects of the present disclosure generally relate artificial neural networks, and more specifically to a neural network architecture for multi-frame gaming superresolution.

BACKGROUND

[0003] Artificial neural networks may comprise interconnected groups of artificial neurons (e.g., neuron models). The artificial neural network may be a computational device or be represented as a method to be performed by a computational device. Convolutional neural networks (CNNs) are a type of feed-forw ard artificial neural network. Convolutional neural networks may include collections of neurons that each have a receptive field and that collectively tile an input space. Convolutional neural networks, such as deep convolutional neural networks (DCNs), have numerous applications. In particular, these neural network architectures are used in various technologies, such as image recognition, speech recognition, acoustic scene classification, keyword spotting, autonomous driving, and other classification tasks.

[0004] The introduction of mobile gaming and next generation gaming consoles, as well as new releases of widely popular games has spurred significant growth in popularity in video gaming. Their popularity has led to increased demand for gaming that provides more immersive experiences with more realistic and higher quality graphics. However, providing higher resolutions, higher refresh rates, more realistic visual effects, and real-time rendering to meet the increased demands is challenging. SUMMARY

[0005] The present disclosure is set forth in the independent claims, respectively. Some aspects of the disclosure are described in the dependent claims.

[0006] In some aspects of the present disclosure, a processor-implemented method includes receiving, by an artificial neural network (ANN), a set of inputs for a current frame of a video game and a recurrent input based on a previous frame of the video game. The current frame has a first resolution and the set of inputs for the current frame includes a jitter offset. The processor-implemented method also includes estimating, by the ANN, weights of a convolution layer based on the jitter offset. The processor- implemented method further includes reconstructing, by the ANN, the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input. The second resolution is greater than the first resolution.

[0007] Various aspects of the present disclosure are directed to an apparatus including means for receiving, by an artificial neural network (ANN), a set of inputs for a current frame of a video game and a recurrent input based on a previous frame of the video game. The current frame has a first resolution and the set of inputs for the cunent frame includes ajitter offset. The apparatus also includes means for estimating, by the ANN, weights of a convolution layer based on the jitter offset. The apparatus further includes means for reconstructing, by the ANN, the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input. The second resolution is greater than the first resolution.

[0008] In some aspects of the present disclosure, a non-transitory computer-readable medium with non-transitory program code recorded thereon is disclosed. The program code is executed by a processor and includes program code to receive, by an artificial neural network (ANN), a set of inputs for a current frame of a video game and a recurrent input based on a previous frame of the video game. The current frame has a first resolution and the set of inputs for the current frame includes a jitter offset. The program code also includes program code to estimate, by the ANN, weights of a convolution layer based on the jitter offset. The program code further includes program code to generate, by the ANN, reconstruct, by the ANN, the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input. The second resolution is greater than the first resolution.

[0009] Various aspects of the present disclosure are directed to an apparatus having a memory and one or more processors coupled to the memory. The processor(s) is configured to receive, by an artificial neural network (ANN), a set of inputs for a current frame of a video game and a recurrent input based on a previous frame of the video game. The current frame has a first resolution and the set of inputs for the current frame includes a jitter offset. The processor(s) is also configured to estimate, by the ANN, weights of a convolution layer based on the jitter offset. The processor(s) is further configured to reconstruct, by the ANN, the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input. The second resolution is greater than the first resolution.

[0010] Additional features and advantages of the disclosure will be described below. It should be appreciated by those skilled in the art that this disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The features, nature, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. [0012] FIGURE 1 illustrates an example implementation of a neural network using a system-on-a-chip (SOC), including a general-purpose processor, in accordance with certain aspects of the present disclosure.

[0013] FIGURES 2A, 2B, and 2C are diagrams illustrating a neural network, in accordance with various aspects of the present disclosure.

[0014] FIGURE 2D is a diagram illustrating an exemplary deep convolutional network (DCN), in accordance with various aspects of the present disclosure.

[0015] FIGURE 3 is a block diagram illustrating an exemplary deep convolutional network (DCN), in accordance with various aspects of the present disclosure.

[0016] FIGURE 4 is a block diagram illustrating an exemplary software architecture that may modularize artificial intelligence (Al) functions, in accordance with various aspects of the present disclosure.

[0017] FIGURE 5 is a diagram illustrating viewport jittering, according to various aspects of the present disclosure.

[0018] FIGURE 6 is a block diagram illustrating example high level architecture for multi-frame gaming super-resolution, in accordance with various aspects of the present disclosure.

[0019] FIGURE 7 is a block diagram illustrating a warping module, in accordance with various aspects of the present disclosure.

[0020] FIGURES 8A and 8B are block diagrams illustrating example architectures of an artificial neural network (ANN) and a multilayer perceptron (MLP), respectively, in accordance with various aspects of the present disclosure.

[0021] FIGURE 9 is a flow diagram illustrating a processor-implemented method for multi-frame gaming super-resolution, in accordance with various aspects of the present disclosure. DETAILED DESCRIPTION

[0022] The detailed description set forth below in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0023] Based on the teachings, one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth. In addition, the scope of the disclosure is intended to cover such an apparatus or method practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth. It should be understood that any aspect of the disclosure disclosed may be embodied by one or more elements of a claim.

[0024] The word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0025] Although particular aspects are described, many variations and permutations of these aspects fall within the scope of the disclosure. Although some benefits and advantages of the preferred aspects are mentioned, the scope of the disclosure is not intended to be limited to particular benefits, uses or objectives. Rather, aspects of the disclosure are intended to be universally applicable to different technologies, system configurations, networks, and protocols, some of which are illustrated by way of example in the figures and in the following description of the preferred aspects. The detailed description and drawings are merely illustrative of the disclosure rather than limiting, the scope of the disclosure being defined by the appended claims and equivalents thereof. [0026] A video game is an electronic interactive game played by manipulating images produced by a computer program on a display screen. The game is displayed on the display screen by a process referred to as rendering. Rendering may involve generating images from a two-dimensional (2D) or three-dimensional (3D) model. Real-time rendering may be used in video game development to build interactive motion graphics.

[0027] Video game rendering may be conducted by a game engine, which is a software framework for video game development. The game engine may include various components for creating the video game. For instance, the game engine may include a rendering engine, a physics engine, a sound engine to control sound effects generated in gameplay interactions, a networking module to enable online and social gaming, and other modules. The physics engine may enable development and control movements of objects in the game such as projectile motions and real-life activities and reactions.

[0028] Super-resolution (SR) has become a popular topic in gaming. Superresolution is the task of recovering a high-resolution image from its low-resolution counterpart. As opposed to single-image models, multi-frame super-resolution approaches have access to multiple, consecutive, low-resolution images.

[0029] In the gaming context, super-resolution aims to improve the visual quality of video games by increasing the resolution of the displayed images. In the field of gaming, super-resolution may be motivated by a performance boost, which may be achieved by rendering the video game at a lower resolution followed by upscaling, which may run faster (e.g.. reduced processing latency) than rendering the game directly at the target resolution.

[0030] One challenge in developing efficient super-resolution is the difficulty of balancing accuracy-speed tradeoffs. Additionally, the lack of a publicly available dataset for developing gaming-specific super-resolution solutions is also challenging. Instead, researchers and developers have to create their own datasets, which may be a time-consuming and resource-intensive process.

[0031] In recent years, deep learning-based approaches for super-resolution of natural content have become increasingly popular, yielding state-of-the-art visual quality compared to interpolation and other algorithmic solutions. Some conventional super-resolution approaches may exploit information gathered from consecutive images, as multi-image super-resolution (also called temporal super-sampling in the gaming field).

[0032] Offline super-resolution approaches designed for video enhancement may not be amenable to gaming. Some conventional online video super-resolution approaches are based on recurrent convolutional architectures and may rely on estimated (e.g.. imperfect) optical flow to re-align past information to the current frame. Other conventional online super-resolution approaches provide alternatives to explicit motion compensation and may include transformer-based architectures and up-sampling kernel prediction networks.

[0033] However, in gaming, performing explicit motion compensation may achieve increased performance because the game engine can produce sub-pixel accurate motion vectors rather than using an estimate. Additionally, an artificial neural network can be significantly smaller if the artificial neural network does not have to learn to copy- previous information over long distances as in conventional super-resolution approaches. Artificial neural networks (ANNs) may be considered a machine learning model including an interconnected group of nodes designed to mimic the function of the human brain.

[0034] Accordingly, aspects of the present disclosure are directed to an efficient multi-frame gaming super-resolution architecture. The gaming super-resolution architecture may leverage auxiliary- modalities (e.g.. sub-pixel accurate motion vectors, depth) and graphics rendering features (e.g.. viewport jittering, mipmap biasing), which may be used for temporal anti-aliasing. As such, aspects of the present disclosure may beneficially increase processing speed, and reduce latency and power consumption while maintaining accuracy in image reconstruction.

[0035] FIGURE 1 illustrates an example implementation of a system-on-a-chip (SOC) 100, which may include a central processing unit (CPU) 102 or a multi-core CPU configured for multi -frame gaming super resolution. Variables (e.g., neural signals and synaptic weights), system parameters associated with a computational device (e.g., neural network with weights), delays, frequency bin information, and task information may be stored in a memory block associated with a neural processing unit (NPU) 108, in a memory block associated with a CPU 102, in a memory block associated with a graphics processing unit (GPU) 104, in a memory' block associated with a digital signal processor (DSP) 106, in a memory block 118, or may be distributed across multiple blocks. Instructions executed at the CPU 102 may be loaded from a program memory associated with the CPU 102 or may be loaded from a memory block 118.

[0036] The SOC 100 may also include additional processing blocks tailored to specific functions, such as a GPU 104, a DSP 106, a connectivity block 110, which may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity', and the like, and a multimedia processor 112 that may, for example, detect and recognize gestures. In one implementation, the NPU 108 is implemented in the CPU 102, DSP 106, and/or GPU 104. The SOC 100 may also include a sensor processor 114, image signal processors (ISPs) 116, and/or navigation module 120, which may include a global positioning system.

[0037] The SOC 100 may be based on an ARM instruction set. In an aspect of the present disclosure, the instructions loaded into the general-purpose processor 102 may include code to receive, by an artificial neural network (ANN), a set of inputs for a current frame of a video game and a recurrent input based on a previous frame of the video game. The current frame has a first resolution and the set of inputs for the current frame includes a jitter offset. Jitter offset may refer to a sub-pixel two-dimensional (2D) shift within a pixel grid by which the pixel in the frame should be offset before rendering (e.g., drawing) the frame. In addition, the jitter offset may vary for each frame.

[0038] The instructions loaded into the general -purpose processor 102 may also include code to estimate, by the ANN. weights of a convolution layer based on the jitter offset. Furthermore, the instructions loaded into the general -purpose processor 102 may include code to reconstruct, by the ANN, the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input. The second resolution is greater than the first resolution. [0039] Deep learning architectures may perform an object recognition task by learning to represent inputs at successively higher levels of abstraction in each layer, thereby building up a useful feature representation of the input data. In this way, deep learning addresses a maj or bottleneck of traditional machine learning. Prior to the advent of deep learning, a machine learning approach to an object recognition problem may have relied heavily on human engineered features, perhaps in combination with a shallow classifier. A shallow classifier may be a two-class linear classifier, for example, in which a weighted sum of the feature vector components may be compared with a threshold to predict to which class the input belongs. Human engineered features may be templates or kernels tailored to a specific problem domain by engineers with domain expertise. Deep learning architectures, in contrast, may learn to represent features that are similar to what a human engineer might design, but through training. Furthermore, a deep network may learn to represent and recognize new t pes of features that a human might not have considered.

[0040] A deep learning architecture may learn a hierarchy of features. If presented with visual data, for example, the first layer may learn to recognize relatively simple features, such as edges, in the input stream. In another example, if presented with auditory data, the first layer may leam to recognize spectral power in specific frequencies. The second layer, taking the output of the first layer as input, may leam to recognize combinations of features, such as simple shapes for visual data or combinations of sounds for auditory data. For instance, higher layers may leam to represent complex shapes in visual data or words in auditory data. Still higher layers may leam to recognize common visual objects or spoken phrases.

[0041] Deep learning architectures may perform especially well when applied to problems that have a natural hierarchical structure. For example, the classification of motorized vehicles may benefit from first learning to recognize wheels, windshields, and other features. These features may be combined at higher layers in different ways to recognize cars, trucks, and airplanes.

[0042] Neural networks may be designed with a variety⁷ of connectivity patterns. In feed-forw ard networks, information is passed from lower to higher layers, with each neuron in a given layer communicating to neurons in higher layers. A hierarchical representation may be built up in successive layers of a feed-forward network, as described above. Neural networks may also have recurrent or feedback (also called top- down) connections. In a recurrent connection, the output from a neuron in a given layer may be communicated to another neuron in the same layer. A recurrent architecture may be helpful in recognizing patterns that span more than one of the input data chunks that are delivered to the neural network in a sequence. A connection from a neuron in a given layer to a neuron in a lower layer is called a feedback (or top-down) connection. A network with many feedback connections may be helpful when the recognition of a high-level concept may aid in discriminating the particular low-level features of an input.

[0043] The connections between layers of a neural network may be fully connected or locally connected. FIGURE 2A illustrates an example of a fully connected neural network 202. In a fully connected neural network 202, a neuron in a first layer may communicate its output to every neuron in a second layer, so that each neuron in the second layer wall receive input from every neuron in the first layer. FIGURE 2B illustrates an example of a locally connected neural netw ork 204. In a locally connected neural network 204, a neuron in a first layer may be connected to a limited number of neurons in the second layer. More generally, a locally connected layer of the locally connected neural network 204 may be configured so that each neuron in a layer will have the same or a similar connectivity pattern, but with connections strengths that may have different values (e.g., 210, 212. 214, and 216). The locally connected connectivitypattern may give rise to spatially distinct receptive fields in a higher layer because the higher layer neurons in a given region may receive inputs that are tuned through training to the properties of a restricted portion of the total input to the netw ork.

[0044] One example of a locally connected neural network is a convolutional neural network. FIGURE 2C illustrates an example of a convolutional neural network 206. The convolutional neural network 206 may be configured such that the connection strengths associated with the inputs for each neuron in the second layer are shared (e.g., 208). Convolutional neural networks may be well suited to problems in which the spatial location of inputs is meaningful.

[0045] One type of convolutional neural network is a deep convolutional network (DCN). FIGURE 2D illustrates a detailed example of a DCN 200 designed to recognize visual features from an image 226 input from an image capturing device 230. such as a car-mounted camera. The DCN 200 of the current example may be trained to identify traffic signs and a number provided on the traffic sign. Of course, the DCN 200 may be trained for other tasks, such as identifying lane markings or identifying traffic lights.

[0046] The DCN 200 may be trained with supervised learning. During training, the DCN 200 may be presented with an image, such as the image 226 of a speed limit sign, and a forward pass may then be computed to produce an output 222. The DCN 200 may include a feature extraction section and a classification section. Upon receiving the image 226. a convolutional layer 232 may apply convolutional kernels (not shown) to the image 226 to generate a first set of feature maps 218. As an example, the convolutional kernel for the convolutional layer 232 may be a 5x5 kernel that generates 28x28 feature maps. In the present example, because four different feature maps are generated in the first set of feature maps 218, four different convolutional kernels were applied to the image 226 at the convolutional layer 232. The convolutional kernels may also be referred to as filters or convolutional filters.

[0047] The first set of feature maps 218 may be subsampled by a max pooling layer (not shown) to generate a second set of feature maps 220. The max pooling layer reduces the size of the first set of feature maps 218. That is, a size of the second set of feature maps 220, such as 14x14, is less than the size of the first set of feature maps 218, such as 28x28. The reduced size provides similar information to a subsequent layer while reducing memory consumption. The second set of feature maps 220 may be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not show n).

[0048] In the example of FIGURE 2D, the second set of feature maps 220 is convolved to generate a first feature vector 224. Furthermore, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature of the second feature vector 228 may include a number that corresponds to a possible feature of the image 226, such as "sign." ^iL60,’^? and "TOOT A softmax function (not shown) may convert the numbers in the second feature vector 228 to a probability. As such, an output 222 of the DCN 200 may be a probability' of the image 226 including one or more features. [0049] In the present example, the probabilities in the output 222 for “sign” and “60” are higher than the probabilities of the others of the output 222, such as “30,” “40,” “50,” “70,” “80,” “90,” and “100”. Before training, the output 222 produced by the DCN 200 may likely be incorrect. Thus, an error may be calculated between the output 222 and a target output. The target output is the ground truth of the image 226 (e.g., “sign” and “60”). The weights of the DCN 200 may then be adjusted so the output 222 of the DCN 200 is more closely aligned with the target output.

[0050] To adjust the weights, a learning algorithm may compute a gradient vector for the weights. The gradient may indicate an amount that an error would increase or decrease if the weight were adjusted. At the top layer, the gradient may correspond directly to the value of a weight connecting an activated neuron in the penultimate layer and a neuron in the output layer. In lower layers, the gradient may depend on the value of the weights and on the computed error gradients of the higher layers. The weights may then be adjusted to reduce the error. This manner of adjusting the weights may be referred to as “back propagation” as it involves a “backward pass” through the neural network.

[0051] In practice, the error gradient of weights may be calculated over a small number of examples, so that the calculated gradient approximates the true error gradient. This approximation method may be referred to as stochastic gradient descent. Stochastic gradient descent may be repeated until the achievable error rate of the entire system has stopped decreasing or until the error rate has reached a target level. After learning, the DCN 200 may be presented with new images and a forward pass through the DCN 200 may yield an output 222 that may be considered an inference or a prediction of the DCN 200.

[0052] Deep belief networks (DBNs) are probabilistic models comprising multiple layers of hidden nodes. DBNs may be used to extract a hierarchical representation of training data sets. A DBN may be obtained by stacking up layers of Restricted Boltzmann Machines (RBMs). An RBM is a type of artificial neural network that can learn a probability distribution over a set of inputs. Because RBMs can learn a probability distribution in the absence of information about the class to which each input should be categorized, RBMs are often used in unsupervised learning. Using a hybrid unsupervised and supervised paradigm, the bottom RBMs of a DBN may be trained in an unsupervised manner and may serve as feature extractors, and the top RBM may be trained in a supervised manner (on a joint distribution of inputs from the previous layer and target classes) and may serve as a classifier.

[0053] DCNs are networks of convolutional networks, configured with additional pooling and normalization layers. DCNs have achieved state-of-the-art performance on many tasks. DCNs can be trained using supervised learning in which both the input and output targets are known for many exemplars and are used to modify the weights of the network by use of gradient descent methods.

[0054] DCNs may be feed-forward networks. In addition, as described above, the connections from a neuron in a first layer of a DCN to a group of neurons in the next higher layer are shared across the neurons in the first layer. The feed-forward and shared connections of DCNs may be exploited for fast processing. The computational burden of a DCN may be much less, for example, than that of a similarly sized neural network that comprises recurrent or feedback connections.

[0055] The processing of each layer of a convolutional network may be considered a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then the convolutional network trained on that input may be considered three-dimensional, with two spatial dimensions along the axes of the image and a third dimension capturing color information. The outputs of the convolutional connections may be considered to form a feature map in the subsequent layer, with each element of the feature map (e.g., 220) receiving input from a range of neurons in the previous layer (e.g., feature maps 218) and from each of the multiple channels. The values in the feature map may be further processed with a non-linearity, such as a rectification, max(0, x). Values from adjacent neurons may be further pooled, which corresponds to down sampling, and may provide additional local invariance and dimensionality reduction. Normalization, which corresponds to whitening, may also be applied through lateral inhibition between neurons in the feature map.

[0056] FIGURE 3 is a block diagram illustrating a DCN 350. The DCN 350 may include multiple different types of layers based on connectivity and weight sharing. As shown in FIGURE 3, the DCN 350 includes the convolution blocks 354A, 354B. Each of the convolution blocks 354A. 354B may be configured with a convolution layer (CONV) 356, a normalization layer (LNorm) 358, and a max pooling layer (MAX POOL) 360. Although only two of the convolution blocks 354A, 354B are shown, the present disclosure is not so limiting, and instead, any number of the convolution blocks 354 A, 354B may be included in the DCN 350 according to design preference.

[0057] The convolution layers 356 may include one or more convolutional filters, which may be applied to the input data to generate a feature map. The normalization layer 358 may normalize the output of the convolution filters. For example, the normalization layer 358 may provide whitening or lateral inhibition. The max pooling layer 360 may provide down sampling aggregation over space for local invariance and dimensionality reduction.

[0058] The parallel filter banks, for example, of a DCN may be loaded on a CPU 102 or GPU 104 of an SOC 100 (e.g., FIGURE 1) to achieve high performance and low pow er consumption. In alternative embodiments, the parallel filter banks may be loaded on the DSP 106 or an ISP 116 of an SOC 100. In addition, the DCN 350 may access other processing blocks that may be present on the SOC 100, such as sensor processor 114 and navigation module 120, dedicated, respectively, to sensors and navigation.

[0059] The DCN 350 may also include one or more fully connected layers 362 (FC1 and FC2). The DCN 350 may further include a logistic regression (LR) layer 364.

Between each layer 356, 358, 360, 362, 364 of the DCN 350 are weights (not shown) that are to be updated. The output of each of the layers (e.g., 356, 358, 360, 362, 364) may serve as an input of a succeeding one of the layers (e g., 356. 358, 360, 362, 364) in the DCN 350 to learn hierarchical feature representations from input data 352 (e.g., images, audio, video, sensor data and/or other input data) supplied at the first of the convolution blocks 354A. The output of the DCN 350 is a classification score 366 for the input data 352. The classification score 366 may be a set of probabilities, where each probability is the probability of the input data including a feature from a set of features.

[0060] FIGURE 4 is a block diagram illustrating an exemplary software architecture 400 that may modularize artificial intelligence (Al) functions. Using the architecture 400, applications may be designed that may cause various processing blocks of an SOC 420 (for example a CPU 422, a DSP 424, a GPU 426 and/or an NPU 428) (which may be similar to SOC 100 of FIGURE 1) to support multi-frame gaming super-resolution for an Al application 402, according to aspects of the present disclosure. The architecture 400 may, for example, be included in a computational device, such as a smartphone.

[0061] The Al application 402 may be configured to call functions defined in a user space 404 that may, for example, provide for the detection and recognition of a scene indicative of the location at which the computational device including the architecture 400 currently operates. The Al application 402 may, for example, configure a microphone and a camera differently depending on whether the recognized scene is an office, a lecture hall, a restaurant, or an outdoor setting such as a lake. The Al application 402 may make a request to compiled program code associated with a library defined in an Al function application programming interface (API) 406. This request may ultimately rely on the output of a deep neural network configured to provide an inference response based on video and positioning data, for example.

[0062] A run-time engine 408, which may be compiled code of a runtime framework, may be further accessible to the Al application 402. The Al application 402 may cause the run-time engine 408, for example, to request an inference at a particular time interval or triggered by an event detected by the user interface of the Al application 402. When caused to provide an inference response, the run-time engine 408 may in turn send a signal to an operating system in an operating system (OS) space 410, such as a Kernel 412, running on the SOC 420. In some examples, the Kernel 412 may be a LINUX Kernel. The operating system, in turn, may cause a continuous relaxation of quantization to be performed on the CPU 422. the DSP 424, the GPU 426, the NPU 428, or some combination thereof. The CPU 422 may be accessed directly by the operating system, and other processing blocks may be accessed through a driver, such as a driver 414, 416, or 418 for, respectively, the DSP 424, the GPU 426, or the NPU 428. In the exemplary example, the deep neural network may be configured to run on a combination of processing blocks, such as the CPU 422, the DSP 424, and the GPU 426, or may be run on the NPU 428.

[0063] As described, aspects of the present disclosure are directed to multi-frame super resolution for gaming using an artificial neural network. [0064] FIGURE 5 is a diagram illustrating viewport jitering. A viewport may be considered a screen onto which a video game is projected. Jitter may refer to an alteration of visible motion of objects on a display screen. For instance jiter may result in slight movement of an object in a video even when the camera does not move. Viewport jitering refers to shifting a sampling grid by a sub-pixel offset. Video games may be displayed on a display screen by way of rendering. Rendered content, unlike natural photographic images, may be formed on a sampling grid wherein each sample may comprise a point sample in space and time rather than a pixel area.

[0065] In order to evenly sample different locations within a frame, a jiter offset may shift the viewport for each frame. That is, the jitter offset may vary from one frame to the next frame. Referring to FIGURE 5, a frame 502 of a video game at timestep t and a frame 504 of the video game at time step t +1 are shown. The frame 502 has a jitter offset of (0.33, -0.33). The frame 504 has ajitter offset of (-0.33, 0.33). The jittering offsets may shift the sampling grid and the display grid.

[0066] FIGURE 6 is a block diagram illustrating example a high-level architecture 600 for multi-frame gaming super-resolution, in accordance with various aspects of the present disclosure. As show n in the FIGURE 6, the example architecture 600 includes a warping module 602 and an artificial neural network (ANN) 604. The example architecture 600 may receive a set of inputs 606a-d. The set of inputs 606a-d may be supplied by a video game engine (not shown), for instance. The set of inputs 606a-d may correspond to the current frame of the video game including a candidate image at a lower resolution. The set of inputs 606a-d may include, for example, color information 606a, depth information 606b, jiter offsets 606c, and motion vectors 606d. Although, the set of inputs (606a-d) shown in FIGURE 6 includes four inputs, this is merely an example and not limiting. Rather any number of inputs may be employed according to design preference. Additionally, other types of inputs may also be included.

[0067] The color information 606a, depth information 606b, and jiter offsets 606c may be supplied to the ANN 604. The color information 606a may comprise a rendered low -resolution frame of the video game. The depth information 606b, the jitter offsets 606c, and motion vectors 606d may be received by the warping module 602 along with recurrent inputs 608. The recurrent inputs 608 may include historical data such as higher resolution color information and higher resolution features generated by the ANN 604 for a frame of a previous time step. The warping module 602 may process the depth information 606b, the jitter offsets 606c, motion vectors 606d, and recurrent inputs 608 to re-align historical data of the recurrent inputs 608 to the current frame of the video game. That is, the warping module 602 may re-proj ect historical data to a current frame of a video game and generate warped recurrent inputs corresponding to the previous time step at a lower-resolution (e.g., down-sampled). The warped recurrent inputs (e.g., warped color 610a, warped features 610b) may be supplied to the ANN 604.

[0068] The ANN 604 may receive the warped recurrent inputs (e.g., warped color 610a, w arped features 610b) along with the color information 606a, depth information 606b, and jitter offsets 606c. In turn, the ANN 604 processes the warped recurrent inputs (e.g., warped color 610a, warped features 610b), the color information 606a, depth information 606b, and jitter offsets 606c and generates a reconstructed image 612 of the current frame at a target resolution (e.g., higher resolution) by blending the candidate image with the previous output image (e.g., warped color 610a, warped features 610b).

[0069] Non-limiting examples of the low-resolution candidate (e.g., 606a-d) and the high-resolution target (e.g., 612) are included below in Table 1.

TABLE 1

[0070] FIGURE 7 is a block diagram illustrating the warping module 602 of

FIGURE 6, in accordance with various aspects of the present disclosure. The warping module 602 may include a jitter compensation module 702. a depth-informed dilation module 704, and a grid sampler module 706.

[0071] Jitter compensation aims to remove a jitter offset contribution to the motion vectors. Jitter compensation may be performed to address viewport jittering which may introduce an artificial motion that may affect the motion vectors returned by a video game engine. Viewport jittering refers to a rendering technique that aims to ensure that consecutive frames contain complementary information about the scene. Viewport rendering may be removed to realign outputs from a previous timestep which have already been jitter-compensated / re-aligned with a non-jittered sampling grid. Realigning with the motion vectors without jitter compensation (e.g., with Viewport jittering) may re-introduce some flickering due to misalignment between consecutive frames.

[0072] In various aspects, the jitter compensation module 702 may receive the jitter offsets 606c and the motion vectors 606d. The jitter compensation module 702 may reduce viewport jittering contribution to the motion vector values, as follows: where MV_t represents the motion vectors, J_t represents the jitter offsets for frame t (e.g.. current frame), and J_t-1 represents the jitter offsets for frame t — 1 (e.g., previous frame). The motion vectors MV_t may be supplied to the depth-informed dilation module 704.

[0073] The depth-informed dilation module 704 may receive the depth information 606b and the motion vectors MV_t 606d. The depth-informed dilation module 704 may preprocess the motion vectors MV_t 606d to reduce aliasing in the foreground objects of the current frame. That is, depth-informed dilation module 704 may preprocess the motion vectors MV_t 606d to perform anti-aliasing. To achieve the reduction in aliasing (which may be referred to as anti-aliasing), the depth-informed dilation module 704 may generate a block-wise motion vector grid, where each block includes the motion vector value of the closest pixel (e.g., the pixel having the lowest depth value) within the block. The depth information 606b (e.g., a depth map) may be used to determine the closest pixel within each block. The motion vector grid may be down-sampled to a lower resolution (e.g., four times lower). Thereafter, the lower-resolution motion vector grid may be up-sampled to the target resolution (e.g., higher resolution) using nearest neighbor upscaling, for example. In some non-limiting examples, a scaling factor of two may be employed to create blocks of size 8x8 at a higher resolution, which may enable warping patches of size 8x8. Warping patches with an 8x8 block size may be beneficial for the reconstruction of thin structures and/or fine-grained objects, such as far-away fences or tree branches.

[0074] The grid sampler module 706 may then use a jitter-compensated and depth- informed dilated motion vector grid to perform a bilinear warp to re-align the high- resolution color images and neural features of the recurrent inputs 608 from the previous timestep to the current frame. A space-to-depth operation 708 may be applied to map the output of the grid sampler module 706 to the resolution of the inputs and generate the warped color 610a and warped features 610b of the previous time step.

[0075] FIGURES 8A and 8B are block diagrams illustrating example architectures of the ANN 604 of FIGURE 6 and a multilayer perceptron (MLP) 850, respectively, in accordance with various aspects of the present disclosure. The ANN 604 may comprise a convolutional neural network, for example. The ANN 604 may include multiple convolution blocks. Each of the convolution blocks may include a convolution layer (e.g., 3x3 convolution layers) 802a-n and a rectified linear unit (ReLU) 804a-n. The ReLUs 804a-n may implement an activation function such as a non-linear activation function which outputs a zero if the input (e.g., the output of the convolution layer (802a-n)) is negative and outputs the input (e g., the output of the convolution layer (802a-n)) otherwise.

[0076] Weights of convolution layers 802a-n may be determined based on the jitter offsets 606c. For example, in various aspects, the weights of 802a-n may be estimated using an MLP conditioned on the jitter offsets J_t 606c. For instance, as show n in the example of FIGURE 8B. an MLP 850 may receive a set of jitter offsets (e.g., jitter offsets J_t 606c). The jitter offsets J_t (e.g., 606c) may be supplied by a video game engine, for example. The jitter offsets J_t (e g., 606c) may be processed with successive fully connected (FC) layers 852a-z of the MLP 850 to generate an estimate of kernel weights and biases 854. [0077] In accordance with various aspects of the present disclosure, a single kernel (e.g., weights and biases) may be estimated for an entire frame of the video game (e.g., the current frame at timestep t). In some aspects, the single kernel (e.g., kernel weights and biases) may be estimated based only on the jitter offset J_t (e.g., 606c), which may comprise a relatively small two-dimensional vector.

[0078] Because the kernels for the convolution layer 802a may be conditioned on the jitter offsets J_t (e.g., 606c), the ANN 604 may compensate for a sub-pixel offset introduced by viewport jittering in lower resolution inputs. Additionally, by implementing the jitter-conditioned convolutions (e.g., 802a, 802n) in the ANN 604, an increase in peak-signal-to-noise-ratio (PSNR) may be achieved. PSNR is a metric that quantifies the quality of the super-resolved image. Higher PSNR values may indicate better reconstruction and higher fidelity to a ground truth image.

[0079] Moreover, because the jitter offsets J_t (e.g., 606c) may be known in advance, the kernel weights for each jitter offset J_t (e.g., 606c) may be pre-computed. Then, at inference time, the corresponding (pre-computed) kernel may be reloaded whenever a new jittered frame is generated. Inference time may refer to a stage, following training using a dataset, during which the ANN may be operated to generate an output (e.g., a decision, a prediction or a classification) based on input data (e.g., unseen data).

[0080] Accordingly, in operation, the ANN 604 may receive the lower resolution warped color 610a and warped features 610b of the previous frame (e.g., at time t-1) along with the lower resolution input of the current frame (e.g., at time t), such as the color information 606a, the depth information 606b, and the jitter offsets J_t 606c. The ANN 604 processes the inputs using the successive convolutional blocks including convolution layers 802a-n to generate a set of outputs as follows: a. Y_t, f_t = F( C_t, D_t, J_t, W( Y_t-1),W( /_t-1)), (2) where a is a pixel-wise blending mask, Y_t is a higher-resolution red-green-blue (RGB) candidate estimate. f_t represents features of the current frame at timestep t, F is the neural network (e.g., ANN 604) without the blending operation, C_t represents the color information 606a, D_t represents the depth information 606b, J_t represents the jitter offsets 606c, f_t-l represents previous features, and Y_t_! represents a previous output, is a previous output, W represents the warping module (e.g., 602), and W( Y_t_ _q ) represents a previous output re-aligned by the warping module W.

[0081] A blending module 810 may receive the higher resolution RGB candidate estimate and the pixel-wise blending mask a. The blending module 810 applies the blending mask a to the candidate higher resolution RGB candidate estimate and combines the color output from the previous frame and the current RGB candidate as follows:

[0082] Thereafter, a depth-to-space operation may map the lower resolution outputs to the target resolution (e.g., higher resolution).

[0083] FIGURE 9 is a flow diagram illustrating a processor-implemented method 900 for multi-frame gaming super-resolution, in accordance with various aspects of the present disclosure. The processor-implemented method 900 may be performed by one or more processors such as the CPU (e.g., 102, 422), the GPU (e.g., 104, 426), the NPU (e.g., 108, 428), and/or other processing units, for example.

[0084] As shown in FIGURE 9, at block 902, the one or more processors receive, by an artificial neural network (ANN), a set of inputs for a current frame of a video game and a recurrent input based on a previous frame of the video game. The current frame has a first resolution and the set of inputs for the current frame includes a jitter offset. For instance, as described with reference to FIGURE 6, the architecture 600 may receive a set of inputs 606a-d. The set of inputs 606a-d may be supplied by a video game engine, for instance . The set of inputs 606a-d may correspond to the current frame of the video game including a candidate image at a lower resolution. The set of inputs 606a-d may include, for example, color information 606a, depth information 606b, jitter offsets 606c, and motion vectors 606d.

[0085] At block 904. the one or more processors estimate, by the ANN, weights of a convolution layer based on the jitter offset. As described, for example, with reference to FIGURE 8A, the ANN 604 may include multiple convolution blocks. Each of the convolution blocks may include a convolution layer (e.g., 3x3 convolution layers) 802a- n. Weights of convolution layers 802a and 802n may be determined based on the jitter offsets 606c. For example, in various aspects, the weights of 802a and 802n may be estimated using a multilayer perceptron (MLP) conditioned on the jitter offsets ]_t 606c.

[0086] At block 906. the one or more processors reconstruct, by the ANN, the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input. The second resolution is greater than the first resolution. For instance, as described with reference to FIGURE 8A, The ANN 604 processes the inputs using the successive convolutional blocks including convolution layers 802a-n to generate a set of outputs including the pixel-wise blending mask a, the higher-resolution red-green- blue (RGB) candidate estimate Y_t. and the features f_t of the current frame at timestep t. A blending module 810 may receive the higher resolution RGB candidate estimate and the pixel-wise blending mask a. The blending module 810 applies the blending mask a to the candidate higher resolution RGB candidate estimate and combines the color output from the previous frame and the current RGB candidate. Thereafter, a depth-to- space operation may map the lower resolution outputs to the target resolution (e.g.. higher resolution).

Example Aspects

[0087] Aspect 1 : An apparatus, comprising: at least one memory; and at least one processor coupled to the at least one memory', the at least one processor configured to: receive, by an artificial neural network (ANN), a set of inputs for a cunent frame of a video game and a recurrent input based on a previous frame of the video game, the current frame, wherein the current frame has a first resolution and the set of inputs for the current frame includes a jitter offset; estimate, by the ANN, weights of a convolution layer based on the jitter offset; and reconstruct, by the ANN, the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input, wherein the second resolution is greater than the first resolution.

[0088] Aspect 2: The apparatus of Aspect 1, wherein the set of inputs for the current frame comprise one or more of depth information, color information or motion vectors, and the at least one processor is further configured to warp the recurrent input based on the one or more of depth information, the color information, or motion vectors. [0089] Aspect 3: The apparatus of Aspect 1 or 2. wherein the at least one processor is further configured to: apply the jitter offset to the motion vectors to compensate for viewport jittering; and adapt the jitter compensated motion vectors based on the depth information to provide anti-aliasing of an image in the current frame of the video game.

[0090] Aspect 4: The apparatus of any preceding Aspects, further comprising generating, by the ANN, the reconstructed current frame of the video game based on a pixel-wise blending mask.

[0091] Aspect 5: The apparatus of any preceding Aspects, wherein the weights of the convolution layer are precomputed at inference time.

[0092] Aspect 6: A processor-implemented method comprising: receiving, by an artificial neural network (ANN), a set of inputs for a current frame of a video game and a recurrent input based on a previous frame of the video game, wherein the current frame has a first resolution and the set of inputs for the current frame includes a jitter offset; estimating, by the ANN, weights of a convolution layer based on the jitter offset; and reconstructing, by the ANN, the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input, wherein the second resolution is greater than the first resolution.

[0093] Aspect 7: The processor-implemented method of Aspect 6, wherein the set of inputs for the current frame comprise one or more of depth information, color information or motion vectors, and the processor-implemented method further comprises warping the recurrent input based on the one or more of depth information, the color information, or motion vectors.

[0094] Aspect 8: The processor-implemented method of Aspect 6 or 7, further comprising: applying the jitter offsets to the motion vectors to compensate for viewport jittering; and adapting the jitter compensated motion vectors based on the depth information to provide anti-aliasing of an image in the current frame of the video game.

[0095] Aspect 9: The processor-implemented method of any of Aspects 6-8. wherein the reconstructed current frame is based on a pixel-wise blending mask. [0096] Aspect 10: The processor-implemented method of any of Aspects 6-9, wherein the weights of the convolution layer are precomputed at inference time.

[0097] Aspect 11: A non-transitory computer-readable medium having program code recorded thereon, the program code executed by a processor and comprising: program code to receive, by an artificial neural network (ANN), a set of inputs for a current frame of a video game and a recurrent input based on a previous frame of the video game, wherein the current frame has a first resolution and the set of inputs for the current frame includes a jitter offset; program code to estimate, by the ANN, weights of one or more convolution layers based on the jitter offsets; and program code to reconstruct, by the ANN, the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input, wherein the second resolution is greater than the first resolution.

[0098] Aspect 12: The non-transitory computer-readable medium of Aspect 11, wherein the set of inputs for the current frame comprise one or more of depth information, color information or motion vectors, and the program code further comprises program code to warp the recurrent input based on the one or more of depth information, the color information, or motion vectors.

[0099] Aspect 13: The non-transitory computer-readable medium of Aspect 11 or 12, wherein the program code further comprises: program code to apply the jitter offsets to the motion vectors to compensate for viewport jittering; and program code to adapt the jitter compensated motion vectors based on the depth information to provide antialiasing of an image in the current frame of the video game.

[00100] Aspect 14: The non-transitory⁷ computer-readable medium of any of Aspects 11-13, wherein the program code further comprises program code to generate, by the ANN, the reconstruction of the current frame of the video game based on a pixel-wise blending mask.

[00101] Aspect 15: The non-transitory computer-readable medium of any of Aspects 11-14, wherein the weights of the convolution layer are precomputed at inference time. [00102] Aspect 16: An apparatus, comprising: means for receiving, by an artificial neural network (ANN), a set of inputs for a current frame of a video game and a recurrent input based on a previous frame of the video game, wherein the current frame has a first resolution and the set of inputs for the current frame includes a jitter offset; means for estimating, by the ANN, weights of a convolution layer based on the jitter offset; and means for reconstructing, by the ANN, the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input, wherein the second resolution is greater than the first resolution.

[00103] Aspect 17: The apparatus of Aspect 1 , wherein the set of inputs for the current frame comprise one or more of depth information, color information or motion vectors, and the apparatus further comprises means for warping the recurrent input based on the one or more of depth information, the color information, or motion vectors.

[00104] Aspect 18: The apparatus of Aspect 16 or 17, further comprising: means for applying the jitter offsets to the motion vectors to compensate for viewport jittering; and means for adapting the jitter compensated motion vectors based on the depth information to provide anti-aliasing of an image in the current frame of the video game.

[00105] Aspect 19: The apparatus of any of Aspects 16-18, further comprising means for generating, by the ANN, the reconstructed current frame of the video game based on a pixel-wise blending mask.

[00106] Aspect 20: The apparatus of any of Aspects 16-19, wherein the weights of the convolution layer are precomputed at inference time.

[00107] In one aspect, the receiving means, estimating means and/or reconstructing means may be the CPU 102, program memory associated with the CPU 102, NPU 108, the dedicated memory block 118, fully connected layers 362, NPU 428 and/or the routing connection processing unit 216 configured to perform the functions recited. In another configuration, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.

[00108] The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to, a circuit, an application specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in the figures, those operations may have corresponding counterpart means-plus-function components with similar numbering.

[00109] As used, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g.. looking up in a table, a database or another data structure), ascertaining and the like. Additionally, “determining” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Furthermore, “determining” may include resolving, selecting, choosing, establishing, and the like.

[00110] As used, a phrase referring to “at least one of’ a list of items refers to any combination of those items, including single members. As an example, “at least one of: a. b, or c” is intended to cover: a, b, c, a-b. a-c, b-c, and a-b-c.

[00111] The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[00112] The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in any form of storage medium that is known in the art. Some examples of storage media that may be used include random access memory (RAM), read only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, a hard disk, a removable disk, a CD-ROM and so forth. A software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media. A storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

[00113] The methods disclosed comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

[00114] The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may comprise a processing system in a device. The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement signal processing functions. For certain aspects, a user interface (e.g.. keypad, display, mouse, joystick, etc.) may also be connected to the bus. The bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further.

[00115] The processor may be responsible for managing the bus and general processing, including the execution of software stored on the machine-readable media. The processor may be implemented with one or more general-purpose and/or specialpurpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software. Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Machine-readable media may include, by way of example, random access memory (RAM), flash memory, read only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable Read-only memory (EEPROM), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The machine-readable media may be embodied in a computer-program product. The computer-program product may comprise packaging materials.

[00116] In a hardware implementation, the machine-readable media may be part of the processing system separate from the processor. However, as those skilled in the art will readily appreciate, the machine-readable media, or any portion thereof, may be external to the processing system. By way of example, the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer product separate from the device, all which may be accessed by the processor through the bus interface. Alternatively, or in addition, the machine-readable media, or any portion thereof, may be integrated into the processor, such as the case may be with cache and/or general register files. Although the various components discussed may be described as having a specific location, such as a local component, they may also be configured in various ways, such as certain components being configured as part of a distributed computing system.

[00117] The processing system may be configured as a general-purpose processing system with one or more microprocessors providing the processor functionality and external memory providing at least a portion of the machine-readable media, all linked together with other supporting circuitry through an external bus architecture. Alternatively, the processing system may comprise one or more neuromorphic processors for implementing the neuron models and models of neural systems described. As another alternative, the processing system may be implemented with an application specific integrated circuit (ASIC) with the processor, the bus interface, the user interface, supporting circuitry', and at least a portion of the machine-readable media integrated into a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system.

[00118] The machine-readable media may comprise a number of software modules. The software modules include instructions that, when executed by the processor, cause the processing system to perform various functions. The software modules may include a transmission module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, a software module may be loaded into RAM from a hard drive when a triggering event occurs. During execution of the software module, the processor may load some of the instructions into cache to increase access speed. One or more cache lines may then be loaded into a general register file for execution by the processor. When referring to the functionality of a software module below, it will be understood that such functionality is implemented by the processor when executing instructions from that software module. Furthermore, it should be appreciated that aspects of the present disclosure result in improvements to the functioning of the processor, computer, machine, or other system implementing such aspects.

[00119] If implemented in software, the functions may be stored or transmitted over as one or more instructions or code on a computer-readable medium. Computer- readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Additionally, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (1R), radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Thus, in some aspects, computer-readable media may comprise non-transitory computer- readable media (e.g., tangible media). In addition, for other aspects computer-readable media may comprise transitory computer- readable media (e.g.. a signal). Combinations of the above should also be included within the scope of computer-readable media.

[00120] Thus, certain aspects may comprise a computer program product for performing the operations presented. For example, such a computer program product may comprise a computer-readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described. For certain aspects, the computer program product may include packaging material.

[00121] Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable. For example, such a device can be coupled to a server to facilitate the transfer of means for performing the methods described. Alternatively, various methods described can be provided via storage means (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a user terminal and/or base station can obtain the various methods upon coupling or providing the storage means to the device. Moreover, any other suitable technique for providing the methods and techniques described to a device can be utilized.

[00122] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes, and variations may be made in the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

CLAIMS WHAT IS CLAIMED IS:

1. An apparatus, comprising: at least one memory; and at least one processor coupled to the at least one memory, the at least one processor configured to: receive, by an artificial neural network (ANN), a set of inputs for a current frame of a video game and a recurrent input based on a previous frame of the video game, the current frame, wherein the current frame has a first resolution and the set of inputs for the current frame includes ajitter offset; estimate, by the ANN, weights of a convolution layer based on the jitter offset; and reconstruct, by the ANN, the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input, wherein the second resolution is greater than the first resolution.

2. The apparatus of claim 1, wherein the set of inputs for the current frame comprise one or more of depth information, color information or motion vectors, and the at least one processor is further configured to warp the recurrent input based on the one or more of depth information, the color information, or motion vectors.

3. The apparatus of claim 2, wherein the at least one processor is further configured to: apply the jitter offset to the motion vectors to compensate for viewport jittering; and adapt the jitter compensated motion vectors based on the depth information to provide anti-aliasing of an image in the current frame of the video game.

4. The apparatus of claim 1, further comprising generating, by the ANN, the reconstructed current frame of the video game based on a pixel-wise blending mask.

5. The apparatus of claim 1, wherein the weights of the convolution layer are precomputed at inference time.

6. A processor-implemented method comprising: receiving, by an artificial neural network (ANN), a set of inputs for a current frame of a video game and a recurrent input based on a previous frame of the video game, wherein the cunent frame has a first resolution and the set of inputs for the current frame includes a jitter offset; estimating, by the ANN, weights of a convolution layer based on the jitter offset; and reconstructing, by the ANN, the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input, wherein the second resolution is greater than the first resolution.

7. The processor-implemented method of claim 6, wherein the set of inputs for the current frame comprise one or more of depth information, color information or motion vectors, and the processor-implemented method further comprises warping the recurrent input based on the one or more of depth information, the color information, or motion vectors.

8. The processor-implemented method of claim 7, further comprising: applying the jitter offsets to the motion vectors to compensate for viewport jittering; and adapting the jitter compensated motion vectors based on the depth information to provide anti-aliasing of an image in the cunent frame of the video game.

9. The processor-implemented method of claim 6, wherein the reconstructed current frame is based on a pixel-wise blending mask.

10. The processor-implemented method of claim 6, wherein the w eights of the convolution layer are precomputed at inference time.

11. A non-transitory computer-readable medium having program code recorded thereon, the program code executed by a processor and comprising: program code to receive, by an artificial neural network (ANN), a set of inputs for a current frame of a video game and a recurrent input based on a previous frame of the video game, wherein the current frame has a first resolution and the set of inputs for the cunent frame includes a jitter offset; program code to estimate, by the ANN, weights of one or more convolution layers based on the jitter offsets; and program code to reconstruct, by the ANN, the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input, wherein the second resolution is greater than the first resolution.

12. The non-transitory computer-readable medium of claim 11, wherein the set of inputs for the current frame comprise one or more of depth information, color information or motion vectors, and the program code further comprises program code to warp the recurrent input based on the one or more of depth information, the color information, or motion vectors.

13. The non-transitory computer-readable medium of claim 12, wherein the program code further comprises: program code to apply the jitter offsets to the motion vectors to compensate for viewport jittering; and program code to adapt the jitter compensated motion vectors based on the depth information to provide anti-aliasing of an image in the current frame of the video game.

14. The non-transitory computer-readable medium of claim 11, wherein the program code further comprises program code to generate, by the ANN, the reconstruction of the current frame of the video game based on a pixel-wise blending mask.

15. The non-transitory computer-readable medium of claim 11, wherein the weights of the convolution layer are precomputed at inference time.

16. An apparatus, comprising: means for receiving, by an artificial neural network (ANN), a set of inputs for a current frame of a video game and a recurrent input based on a previous frame of the video game, wherein the current frame has a first resolution and the set of inputs for the current frame includes a jitter offset; means for estimating, by the ANN, weights of a convolution layer based on the jitter offset; and means for reconstructing, by the ANN, the current frame of the video game at a second resolution to generate a reconstructed current frame based on the set of inputs for the current frame of the video game and the recurrent input, wherein the second resolution is greater than the first resolution.

17. The apparatus of claim 16, wherein the set of inputs for the current frame comprise one or more of depth information, color information or motion vectors, and the apparatus further comprises means for warping the recurrent input based on the one or more of depth information, the color information, or motion vectors.

18. The apparatus of claim 17, further comprising: means for applying the jitter offsets to the motion vectors to compensate for viewport jittering; and means for adapting the jitter compensated motion vectors based on the depth information to provide anti-aliasing of an image in the current frame of the video game.

19. The apparatus of claim 16, further comprising means for generating, by the ANN, the reconstructed current frame of the video game based on a pixel-wise blending mask.

20. The apparatus of claim 16, wherein the weights of the convolution layer are precomputed at inference time.