EP4674076A1

EP4674076A1 - Block-code-based constellation shaping

Info

Publication number: EP4674076A1
Application number: EP23924676.2A
Authority: EP
Inventors: Changlong Xu; Liangming WU; Jian Li; Wei Liu; Kexin XIAO; Kangqi LIU; Hao Xu
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2023-03-02
Filing date: 2023-03-02
Publication date: 2026-01-07
Also published as: CN120752869A; WO2024178707A1

Abstract

Aspects of this disclosure provide techniques for block-code-based constellation shaping. An example method includes generating a first set of bits for transmission, generating and attaching a plurality of cyclic redundancy check bits to the first set of bits to obtain a second set of bits, generating a set of log likelihood ratios (LLRs) corresponding to the second set of bits, wherein a size of the set of LLRs depends on a number of physical resource blocks and a modulation and coding scheme configured for transmitting the second set of bits, decoding, according to a shaping code rate, the set of LLRs using a block code to obtain a sequence of shaping bits, generating a sequence of shaped symbols based, at least in part, on the sequence of shaping bits and the second set of bits, and transmitting the sequence of shaped symbols to a receiving device.

Description

BLOCK-CODE-BASED CONSTELLATION SHAPING

BACKGROUND

Field of the Disclosure
Aspects of the present disclosure relate to wireless communications, and more particularly, to techniques for block-code-based constellation shaping.
Description of Related Art
Wireless communications systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, broadcasts, or other similar types of services. These wireless communications systems may employ multiple-access technologies capable of supporting communications with multiple users by sharing available wireless communications system resources with those users
Although wireless communications systems have made great technological advancements over many years, challenges still exist. For example, complex and dynamic environments can still attenuate or block signals between wireless transmitters and wireless receivers. Accordingly, there is a continuous desire to improve the technical performance of wireless communications systems, including, for example: improving speed and data carrying capacity of communications, improving efficiency of the use of shared communications mediums, reducing power used by transmitters and receivers while performing communications, improving reliability of wireless communications, avoiding redundant transmissions and/or receptions and related processing, improving the coverage area of wireless communications, increasing the number and types of devices that can access wireless communications systems, increasing the ability for different types of devices to intercommunicate, increasing the number and type of wireless communications mediums available for use, and the like. Consequently, there exists a need for further improvements in wireless communications systems to overcome the aforementioned technical challenges and others.
SUMMARY
One aspect provides a method for wireless communication by a transmitting device. The method includes generating a first set of bits for transmission; generating and attaching a plurality of cyclic redundancy check (CRC) bits to the first set of bits to obtain a second set of bits for transmission; generating a set of log likelihood ratios (LLRs) corresponding to the second set of bits, wherein a size of the set of LLRs depends on a number of physical resource blocks (PRBs) configured for transmitting the second set of bits and a modulation and coding scheme (MCS) configured for transmitting the second set of bits; decoding, according to a shaping code rate, the set of LLRs using a block code to obtain a sequence of shaping bits; generating a sequence of shaped symbols based, at least in part, on the sequence of shaping bits and the second set of bits; and transmitting the sequence of shaped symbols to a receiving device.
Another aspect provides a method for wireless communication by a receiving device. The method includes receiving, from a transmitting device, a sequence of shaped symbols corresponding to a set of bits; converting the sequence of shaped symbols to a sequence of bit-level LLRs; decoding, based on a transport block size associated with the set of bits, the sequence of bit-level LLRs, using a forward error correction (FEC) code rate, to obtain a set of decoded bits, the set of decoded bits including a sequence of shaping bits, a sequence of shaped bits of the set of bits, and a remaining subset of non-shaped bits of the set of bits; performing, using a shaping code rate, a deshaping operation on the sequence of shaped bits based on the sequence of shaping bits to obtain a sequence of deshaped bits; and concatenating the sequence of deshaped bits with the remaining subset of non-shaped bits to obtain the set of bits.
Other aspects provide: an apparatus operable, configured, or otherwise adapted to perform any one or more of the aforementioned methods and/or those described elsewhere herein; a non-transitory, computer-readable media comprising instructions that, when executed by a processor of an apparatus, cause the apparatus to perform the aforementioned methods as well as those described elsewhere herein; a computer program product embodied on a computer-readable storage medium comprising code for performing the aforementioned methods as well as those described elsewhere herein; and/or an apparatus comprising means for performing the aforementioned methods as well as those described elsewhere herein. By way of example, an apparatus may comprise a processing system, a device with a processing system, or processing systems cooperating over one or more networks.
The following description and the appended figures set forth certain features for purposes of illustration.

BRIEF DESCRIPTION OF DRAWINGS

The appended figures depict certain features of the various aspects described herein and are not to be considered limiting of the scope of this disclosure.
FIG. 1 depicts an example wireless communications network.
FIG. 2 depicts an example disaggregated base station architecture.
FIG. 3 depicts aspects of an example base station and an example user equipment.
FIGS. 4A, 4B, 4C, and 4D depict various example aspects of data structures for a wireless communications network.
FIG. 5 depicts an example implementation of a transmitter and receiver.
FIG. 6 illustrates a communication system, including a transmitter and a receiver, employing block-code-based constellation shaping.
FIG. 7 depicts a method for wireless communications.
FIG. 8 depicts a method for wireless communications.
FIG. 9 depicts aspects of an example communications device.
FIG. 10 depicts aspects of an example communications device.

DETAILED DESCRIPTION

Aspects of the present disclosure provide apparatuses, methods, processing systems, and computer-readable mediums for block-code-based constellation shaping.
For example, a technique known as constellation shaping may be used to improve the performance of digital communication systems by shaping the constellation of a signal. The constellation of a signal refers to the set of possible signal points that can be transmitted, which are represented by a set of complex numbers in the complex plane.
In some cases, a goal of constellation shaping is to minimize an average signal power of a transmitted signal and to increase the throughput of a wireless communication network. In some cases, a shaping operation may be performed on an original set of bits for transmission to shape a constellation associated with this original set of bits and to minimize the average signal power of the transmission of the original set of bits. In some cases, the shaping operation may involve bit-masking a subset of bits of the original set of bits for transmission based on a shaping codeword. The shaping codeword may be obtained using on sequence of shaping bits that are generated based on the original set of bits and a particular block code.
While the techniques described above for constellation shaping may help to reduce transmission power associated with transmitting information, these techniques may not be aligned with the current channel encoding techniques defined by certain wireless communication standards. For example, in some cases, when decoding information, a receiver may need to know a transport block size associated with the set of data bits that are transmitted. However, unlink traditional techniques in which the transport block size may be equal to a number of bits of the set of bits input into an encoder, when constellation shaping is used, the set of bits input into the encoder include the original set of bits for transmission as well as the sequence of shaping bits. Accordingly, using existing techniques for determining the transport block size may lead to an inaccurate transport block size being determined, which may lead to failures in the decoding process. Failures in the decoding process may, in turn, lead to one or more retransmissions of the improperly decoded information, unnecessarily consuming time and frequency resources within a wireless network and power resources at a transmitter and receiver.
Accordingly, aspects of the present disclosure provide techniques for block-code-based constellation shaping that help to reduce or eliminate the issues described above. The techniques presented herein may allow for constellation shaping to be adapted for use with current channel encoding techniques associated with certain wireless communication standards. For example, in some cases, the techniques may allow a receiver to properly determine the transport block size by taking into account the number of shaping bits that are encoded with the original set of bits. By taking into account the shaping bits when determining the transport block size, the receiver can improve the chances that the set of bits are correctly decoded, thereby avoiding or reducing the unnecessary retransmission of the bits and associated wasted time, frequency, and power resources.
Introduction to Wireless Communications Networks
The techniques and methods described herein may be used for various wireless communications networks. While aspects may be described herein using terminology commonly associated with 3G, 4G, and/or 5G wireless technologies, aspects of the present disclosure may likewise be applicable to other communications systems and standards not explicitly mentioned herein.
FIG. 1 depicts an example of a wireless communications network 100, in which aspects described herein may be implemented.
Generally, wireless communications network 100 includes various network entities (alternatively, network elements or network nodes) . A network entity is generally a communications device and/or a communications function performed by a communications device (e.g., a user equipment (UE) , a base station (BS) , a component of a BS, a server, etc. ) . For example, various functions of a network as well as various devices associated with and interacting with a network may be considered network entities. Further, wireless communications network 100 includes terrestrial aspects, such as ground-based network entities (e.g., BSs 102) , and non-terrestrial aspects, such as satellite 140 and aircraft 145, which may include network entities on-board (e.g., one or more BSs) capable of communicating with other network elements (e.g., terrestrial BSs) and user equipments.
In the depicted example, wireless communications network 100 includes BSs 102, UEs 104, and one or more core networks, such as an Evolved Packet Core (EPC) 160 and 5G Core (5GC) network 190, which interoperate to provide communications services over various communications links, including wired and wireless links.
FIG. 1 depicts various example UEs 104, which may more generally include: a cellular phone, smart phone, session initiation protocol (SIP) phone, laptop, personal digital assistant (PDA) , satellite radio, global positioning system, multimedia device, video device, digital audio player, camera, game console, tablet, smart device, wearable device, vehicle, electric meter, gas pump, large or small kitchen appliance, healthcare device, implant, sensor/actuator, display, internet of things (IoT) devices, always on (AON) devices, edge processing devices, or other similar devices. UEs 104 may also be referred to more generally as a mobile device, a wireless device, a wireless communications device, a station, a mobile station, a subscriber station, a mobile subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a remote device, an access terminal, a mobile terminal, a wireless terminal, a remote terminal, a handset, and others.
BSs 102 wirelessly communicate with (e.g., transmit signals to or receive signals from) UEs 104 via communications links 120. The communications links 120 between BSs 102 and UEs 104 may include uplink (UL) (also referred to as reverse link) transmissions from a UE 104 to a BS 102 and/or downlink (DL) (also referred to as forward link) transmissions from a BS 102 to a UE 104. The communications links 120 may use multiple-input and multiple-output (MIMO) antenna technology, including spatial multiplexing, beamforming, and/or transmit diversity in various aspects.
BSs 102 may generally include: a NodeB, enhanced NodeB (eNB) , next generation enhanced NodeB (ng-eNB) , next generation NodeB (gNB or gNodeB) , access point, base transceiver station, radio base station, radio transceiver, transceiver function, transmission reception point, and/or others. Each of BSs 102 may provide communications coverage for a respective geographic coverage area 110, which may sometimes be referred to as a cell, and which may overlap in some cases (e.g., small cell 102’ may have a coverage area 110’ that overlaps the coverage area 110 of a macro cell) . A BS may, for example, provide communications coverage for a macro cell (covering relatively large geographic area) , a pico cell (covering relatively smaller geographic area, such as a sports stadium) , a femto cell (relatively smaller geographic area (e.g., a home) ) , and/or other types of cells.
While BSs 102 are depicted in various aspects as unitary communications devices, BSs 102 may be implemented in various configurations. For example, one or more components of a base station may be disaggregated, including a central unit (CU) , one or more distributed units (DUs) , one or more radio units (RUs) , a Near-Real Time (Near-RT) RAN Intelligent Controller (RIC) , or a Non-Real Time (Non-RT) RIC, to name a few examples. In another example, various aspects of a base station may be virtualized. More generally, a base station (e.g., BS 102) may include components that are located at a single physical location or components located at various physical locations. In examples in which a base station includes components that are located at various physical locations, the various components may each perform functions such that, collectively, the various components achieve functionality that is similar to a base station that is located at a single physical location. In some aspects, a base station including components that are located at various physical locations may be referred to as a disaggregated radio access network architecture, such as an Open RAN (O-RAN) or Virtualized RAN (VRAN) architecture. FIG. 2 depicts and describes an example disaggregated base station architecture.
Different BSs 102 within wireless communications network 100 may also be configured to support different radio access technologies, such as 3G, 4G, and/or 5G. For example, BSs 102 configured for 4G LTE (collectively referred to as Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN) ) may interface with the EPC 160 through first backhaul links 132 (e.g., an S1 interface) . BSs 102 configured for 5G (e.g., 5G NR or Next Generation RAN (NG-RAN) ) may interface with 5GC 190 through second backhaul links 184. BSs 102 may communicate directly or indirectly (e.g., through the EPC 160 or 5GC 190) with each other over third backhaul links 134 (e.g., X2 interface) , which may be wired or wireless.
Wireless communications network 100 may subdivide the electromagnetic spectrum into various classes, bands, channels, or other features. In some aspects, the subdivision is provided based on wavelength and frequency, where frequency may also be referred to as a carrier, a subcarrier, a frequency channel, a tone, or a subband. For example, 3GPP currently defines Frequency Range 1 (FR1) as including 410 MHz –7125 MHz, which is often referred to (interchangeably) as “Sub-6 GHz” . Similarly, 3GPP currently defines Frequency Range 2 (FR2) as including 24, 250 MHz –52, 600 MHz, which is sometimes referred to (interchangeably) as a “millimeter wave” ( “mmW” or “mmWave” ) . A base station configured to communicate using mmWave/near mmWave radio frequency bands (e.g., a mmWave base station such as BS 180) may utilize beamforming (e.g., 182) with a UE (e.g., 104) to improve path loss and range.
The communications links 120 between BSs 102 and, for example, UEs 104, may be through one or more carriers, which may have different bandwidths (e.g., 5, 10, 15, 20, 100, 400, and/or other MHz) , and which may be aggregated in various aspects. Carriers may or may not be adjacent to each other. Allocation of carriers may be asymmetric with respect to DL and UL (e.g., more or fewer carriers may be allocated for DL than for UL) .
Communications using higher frequency bands may have higher path loss and a shorter range compared to lower frequency communications. Accordingly, certain base stations (e.g., 180 in FIG. 1) may utilize beamforming 182 with a UE 104 to improve path loss and range. For example, BS 180 and the UE 104 may each include a plurality of antennas, such as antenna elements, antenna panels, and/or antenna arrays to facilitate the beamforming. In some cases, BS 180 may transmit a beamformed signal to UE 104 in one or more transmit directions 182’ . UE 104 may receive the beamformed signal from the BS 180 in one or more receive directions 182”. UE 104 may also transmit a beamformed signal to the BS 180 in one or more transmit directions 182”. BS 180 may also receive the beamformed signal from UE 104 in one or more receive directions 182’ . BS 180 and UE 104 may then perform beam training to determine the best receive and transmit directions for each of BS 180 and UE 104. Notably, the transmit and receive directions for BS 180 may or may not be the same. Similarly, the transmit and receive directions for UE 104 may or may not be the same.
Wireless communications network 100 further includes a Wi-Fi AP 150 in communication with Wi-Fi stations (STAs) 152 via communications links 154 in, for example, a 2.4 GHz and/or 5 GHz unlicensed frequency spectrum.
Certain UEs 104 may communicate with each other using device-to-device (D2D) communications link 158. D2D communications link 158 may use one or more sidelink channels, such as a physical sidelink broadcast channel (PSBCH) , a physical sidelink discovery channel (PSDCH) , a physical sidelink shared channel (PSSCH) , a physical sidelink control channel (PSCCH) , and/or a physical sidelink feedback channel (PSFCH) .
EPC 160 may include various functional components, including: a Mobility Management Entity (MME) 162, other MMEs 164, a Serving Gateway 166, a Multimedia Broadcast Multicast Service (MBMS) Gateway 168, a Broadcast Multicast Service Center (BM-SC) 170, and/or a Packet Data Network (PDN) Gateway 172, such as in the depicted example. MME 162 may be in communication with a Home Subscriber Server (HSS) 174. MME 162 is the control node that processes the signaling between the UEs 104 and the EPC 160. Generally, MME 162 provides bearer and connection management.
Generally, user Internet protocol (IP) packets are transferred through Serving Gateway 166, which itself is connected to PDN Gateway 172. PDN Gateway 172 provides UE IP address allocation as well as other functions. PDN Gateway 172 and the BM-SC 170 are connected to IP Services 176, which may include, for example, the Internet, an intranet, an IP Multimedia Subsystem (IMS) , a Packet Switched (PS) streaming service, and/or other IP services.
BM-SC 170 may provide functions for MBMS user service provisioning and delivery. BM-SC 170 may serve as an entry point for content provider MBMS transmission, may be used to authorize and initiate MBMS Bearer Services within a public land mobile network (PLMN) , and/or may be used to schedule MBMS transmissions. MBMS Gateway 168 may be used to distribute MBMS traffic to the BSs 102 belonging to a Multicast Broadcast Single Frequency Network (MBSFN) area broadcasting a particular service, and/or may be responsible for session management (start/stop) and for collecting eMBMS related charging information.
5GC 190 may include various functional components, including: an Access and Mobility Management Function (AMF) 192, other AMFs 193, a Session Management Function (SMF) 194, and a User Plane Function (UPF) 195. AMF 192 may be in communication with Unified Data Management (UDM) 196.
AMF 192 is a control node that processes signaling between UEs 104 and 5GC 190. AMF 192 provides, for example, quality of service (QoS) flow and session management.
Internet protocol (IP) packets are transferred through UPF 195, which is connected to the IP Services 197, and which provides UE IP address allocation as well as other functions for 5GC 190. IP Services 197 may include, for example, the Internet, an intranet, an IMS, a PS streaming service, and/or other IP services.
In various aspects, a network entity or network node can be implemented as an aggregated base station, as a disaggregated base station, a component of a base station, an integrated access and backhaul (IAB) node, a relay node, a sidelink node, to name a few examples.
FIG. 2 depicts an example disaggregated base station 200 architecture. The disaggregated base station 200 architecture may include one or more central units (CUs) 210 that can communicate directly with a core network 220 via a backhaul link, or indirectly with the core network 220 through one or more disaggregated base station units (such as a Near-Real Time (Near-RT) RAN Intelligent Controller (RIC) 225 via an E2 link, or a Non-Real Time (Non-RT) RIC 215 associated with a Service Management and Orchestration (SMO) Framework 205, or both) . A CU 210 may communicate with one or more distributed units (DUs) 230 via respective midhaul links, such as an F1 interface. The DUs 230 may communicate with one or more radio units (RUs) 240 via respective fronthaul links. The RUs 240 may communicate with respective UEs 104 via one or more radio frequency (RF) access links. In some implementations, the UE 104 may be simultaneously served by multiple RUs 240.
Each of the units, e.g., the CUs 210, the DUs 230, the RUs 240, as well as the Near-RT RICs 225, the Non-RT RICs 215 and the SMO Framework 205, may include one or more interfaces or be coupled to one or more interfaces configured to receive or transmit signals, data, or information (collectively, signals) via a wired or wireless transmission medium. Each of the units, or an associated processor or controller providing instructions to the communications interfaces of the units, can be configured to communicate with one or more of the other units via the transmission medium. For example, the units can include a wired interface configured to receive or transmit signals over a wired transmission medium to one or more of the other units. Additionally or alternatively, the units can include a wireless interface, which may include a receiver, a transmitter or transceiver (such as a radio frequency (RF) transceiver) , configured to receive or transmit signals, or both, over a wireless transmission medium to one or more of the other units.
In some aspects, the CU 210 may host one or more higher layer control functions. Such control functions can include radio resource control (RRC) , packet data convergence protocol (PDCP) , service data adaptation protocol (SDAP) , or the like. Each control function can be implemented with an interface configured to communicate signals with other control functions hosted by the CU 210. The CU 210 may be configured to handle user plane functionality (e.g., Central Unit –User Plane (CU-UP) ) , control plane functionality (e.g., Central Unit –Control Plane (CU-CP) ) , or a combination thereof. In some implementations, the CU 210 can be logically split into one or more CU-UP units and one or more CU-CP units. The CU-UP unit can communicate bidirectionally with the CU-CP unit via an interface, such as the E1 interface when implemented in an O-RAN configuration. The CU 210 can be implemented to communicate with the DU 230, as necessary, for network control and signaling.
The DU 230 may correspond to a logical unit that includes one or more base station functions to control the operation of one or more RUs 240. In some aspects, the DU 230 may host one or more of a radio link control (RLC) layer, a medium access control (MAC) layer, and one or more high physical (PHY) layers (such as modules for forward error correction (FEC) encoding and decoding, scrambling, modulation and demodulation, or the like) depending, at least in part, on a functional split, such as those defined by the 3^rd Generation Partnership Project (3GPP) . In some aspects, the DU 230 may further host one or more low PHY layers. Each layer (or module) can be implemented with an interface configured to communicate signals with other layers (and modules) hosted by the DU 230, or with the control functions hosted by the CU 210.
Lower-layer functionality can be implemented by one or more RUs 240. In some deployments, an RU 240, controlled by a DU 230, may correspond to a logical node that hosts RF processing functions, or low-PHY layer functions (such as performing fast Fourier transform (FFT) , inverse FFT (iFFT) , digital beamforming, physical random access channel (PRACH) extraction and filtering, or the like) , or both, based at least in part on the functional split, such as a lower layer functional split. In such an architecture, the RU (s) 240 can be implemented to handle over the air (OTA) communications with one or more UEs 104. In some implementations, real-time and non-real-time aspects of control and user plane communications with the RU (s) 240 can be controlled by the corresponding DU 230. In some scenarios, this configuration can enable the DU (s) 230 and the CU 210 to be implemented in a cloud-based RAN architecture, such as a vRAN architecture.
The SMO Framework 205 may be configured to support RAN deployment and provisioning of non-virtualized and virtualized network elements. For non-virtualized network elements, the SMO Framework 205 may be configured to support the deployment of dedicated physical resources for RAN coverage requirements which may be managed via an operations and maintenance interface (such as an O1 interface) . For virtualized network elements, the SMO Framework 205 may be configured to interact with a cloud computing platform (such as an open cloud (O-Cloud) 290) to perform network element life cycle management (such as to instantiate virtualized network elements) via a cloud computing platform interface (such as an O2 interface) . Such virtualized network elements can include, but are not limited to, CUs 210, DUs 230, RUs 240 and Near-RT RICs 225. In some implementations, the SMO Framework 205 can communicate with a hardware aspect of a 4G RAN, such as an open eNB (O-eNB) 211, via an O1 interface. Additionally, in some implementations, the SMO Framework 205 can communicate directly with one or more RUs 240 via an O1 interface. The SMO Framework 205 also may include a Non-RT RIC 215 configured to support functionality of the SMO Framework 205.
The Non-RT RIC 215 may be configured to include a logical function that enables non-real-time control and optimization of RAN elements and resources, Artificial Intelligence/Machine Learning (AI/ML) workflows including model training and updates, or policy-based guidance of applications/features in the Near-RT RIC 225. The Non-RT RIC 215 may be coupled to or communicate with (such as via an A1 interface) the Near-RT RIC 225. The Near-RT RIC 225 may be configured to include a logical function that enables near-real-time control and optimization of RAN elements and resources via data collection and actions over an interface (such as via an E2 interface) connecting one or more CUs 210, one or more DUs 230, or both, as well as an O-eNB, with the Near-RT RIC 225.
In some implementations, to generate AI/ML models to be deployed in the Near-RT RIC 225, the Non-RT RIC 215 may receive parameters or external enrichment information from external servers. Such information may be utilized by the Near-RT RIC 225 and may be received at the SMO Framework 205 or the Non-RT RIC 215 from non-network data sources or from network functions. In some examples, the Non-RT RIC 215 or the Near-RT RIC 225 may be configured to tune RAN behavior or performance. For example, the Non-RT RIC 215 may monitor long-term trends and patterns for performance and employ AI/ML models to perform corrective actions through the SMO Framework 205 (such as reconfiguration via O1) or via creation of RAN management policies (such as A1 policies) .
FIG. 3 depicts aspects of an example BS 102 and a UE 104.
Generally, BS 102 includes various processors (e.g., 320, 330, 338, and 340) , antennas 334a-t (collectively 334) , transceivers 332a-t (collectively 332) , which include modulators and demodulators, and other aspects, which enable wireless transmission of data (e.g., data source 312) and wireless reception of data (e.g., data sink 339) . For example, BS 102 may send and receive data between BS 102 and UE 104. BS 102 includes controller/processor 340, which may be configured to implement various functions described herein related to wireless communications.
Generally, UE 104 includes various processors (e.g., 358, 364, 366, and 380) , antennas 352a-r (collectively 352) , transceivers 354a-r (collectively 354) , which include modulators and demodulators, and other aspects, which enable wireless transmission of data (e.g., retrieved from data source 362) and wireless reception of data (e.g., provided to data sink 360) . UE 104 includes controller/processor 380, which may be configured to implement various functions described herein related to wireless communications.
In regards to an example downlink transmission, BS 102 includes a transmit processor 320 that may receive data from a data source 312 and control information from a controller/processor 340. The control information may be for the physical broadcast channel (PBCH) , physical control format indicator channel (PCFICH) , physical HARQ indicator channel (PHICH) , physical downlink control channel (PDCCH) , group common PDCCH (GC PDCCH) , and/or others. The data may be for the physical downlink shared channel (PDSCH) , in some examples.
Transmit processor 320 may process (e.g., encode and symbol map) the data and control information to obtain data symbols and control symbols, respectively. Transmit processor 320 may also generate reference symbols, such as for the primary synchronization signal (PSS) , secondary synchronization signal (SSS) , PBCH demodulation reference signal (DMRS) , and channel state information reference signal (CSI-RS) .
Transmit (TX) multiple-input multiple-output (MIMO) processor 330 may perform spatial processing (e.g., precoding) on the data symbols, the control symbols, and/or the reference symbols, if applicable, and may provide output symbol streams to the modulators (MODs) in transceivers 332a-332t. Each modulator in transceivers 332a-332t may process a respective output symbol stream to obtain an output sample stream. Each modulator may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain a downlink signal. Downlink signals from the modulators in transceivers 332a-332t may be transmitted via the antennas 334a-334t, respectively.
In order to receive the downlink transmission, UE 104 includes antennas 352a-352r that may receive the downlink signals from the BS 102 and may provide received signals to the demodulators (DEMODs) in transceivers 354a-354r, respectively. Each demodulator in transceivers 354a-354r may condition (e.g., filter, amplify, downconvert, and digitize) a respective received signal to obtain input samples. Each demodulator may further process the input samples to obtain received symbols.
MIMO detector 356 may obtain received symbols from all the demodulators in transceivers 354a-354r, perform MIMO detection on the received symbols if applicable, and provide detected symbols. Receive processor 358 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for the UE 104 to a data sink 360, and provide decoded control information to a controller/processor 380.
In regards to an example uplink transmission, UE 104 further includes a transmit processor 364 that may receive and process data (e.g., for the PUSCH) from a data source 362 and control information (e.g., for the physical uplink control channel (PUCCH) ) from the controller/processor 380. Transmit processor 364 may also generate reference symbols for a reference signal (e.g., for the sounding reference signal (SRS) ) . The symbols from the transmit processor 364 may be precoded by a TX MIMO processor 366 if applicable, further processed by the modulators in transceivers 354a-354r (e.g., for SC-FDM) , and transmitted to BS 102.
At BS 102, the uplink signals from UE 104 may be received by antennas 334a-t, processed by the demodulators in transceivers 332a-332t, detected by a MIMO detector 336 if applicable, and further processed by a receive processor 338 to obtain decoded data and control information sent by UE 104. Receive processor 338 may provide the decoded data to a data sink 339 and the decoded control information to the controller/processor 340.
Memories 342 and 382 may store data and program codes for BS 102 and UE 104, respectively.
Scheduler 344 may schedule UEs for data transmission on the downlink and/or uplink.
In various aspects, BS 102 may be described as transmitting and receiving various types of data associated with the methods described herein. In these contexts, “transmitting” may refer to various mechanisms of outputting data, such as outputting data from data source 312, scheduler 344, memory 342, transmit processor 320, controller/processor 340, TX MIMO processor 330, transceivers 332a-t, antenna 334a-t, and/or other aspects described herein. Similarly, “receiving” may refer to various mechanisms of obtaining data, such as obtaining data from antennas 334a-t, transceivers 332a-t, RX MIMO detector 336, controller/processor 340, receive processor 338, scheduler 344, memory 342, and/or other aspects described herein.
In various aspects, UE 104 may likewise be described as transmitting and receiving various types of data associated with the methods described herein. In these contexts, “transmitting” may refer to various mechanisms of outputting data, such as outputting data from data source 362, memory 382, transmit processor 364, controller/processor 380, TX MIMO processor 366, transceivers 354a-t, antenna 352a-t, and/or other aspects described herein. Similarly, “receiving” may refer to various mechanisms of obtaining data, such as obtaining data from antennas 352a-t, transceivers 354a-t, RX MIMO detector 356, controller/processor 380, receive processor 358, memory 382, and/or other aspects described herein.
In some aspects, a processor may be configured to perform various operations, such as those associated with the methods described herein, and transmit (output) to or receive (obtain) data from another interface that is configured to transmit or receive, respectively, the data.
FIGS. 4A, 4B, 4C, and 4D depict aspects of data structures for a wireless communications network, such as wireless communications network 100 of FIG. 1.
In particular, FIG. 4A is a diagram 400 illustrating an example of a first subframe within a 5G (e.g., 5G NR) frame structure, FIG. 4B is a diagram 430 illustrating an example of DL channels within a 5G subframe, FIG. 4C is a diagram 450 illustrating an example of a second subframe within a 5G frame structure, and FIG. 4D is a diagram 480 illustrating an example of UL channels within a 5G subframe.
Wireless communications systems may utilize orthogonal frequency division multiplexing (OFDM) with a cyclic prefix (CP) on the uplink and downlink. Such systems may also support half-duplex operation using time division duplexing (TDD) . OFDM and single-carrier frequency division multiplexing (SC-FDM) partition the system bandwidth (e.g., as depicted in FIGS. 4B and 4D) into multiple orthogonal subcarriers. Each subcarrier may be modulated with data. Modulation symbols may be sent in the frequency domain with OFDM and/or in the time domain with SC-FDM.
A wireless communications frame structure may be frequency division duplex (FDD) , in which, for a particular set of subcarriers, subframes within the set of subcarriers are dedicated for either DL or UL. Wireless communications frame structures may also be time division duplex (TDD) , in which, for a particular set of subcarriers, subframes within the set of subcarriers are dedicated for both DL and UL.
In FIG. 4A and 4C, the wireless communications frame structure is TDD where D is DL, U is UL, and X is flexible for use between DL/UL. UEs may be configured with a slot format through a received slot format indicator (SFI) (dynamically through DL control information (DCI) , or semi-statically/statically through radio resource control (RRC) signaling) . In the depicted examples, a 10 ms frame is divided into 10 equally sized 1 ms subframes. Each subframe may include one or more time slots. In some examples, each slot may include 7 or 14 symbols, depending on the slot format. Subframes may also include mini-slots, which generally have fewer symbols than an entire slot. Other wireless communications technologies may have a different frame structure and/or different channels.
In certain aspects, the number of slots within a subframe is based on a slot configuration and a numerology. For example, for slot configuration 0, different numerologies (μ) 0 to 5 allow for 1, 2, 4, 8, 16, and 32 slots, respectively, per subframe. For slot configuration 1, different numerologies 0 to 2 allow for 2, 4, and 8 slots, respectively, per subframe. Accordingly, for slot configuration 0 and numerology μ, there are 14 symbols/slot and 2μ slots/subframe. The subcarrier spacing and symbol length/duration are a function of the numerology. The subcarrier spacing may be equal to 2^μ×15 kHz, where μ is the numerology 0 to 5. As such, the numerology μ=0 has a subcarrier spacing of 15 kHz and the numerology μ=5 has a subcarrier spacing of 480 kHz. The symbol length/duration is inversely related to the subcarrier spacing. FIGS. 4A, 4B, 4C, and 4D provide an example of slot configuration 0 with 14 symbols per slot and numerology μ=2 with 4 slots per subframe. The slot duration is 0.25 ms, the subcarrier spacing is 60 kHz, and the symbol duration is approximately 16.67 μs.
As depicted in FIGS. 4A, 4B, 4C, and 4D, a resource grid may be used to represent the frame structure. Each time slot includes a resource block (RB) (also referred to as physical RBs (PRBs) ) that extends, for example, 12 consecutive subcarriers. The resource grid is divided into multiple resource elements (REs) . The number of bits carried by each RE depends on the modulation scheme.
As illustrated in FIG. 4A, some of the REs carry reference (pilot) signals (RS) for a UE (e.g., UE 104 of FIGS. 1 and 3) . The RS may include demodulation RS (DMRS) and/or channel state information reference signals (CSI-RS) for channel estimation at the UE.The RS may also include beam measurement RS (BRS) , beam refinement RS (BRRS) , and/or phase tracking RS (PT-RS) .
FIG. 4B illustrates an example of various DL channels within a subframe of a frame. The physical downlink control channel (PDCCH) carries DCI within one or more control channel elements (CCEs) , each CCE including, for example, nine RE groups (REGs) , each REG including, for example, four consecutive REs in an OFDM symbol.
A primary synchronization signal (PSS) may be within symbol 2 of particular subframes of a frame. The PSS is used by a UE (e.g., 104 of FIGS. 1 and 3) to determine subframe/symbol timing and a physical layer identity.
A secondary synchronization signal (SSS) may be within symbol 4 of particular subframes of a frame. The SSS is used by a UE to determine a physical layer cell identity group number and radio frame timing.
Based on the physical layer identity and the physical layer cell identity group number, the UE can determine a physical cell identifier (PCI) . Based on the PCI, the UE can determine the locations of the aforementioned DMRS. The physical broadcast channel (PBCH) , which carries a master information block (MIB) , may be logically grouped with the PSS and SSS to form a synchronization signal (SS) /PBCH block. The MIB provides a number of RBs in the system bandwidth and a system frame number (SFN) . The physical downlink shared channel (PDSCH) carries user data, broadcast system information not transmitted through the PBCH such as system information blocks (SIBs) , and/or paging messages.
As illustrated in FIG. 4C, some of the REs carry DMRS (indicated as R for one particular configuration, but other DMRS configurations are possible) for channel estimation at the base station. The UE may transmit DMRS for the PUCCH and DMRS for the PUSCH. The PUSCH DMRS may be transmitted, for example, in the first one or two symbols of the PUSCH. The PUCCH DMRS may be transmitted in different configurations depending on whether short or long PUCCHs are transmitted and depending on the particular PUCCH format used. UE 104 may transmit sounding reference signals (SRS) . The SRS may be transmitted, for example, in the last symbol of a subframe. The SRS may have a comb structure, and a UE may transmit SRS on one of the combs. The SRS may be used by a base station for channel quality estimation to enable frequency-dependent scheduling on the UL.
FIG. 4D illustrates an example of various UL channels within a subframe of a frame. The PUCCH may be located as indicated in one configuration. The PUCCH carries uplink control information (UCI) , such as scheduling requests, a channel quality indicator (CQI) , a precoding matrix indicator (PMI) , a rank indicator (RI) , and HARQ ACK/NACK feedback. The PUSCH carries data, and may additionally be used to carry a buffer status report (BSR) , a power headroom report (PHR) , and/or UCI.
Introduction to Probabilistic Amplitude Shaping
FIG. 5 illustrates a communication system employing probabilistic amplitude shaping. Probabilistic amplitude shaping (PAS) utilizes reverse concatenation whereby the shaping precedes FEC coding.
The communication system 500 includes a wireless transmitter 501 and a wireless receiver 503. For example, an information source 502 may generate k information bits that is received by an amplitude shaper 504. The amplitude shaper 504 may generate a sequence of symbols (e.g., n symbols in a fixed-to-fixed scheme orsymbols in a variable-to-fixed scheme) . The sequence of symbols (n symbols orsymbols) may be received by an amplitude to bit component 506 and then an FEC encoder 508 to produce a set of bits. In some examples, some of the bits are shaped and others are uniformly distributed. After the encoding, the bits are mapped, e.g., to quadrature amplitude modulation (QAM) symbols by a QAM mapping component 510. A signal 511 (e.g., the symbols) is then transmitted over the wireless medium to the wireless receiver 503, e.g., over a channel 512.
At the wireless receiver 503, the signal 511 is received by a bitwise log-likelihood ratios (LLR) demapper component 514 to demap the symbols of the signal 511. The demapped symbols are received by the FEC decoder 516 and then a bit to amplitude component 518 to decode the bits. The decoded bits are provided to an amplitude deshaper 520 to distribute the received bits (e.g., uniformly) , which may then be sent to their destination.
Amplitude shaper 504 can also be known as or an implementation of a distribution matcher. In some aspects, a distribution matcher includes a decompressor (e.g., a decoder) to convert a sequence of information bits (u) into a set of symbols. The sequence of information bits (u) may be uniformly distributed. In an example, in 5G NR, the sequence of information bits may be uniformly distributed. The decompressor may generate the sequence of symbols based on a target probability mass function (PMF) , such as a Maxwell-Boltzmann Distribution, and a symbol block length (n) . The sequence of symbols may be transmitted to a receiver for processing to determine the transmitted information.
The distribution matcher may also include a compressor (e.g., an encoder) to convert the set of symbols into a sequence of compressed information bitsIn a fixed-to-fixed scheme, the distribution matcher may include a comparator to compare the sequence of information bits (u) to the sequence of compressed information bitsto determine how many information bits were not converted into the set of symbols. In some examples, the distribution matcher may provide the output of the comparator to the receiver so that the receiver can determine how to process the set of symbols. For example, based on a compressor at the receiver, the receiver may compress the set of symbols to generate information bits based on the target PMF, which may result in extra bits. The receiver may use the output of the comparator (e.g., discard signaling) to determine how many bits to discard.
Alternatively, the distribution matcher may employ a variable-to-fixed scheme in which the decompressor is configured with a “back-off” limit. The back-off limit may limit the amount of information bits that the decompressor may convert to the set of symbols so that extra bits are not transmitted to the receiver for discarding. Moreover, the variable-to-fixed scheme may limit the amount of overhead (e.g., compared to the fixed-to-fixed scheme) as a comparator is not needed and, thus, the distribution matcher may forego transmitting discard signaling with information about the number of bits to discard at the receiver. In such examples, when employing the variable-to-fixed scheme, the rate loss compared to target entropy may be improved compared to when employing the fixed-to-fixed scheme.
Aspects Related to Block-Code-Based Constellation Shaping
In some cases, a technique known as constellation shaping may be used to improve the performance of digital communication systems by shaping the constellation of a signal. The constellation of a signal refers to the set of possible signal points that can be transmitted, which are represented by a set of complex numbers in the complex plane.
A traditional method for choosing the signal points in a constellation is to minimize the average energy of the signal. However, this may not always result in optimal performance for the communication system. Constellation shaping modifies the signal points in a constellation in order to improve the performance of the communication system. More specifically, for example, a main benefit of constellation shaping is that it allows for the use of non-uniform constellations, which can result in a significant improvement in performance compared to traditional uniform constellations. By shaping the constellation in this way, it can improve the performance of the communication system in terms of its error rate, capacity, or power efficiency.
There are two main ways of implementing constellation shaping: geometric constellation shaping (GCS) and probabilistic constellation shaping (PCS) . GCS focuses on shaping the geometric properties of the signal points, such as their distance to the origin, their distance to other signal points, or their angle with respect to a reference axis. The goal of GCS is to optimize the placement of the signal points in the complex plane in order to improve the performance of the communication system. However, GCS may not be the best option for some communication systems, as it can be sensitive to channel estimation errors and may not be able to adapt to changing channel conditions. Additionally, GCS has some drawbacks such as lower gains and high demodulation complexity, which can result in increased computational cost GCS, making it less appealing in some cases.
On the other hand, PCS modifies the probability distribution of the signal points in a constellation in order to minimize an average energy of the signal and to improve the performance of the communication system. This can be achieved by adjusting the probabilities of the different signal points, or by adding or removing signal points from the constellation, which may result in a non-uniform constellation. In some cases, the adjusting of probabilities or adding/removing signal points in a constellation may be performed based on a signal to noise ratio (SNR) associated with a wireless channel over which signals are to be transmitted. The use of non-uniform constellations may result in a significant improvement in performance compared to traditional uniform constellations. For example, non-uniform constellations may have a higher density of signal points in the regions of the complex plane where the channel noise is low, and a lower density of signal points in the regions where the channel noise is high. This allows for a more efficient use of the signal power, resulting in a lower bit error rate and a higher data rate.
In some cases, another technique to minimize the average signal power of a transmitted signal may involve modifying a bit sequence of the transmitted signal. In some cases, modifying the bit sequence of the transmitted signal may involve applying a bit-mask to a most significant bit (MSB) of the bit sequence to lower the average signal power of the transmitted signal. For example, a bit-level and symbol transmit power may have a certain relationship in which a first bit (e.g., b0) (excluding a sign bit) may control the transmit power of a symbol ‘s’ of the transmitted signal (e.g., assuming gray mapping) than other bits. As a result, if bit u0 is transmitted with a bit value of 0 (zero) , then the transmit power associated with symbol ‘s’ of the transmitted signal may be lower as compared to a bit value of 1 (one) (e.g., ( ‘1’ , ’ 9’ ) , vs. (’ 25’ , ’ 49’ ) ) , as shown in the Table 1 below.
Table 1
In some cases, to perform constellation shaping and the bit-masking of certain bits of a transmitted signal, a transmitter may first identify an original set of bits for transmission. Thereafter, the transmitter may generate a set of LLRs based on the original set of bits. In some cases, a goal of constellation shaping is to generate a cover code that maximizes power savings after bit-masking. This may be achieved, in some cases, the by generating LLRs for the set of bits according to how much power is saved by the flipping of a most significant bit (MSB) of a symbol. For example, with reference to Table 2, below, assuming that data bits (u₀, u₁) in a particular symbol corresponding to the set of bits are equal to (1, 1) (e.g., see symbol index 2 in Table 2) , flipping (e.g., masking) u₀ such thatthe associated power change and LLR is 16. For example, as shown in Table 2, a transmit power associated with the original bits values ofu₁) = (1, 1) is while the transmit power associated with flipping u₀ such thatis 25. As such, the reduction in power (e.g., LLR) resulting from flipping u₀ to 0 (zero) is 16 (e.g., 25-9=16) . Table 2, below, illustrates additional bit combinations and associated LLRs that may be achieved when flipping u₀ and associated LLR and power savings.
Table 2
After a set of LLRs are generated based on the set of bits, the set of LLRs may then be decoded based on a particular shaping code rate to obtain a sequence of shaping bits. Thereafter, a shaping encoder may be used mask the set of bits based on the sequence of shaping bits to generate a sequence of shaped data bits. Thereafter, the transmitter may encode the sequence of shaping bits and sequence of shaped data bits (as well as, in some cases, a remaining set of non-shaped data bits) to generate a set of encoded bits. After the encoding, the set of encoded bits are mapped to, for example, a sequence of shaped symbols (e.g., QAM symbol) and transmitted in a signal over a wireless channel to a receiver.
At the receiver, the signal is received by a bitwise LLR demapper component which is configured to demap the sequence of symbols of the signal. In some cases, demapping the sequence of symbols may be based on symbol probabilities associated with the QAM symbols. Thereafter, the demapped sequence of symbols may then be jointly decoded by an FEC decoder to obtain the sequence of shaping bits and sequence of shaped data bits. Thereafter, the receiver may then re-encode the decoded shaping bits and perform a bit-masking operation on the shaped data bits using the re-encoded shaping bits to obtain the original set of bits. Additional details of this process are described with respect to FIG. 6, below.
While the techniques described above for constellation shaping involving bit-masking MSBs may help to reduce transmission power associated with transmitting information, these techniques may not be aligned with the current channel encoding techniques defined by certain wireless communication standards. For example, in many cases, the generation of the set of LLRs based on the set of bits may be assumed to be ideal and, thus, may need to be adapted to non-ideal scenarios associated with current channel encoding techniques, as described below with respect to Table 3.
Additionally, when decoding information, a receiver may need to know a transport block size associated with the set of bits that are transmitted. In traditional encoding techniques, the transport block size may be equal to a size of the set of bits (and any cyclic redundancy bits generated based on the set of bits) that are input into a forward error correction (FEC) encoder. However, when constellation shaping is used, the set of bits are encoded together with the sequence of shaping bits. As such, the traditional techniques for determining the transport block size associated with the set of bits may not be accurate when constellation shaping is used because the set of bits and the sequence of shaping bits are encoded together.
In other words, when constellation shaping is used, the transport block size associated with the set of bits is no longer simply equal to the number of bits input into the FEC encoder since these bits input into the FEC encoder include data bits as well as shaping bits. Accordingly, using existing techniques for determining the transport block size may lead to an inaccurate transport block size being determined, which may lead to failures in the decoding process. Failures in the decoding process may, in turn, lead to one or more retransmissions of the improperly decoded information, unnecessarily consuming time and frequency resources within a wireless network and power resources at a transmitter and receiver.
Accordingly, aspects of the present disclosure provide techniques for block-code-based constellation shaping that help to reduce or eliminate the issues described above. For example, the techniques presented herein may allow for constellation shaping to be adapted for use with current channel encoding techniques associated with certain wireless communication standards. For example, in some cases, to better align constellation shaping with current channel encoding techniques, the generation of LLRs (e.g., that be used to generate the sequence of shaping bits used for constellation shaping) may take into account certain transmission parameters used for transmitting a set of bits, such as a number of physical resource blocks (PRBs) configured for transmitting the set of bits and a modulation and coding scheme (MCS) configured for transmitting the set of bits.
Additionally, the techniques presented herein may help a receiver to properly determine a transport block size associated with the set of bits when constellation shaping is used. For example, in some embodiments, these techniques may allow the receiver take into account the number of shaping bits encoded with set of bits when determining the transport block size associated with the set of bits. By taking into account the shaping bits when determining the transport block size, the receiver can improve the chances that the set of bits are correctly decoded, thereby avoiding or reducing the unnecessary retransmission of the bits and associated wasted time, frequency, and power resources.
Example Operations for Block-Code-Based Constellation Shaping
FIG. 6 illustrates a communication system 600, including a transmitter 602 and a receiver 604, employing block-code-based constellation shaping. In some cases, the transmitter 602 may be an example of a network entity, such as the BS 102 described with respect to FIGS. 1 and 3 or a disaggregated BS as described with respect to FIG. 2. In some cases, the receiver 604 may be an example of a user equipment, such as the UE 104 described with respect to FIGS. 1 and 3. In other cases, the transmitter 602 may be an example of the UE 104 while the receiver 604 may be an example of the BS 102 or a disaggregated BS.
As shown, the transmitter 602 may generates a first set of bits 606 for transmission. The first set of bits 606 may include a number of bits equal to A bits (e.g., bits a₀, …, a_A-1) . Additionally, in some cases, the first set of bits 606 may include control information and/or data information. As shown at 607, the first set of bits 606 may then be input into a cyclic redundancy check (CRC) encoder, which is configured to generate a plurality of CRC bits (e.g., L bits) and attach these bits to the first set of bits 606 to obtain a second set of bits 610. After the plurality of CRC bits are attached, the first set of bits 606 includes a number of bits equal to B bits (e.g., bits b₀, …, b_B-1) , where B = A + L.
Thereafter, the second set of bits 610 may be input into an LLR generator 612 of the transmitter 602. The LLR generator 612 is configured to generate a set of LLRs 614 (e.g., r₀, …, r_H-1) corresponding to the second set of bits 610 (and first set of bits 606) . In some cases, the LLR generator 612 may also be configured to segment the set of LLRs 614 into a plurality of shaping blocks based, at least in part, on a shaping block length for the plurality of shaping blocks.
As shown, the set of LLRs may have a size H, which may be equal to two times the number of resource elements (REs) allocated for transmitting the second set of bits 610. In some cases, H may be represented aswhere E is a number of bits in a set of encoded bits configured to be output by an FEC encoder 628 of the transmitter 602 and Q_m is a modulation order for transmitting the second set of bits 610. In some cases, E and Q_m may depend on a number of physical resource blocks (N_PRB) configured for transmitting the second set of bits 610 and a modulation and coding scheme (MCS) configured for transmitting the second set of bits 610. Accordingly, as a result, H may also depend on N_PRB and the MCS configured for transmitting the second set of bits 610.
In some cases, Q_m may be specified by an MCS index value (I_MCS) , which indicates the modulation order Q_m within an MCS look up table. Further, E is related to the actual number of REs allocated to a wireless channel for transmitting the second set of bits 610, such as a physical uplink shared channel (PUSCH) , a physical downlink shared channel (PDSCH) , etc.. For example, assuming the second set of bits 610 will be transmitted on a PDSCH, if 10 physical resource blocks (PRBs) are allocated for transmission of the PDSCH, the actual number of REs is the nominal number REs (10*12 REs *18 symbols = 196 REs) in 10 PRBs minus the number of REs which cannot be used for transmission of PDSCH, such as the REs used for reference signals, synchronization signal block (SSBs) , and the like.
Accordingly, since both the transmitter 602 and receiver 604 know the REs that are not available for transmitting the PDSCH, the transmitter 602 and receiver 604 may determine the actual number of REs for transmitting the second set of bits 610 when the number of PRBs allocated is known (N_PRB) and may perform rate-matching by skipping these unavailable REs. Accordingly, E may be determined according to Q_m *the actual number of REs allocated. Further, because a constellation map associated with the transmission of the second set of bits 610 may need to be shaped in both the in-phase (I) and quadrature (Q) branches of the constellation map, the number of REs for transmitting the second set of bits 610 may be equal torather than
In some cases, generating the set of LLRs 614 may include arranging the second set of bits 610 into a matrix having dimensions Q_m/2 and H, as shown in Table 3, below. As shown in Table 1, Q_m may be assumed to be 6 in this example. In some cases, columns 0, 2, 4, and 6 may correspond to the I branch of the constellation map and columns 1, 3, 5, and 7 may correspond to the Q branch of the constellation map. In some cases, two columns of Table 3 may correspond to one QAM symbol.
Table 3
In some cases, the LLR generator 612 of the transmitter 602 may be configured to generate a respective LLR for each different column in the matrix. For example, with reference to the matrix shown in Table 3, the transmitter 602 may generate a first LLR for the bits of the second set of bits 610 arranged in column 0, a second LLR for bits of the second set of bits 610 arranged in column 1, and so on.
In some cases, the LLR generator 612 of the transmitter 602 may generate the respective LLR for each different column of the matrix by determining a first power value for a first subset of bits of the second set of bits arranged in that different column of the matrix. For example, as shown in Table 3, the LLR generator 612 may determine a power value for bits b₀, …, b_B-6 arranged in column 0. For example, assuming that the first subset bits arranged in column 0 of Table 3 are 101, the LLR generator 612 may determine the power value for the bits arranged in column 0 of Table 3 (e.g., 101) by squaring the symbol that these bits represent. For example, with reference to the last column in Table 1, the bits 101 in column 0 of Table 3 represent the symbol 7 in Table 1. As such, the LLR generator 612 may determine the first power value for column 0 of Table 3 as 7*7 (e.g., 7²) or 49.
Thereafter, the LLR generator 612 may be configured to flip a value of a first bit of the subset of bits arranged in that different column of the matrix to obtain a second subset of bits arranged in that different column of the matrix. For example, continuing with the example above, the LLR generator may flip the first bit of column 0 in Table 3 from 1 (e.g., 1) to 0 (e.g., zero) . Accordingly, the second subset of bits arranged in column 0 of Table 3 may be 001.
Thereafter, the LLR generator 612 may determine a second power value for the second subset of bits arranged in that different column of the matrix. For example, continuing with the example above, the bits 001 represent the symbol 1 in the fifth column of Table 1. As such, the LLR generator 612 may determine the second power value as 1*1 (e.g., 1²) or 1.
Thereafter, the LLR generator 612 may generate the respective LLR for that different column of the matrix based on the first power value and the second power value. For example, the LLR generator 612 may generate the respective LLR for column 0 (e.g., r₀) of Table 3 by determining the difference between the second power value and the first power value according to r₀= (1*1) - (7*7) = 1-49=-48. The LLR generator 612 may then repeat this process for the remaining columns of the matrix in Table 3.
The example shown in Table 3 illustrates a case in which LLR generation is ideal and the second set of bits 610 (e.g., bits b₀, …, b_B-1) match all of the entries of the matrix having the dimensions Q_m/2 and H. However, there may be cases in which LLR generation is not ideal and the second set of bits 610 does not match the entries of the matrix. This scenario may occur, for example, when the second set of bits 610 includes less bits than a configured number of bits in a set of encoded bits configured to be output by the FEC encoder 628 of the transmitter 602.
In such cases, the transmitter 602 may be configured to add one or more padding bits to the second set of bits 610 prior to arranging the second set of bits 610 into the matrix, as shown as an “x” in the Table 4, below.
Table 4
Accordingly, when generating the respective LLR for each different column of the matrix, the different column of the matrix for which the respective LLR is generated may include at least one padding bit, which may have a value of either 0 (zero) or 1 (one) . In some cases, because the at least one padding bit may have a value of 0 or 1, the LLR generator 612 may be configured to generate the respective LLR for the different column of the matrix based on an average between power values determined using these different values for the at least one padding bit.
For example, as noted above, the LLR generator 612 is configured to determine a first power value for the first subset of bits of the second set of bits 610, flip a value of the first bit in the first subset of bits to obtain a second subset of bits of the first set of bits 610, and determine a second power value for the second subset of bits. Accordingly, when the different column of the matrix for which the respective LLR is being generated includes at least one passing bit, determining the first power value for the first subset of bits may be based on a first value of the at least one padding bit. Thereafter, once the value of the first bit of the first subset of bits has been flipped, the LLR generator 612 may determine the second power value for the second subset of bits based on the first value of the at least one padding bit. Thereafter, the LLR generator 612 may determine a third power value for the first subset of bits and a fourth power value for the second subset of bits based on a second value of the at least one bit.
More specifically, for example, assume that the first subset of bits in column 0 of Table 4 (e.g., bits b₀, …, x) includes bits 101 (e.g., the first value of the at least one padding bit is 1) . Accordingly, with reference to Table 1, the LLR generator 612 may determine the first power value for the first subset of bits to be 49 (e.g., bits 101 correspond to symbol 7 in Table 1 and 7² is 49) . Thereafter, the LLR generator 612 flips the first bit of the first subset of bits to a 0 (zero) to obtain the second subset of bits 001. The LLR generator 612 may then determine the second power value for the second subset of bits to be 1 (e.g., bits 001 correspond to symbol 1 in Table 1 and 1² is 1) .
Thereafter, the LLR generator 612 may assume a second value for the at least one padding bit (e.g., x=0) , such that the first subset of bits includes the bits 100. Accordingly, the LLR generator 612 may then determine a third power value for the first subset of bits based on the second value of the at least one padding bit. For example, with reference to Table 1, assuming that the first subset of bits includes bits 100, the LLR generator 612 may determine the third power value to be 49 (e.g., bits 100 correspond to symbol -7 in Table 1 and -7² is 49) . The LLR generator 612 may again flip the value of the first bit of the first subset of bits to a 0 (zero) to obtain the second subset of bits 000. The LLR generator 612 may then determine a fourth power value for the second subset of bits to be 1 (e.g., bits 000 correspond to symbol -1 in Table 1 and -1² is 1) .
Accordingly, the LLR generator 612 of the transmitter 602 may then generate the respective LLR for column 0 of Table 4 based on the first power value, the second power value, the third power value, and the fourth power value. For example, the LLR generator 612 may determine a first difference between the first power value and the second power value (e.g., 1*1-7*7= -48) . The LLR generator 612 may then determine a second difference between the third power value and the fourth power value (e.g., 1*1-7*7= -48) . The LLR generator 612 may then generate the respective LLR for column 0 of Table 4 based on an average of the first difference and the second difference. For example, the LLR generator 612 may generate the respective LLR for column 0 of Table 4 (e.g., r₀) according toThe LLR generator 612 may then repeat this process for the remaining columns of the matrix in Table 4.
Once the set of LLRs (e.g., r₀, …, r_H-1) has been generated, the LLR generator 612 may segment the set of LLRs 614 into a plurality of shaping blocks, for example, based on a shaping block length for the plurality of shaping blocks. Thereafter, the plurality shaping blocks and set of LLRs may be input into the channel decoder 616, which is configured to decode the set of LLRs, according to a block code (e.g., a low-density parity-check (LDPC) code, a Polar code, Hamming, Bose–Chaudhuri–Hocquenghem (BCH) codes, Reed-Solomon codes, etc. ) to obtain a sequence of shaping bits 618 (e.g., e₀, …, e_S-1) . In some cases, the channel decoder 616 may be configured to decode the set of LLRs according to a shaping code rate (R_s) , which may be defined as R_s=K_s/N_s, where K_s is a size of the sequence of shaping bits 618 (e.g., s) and N_s is the shaping block length associated with the plurality of shaping blocks into which the set of LLRs 614 have been segmented. In some cases, the shaping code rate (R_s) may depend on a subband over which the second set of bits 610 are to be transmitted and may be different for different subbands. For example, in some cases, the shaping code rate (R_s) may be based on a signal to noise ratio (SNR) associated with the subband over which the second set of bits 610 are to be transmitted.
After being generated, the sequence of shaping bits 618 may be input into a channel encoder 620. The channel encoder 620 may be configured to (re) encode, according to the shaping code rate (R_s) , the sequence of shaping bits 618 using the block code to obtain a shaping codeword (v) 622 having a size H and represented by the bit sequence f₀, …, f_H-1. For example, to obtain the shaping codeword 622, the channel encoder 620 may multiply the sequence of shaping bits 618 (e.g., e₀, …, e_S-1) by a generator matrix (G) of the block code of size S according to v= [e₀, …, e_S-1] ×G_S.
Thereafter, a bit-masking component 624 of the transmitter 602 may be configured to perform, using the shaping codeword, a shaping operation on a subset of the second set of bits 610 to generate a sequence of shaped bits. For example, the shaping operation may be performed on the same number of bits in the second set of bits 610 as are included within the shaping codeword. In other words, a first number of bits in the shaping codeword (e.g., f₀, …, f_H-1) may be equal to a second number of bits in the subset of bits (e.g., b₀, …, b_H-1) of the second set of bits 610. Accordingly, the bit-masking component 624 may perform the shaping operation by bit-masking the second number of bits in the subset of bits (e.g., b₀, …, b_H-1) using the first number of bits in the shaping codeword (e.g., f₀, …, f_H-1) . For example, For example, bit-masking component 624 may perform the shaping operation according toto generate the sequence of shaped bits, wheredenotes element-wise modulo-2 addition (e.g., exclusive OR (XOR) ) . As noted above, a goal of shaping is to maximize power savings. Accordingly, to maximize power savings, bit-masking the second number of bits in the subset of bits (e.g., b₀, …, b_H-1) comprises shifting at least some of the bits in the second number of bits to zero.
Once the shaping operation has been performed, the transmitter 602 may be configured to concatenate the sequence of shaped bits (e.g., b₀, …, b_H-1) , a remaining subset of non-shaped bits (e.g., b_H, …, b_B-1) of the second set of bits 610, and the sequence of shaping bits (e.g., e₀, …, e_S-1) to obtain a set of information bits 626 (e.g., c₀, …, c_K- ₁) . Accordingly, the set of information bits may be represented as
After performing the shaping operation, the set of information bits 626 (e.g., c₀, …, c_K-1) (e.g., including sequence of shaped bits, the remaining subset of non-shaped bits, and the sequence of shaping bits) may be input into a systematic FEC encoder 628. The FEC encoder 628 may then encode the set of information bits 626 to obtain a set of encoded bits. In some cases, an FEC code rate used to encode the set of information bits 626 may be specified by an MCS for transmitting the second set of bits 610, which may be indicated using an MCS table.
After encoding, the set of encoded bits may be sent to a bit-to-symbol mapper 630. The bit-to-symbol mapper 630 is configured to map the encoded bits to symbols (e.g., QAM symbols) to generate a sequence of shaped symbols from or based on the sequence of shaping bits 618. Thereafter, the sequence of shaped symbols may be transmitted to the receiver 604 over a wireless channel 632.
As shown in FIG. 6, a symbol-to-bit demapper 634 of the receiver 604 receives the sequence of shaped symbols, which correspond to the second set of bits 610. The symbol-to-bit demapper 634 is configured to demap the sequence of shaped symbols to generate a sequence of bit-level LLRs corresponding to the set of encoded bits output from the FEC encoder 628 of the transmitter 602, as described above. In some cases, demapping the sequence of symbols may be based on symbol probabilities associated with the sequence of shaped symbols. For example, in some cases, the receiver 604 may receive the sequence of shaped symbols and may use the symbol probabilities to perform maximum a posertiori probability (MAP) demodulation to convert the received sequence of symbols to the bit-level LLRs of the set of encoded bits.
Thereafter, the bit-level LLRs may be input into an FEC decoder 636. The FEC decoder 636 may be configured to decode the sequence of bit-level LLRs using an FEC code rate to obtain a set of decoded bits 638. In some cases, the FEC code rate may be the same FEC code rate that was used by the FEC encoder 628 of the transmitter 602 to encode the set of information bits 626.
In some cases, the set of decoded bits 638 corresponds to the set of information bits 626 (e.g., c₀, …, c_K-1) and includes a sequence of shaping bits 640 (e.g., e₀, …, e_S- ₁) , a sequence of shaped bits 642 of a set of bits, and a remaining subset of non-shaped bits 644 of the set of bits. The sequence of shaping bits 640 corresponds to the sequence of shaping bits 618 generated by the transmitter 602. Similarly, the sequence of shaped bits 642 correspond to the sequence of shaped bits (e.g., b₀, …, b_H-1) generated by the transmitter 602 and the subset of non-shaped bits 644 corresponds to the subset of non-shaped bits (e.g., b_H, …, b_B-1) generated by the transmitter 602.
In some cases, the FEC decoder 636 may decode the bit-level LLRs based on a transport block size associated with the second set of bits 610 (e.g., which are included within or represented by the bit-level LLRs determined by the receiver 604) . Additionally, in some cases, the FEC decoder 636 may also use the transport block size associated with the second set of bits 610 in order to segment the sequence of shaping bits 640 from the sequence of shaped bits 642 and the remaining subset of non-shaped bits 644.
As noted above, traditional techniques for determining the transport block size may not be accurate when constellation shaping is used and may result in the transport block size being incorrectly determined due to the addition of the sequence of shaping bits 640 included within the bit-level LLRs. Accordingly, in some cases, to accurately determine the transport block size (B) associated with the second set of bits 610 generated by the transmitter 602, the receiver 604 may first determine a size of the set of information bits 626 (e.g., K) configured to be input into the FEC encoder 628 of the transmitter 602. The receiver 604 may determine the size of the set of information bits 626 based on the number of physical resource blocks (N_PRB) used to transmit the second set of bits 610 and an MCS configured to transmit the second set of bits 610.
In some cases, the receiver 604 may receive configuration information from the transmitter 602 indicating N_PRB used to transmit the second set of bits 610 and an MCS index value of the MCS configured to transmit the second set of bits 610. In some cases, the configuration information may be received in downlink control information (DCI) . In some cases, the MCS index value may correspond to an entry in an MCS lookup table that indicates: the modulation order (Q_m) and the FEC code rate associated with the second set of bits 610.
Thereafter, the receiver 604 may determine a number of resource elements (H) associated with a transport block used to transmit the transmit the second set of bits 610 based on the modulation order (Q_m) and a configured number of encoded bits (E) associated with FEC encoding (e.g., configured to be output by the FEC encoder 628 of the transmitter 602) . In some cases, the receiver may determine H according to:
Thereafter, the receiver 604 may determine a number of shaping bits (S) in the sequence of shaping bits 640 (e.g., e₀, …, e_S-1) based on the number of resource elements (H) and the shaping code rate (R_s) (e.g., used by the transmitter 602 to generate the sequence of shaping bits 618) . For example, in some cases, the receiver 604 may determine S according to: whereis a floor operator. In some cases, receiver 604 may receive information from the transmitter 602 indicating the shaping code rate (R_s) . In some cases, the information indicating the shaping code rate (R_s) may be included within the configuration information received from the transmitter 602. For example, the information indicating the shaping code rate may be included in the MCS lookup table and may be provided by the MCS index value received in the configuration information from the transmitter 602. In other cases, the configuration information may explicitly indicate the shaping code rate.
After determining the number of shaping bits (S) , the receiver 604 may then determine the transport block size (B) (e.g., associated with the second set of bits 610) for decoding the sequence of bit-level LLRs based on the number of shaping bits (S) and the size of the set of information bits (K) . For example, the receiver 604 may determine the transport block size (B) according to: B=K-S.
As shown, the sequence of shaping bits 640 are input into a channel encoder 646. The channel encoder 646 may be configured to encode, according to the shaping code rate (R_s) (e.g., used by the transmitter 602) , the sequence of shaping bits 640 using a block code to obtain a deshaping codeword. This encoding process may be similar to the encoding process performed by the channel encoder 620 of the transmitter 602. As such, the deshaping codeword may, in some cases, correspond to the shaping codeword (e.g., f₀, …, f_H-1) generated by the transmitter 602.
Thereafter, the deshaping codeword 649 as well as the sequence of shaped bits 642 and the remaining subset of non-shaped bits 644 may be input into a bit-masking component 647 of the receiver 604. The bit-masking component 647 is configured to perform a deshaping operation on the sequence of shaped bits 642. For example, in some cases, the bit-masking component 647 may apply the deshaping codeword 649 to the sequence of shaped bits 642 to deshape the sequence of shaped bits 642 and to obtain a sequence of deshaped bits. Thereafter, the receiver 604 may concatenate the sequence of deshaped bits with the remaining subset of non-shaped bits 644 to obtain the set of bits 648 corresponding to the second set of bits 610 generated by the transmitter 602. Accordingly, the set of bits 648 may include the first set of bits 606 as well as the plurality of CRC bits described above.
In some cases, the receiver 604 may then use the plurality of CRC bits included within the set of bits 648 to verify that the first set of bits 606 were correctly received and decoded. For example, the receiver 604 may use a CRC encoder to encode the first set of bits 606 included within the set of bits 648 to generate a second plurality of CRC bits. If the second plurality of CRC bits generated by the receiver 604 match the plurality of CRC bits received in the set of bits 648, the receiver 604 may know that the first set of bits 606 received in the set of bits 648 were correctly received and decoded.
Example Operations of a Transmitting Device
FIG. 7 shows an example of a method 700 of wireless communication by a transmitting device. In some examples, the transmitting device is a user equipment, such as a UE 104 of FIGS. 1 and 3. In some examples, the transmitting device is a network entity, such as a BS 102 of FIGS. 1 and 3, or a disaggregated base station as discussed with respect to FIG. 2.
Method 700 begins at step 705 with generating a first set of bits for transmission. In some cases, the operations of this step refer to, or may be performed by, circuitry for generating and/or code for generating as described with reference to FIG. 9.
Method 700 then proceeds to step 710 with generating and attaching a plurality of CRC bits to the first set of bits to obtain a second set of bits for transmission. In some cases, the operations of this step refer to, or may be performed by, circuitry for generating and/or code for generating as described with reference to FIG. 9.
Method 700 then proceeds to step 715 with generating a set of LLRs corresponding to the second set of bits, wherein a size of the set of LLRs depends on a number of PRBs configured for transmitting the second set of bits and a MCS configured for transmitting the second set of bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for generating and/or code for generating as described with reference to FIG. 9.
Method 700 then proceeds to step 720 with decoding, according to a shaping code rate, the set of LLRs using a block code to obtain a sequence of shaping bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for decoding and/or code for decoding as described with reference to FIG. 9.
Method 700 then proceeds to step 725 with generating a sequence of shaped symbols based, at least in part, on the sequence of shaping bits and the second set of bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for generating and/or code for generating as described with reference to FIG. 9.
Method 700 then proceeds to step 730 with transmitting the sequence of shaped symbols to a receiving device. In some cases, the operations of this step refer to, or may be performed by, circuitry for transmitting and/or code for transmitting as described with reference to FIG. 9.
In some aspects, the method 700 further includes encoding, according to the shaping code rate, the sequence of shaping bits using the block code to obtain a shaping codeword. In some cases, the operations of this step refer to, or may be performed by, circuitry for encoding and/or code for encoding as described with reference to FIG. 9.
In some aspects, the method 700 further includes performing, using the shaping codeword, a shaping operation on a subset of bits of the second set of bits to generate a sequence of shaped bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for performing and/or code for performing as described with reference to FIG. 9.
In some aspects, the method 700 further includes concatenating the sequence of shaped bits, a remaining subset of non-shaped bits of the second set of bits, and the sequence of shaping bits to obtain a set of information bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for concatenating and/or code for concatenating as described with reference to FIG. 9.
In some aspects, the method 700 further includes encoding, using a FEC code rate, the set of information bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for encoding and/or code for encoding as described with reference to FIG. 9.
In some aspects, the method 700 further includes generating the sequence of shaped symbols based on the set of encoded bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for generating and/or code for generating as described with reference to FIG. 9.
In some aspects, a first number of bits in the shaping codeword is equal to a second number of bits in the subset of bits of the second set of bits; and performing the shaping operation comprises bit-masking the second number of bits in the subset of bits using the first number of bits in the shaping codeword.
In some aspects, bit-masking the second number of bits in the subset of bits comprises shifting at least some of the bits in the second number of bits to zero.
In some aspects, generating the set of LLRs comprises arranging the second set of bits into a matrix having dimensions Qm/2 and H, where Qm is a modulation order for transmitting the second set of bits and H is two times a number of bits of the set of encoded bits (E) divided by the modulation order (Qm) .
In some aspects, generating the set of LLRs further comprises generating a respective LLR for each different column in the matrix.
In some aspects, generating the respective LLR for each different column of the matrix comprises: determining a first power value for a second subset of bits of second set of bits arranged in that different column of the matrix; flipping a value of a first bit of the second subset of bits arranged in that different column of the matrix to obtain a third subset of bits arranged in that different column of the matrix; and determining a second power value for the third subset of bits arranged in that different column of the matrix.
In some aspects, generating the respective LLR for that different column of the matrix based on the first power value and the second power value.
In some aspects, the method 700 further includes adding one or more padding bits to the second set of bits prior to arranging the second set of bits into the matrix when the second set of bits includes less bits than a configured number of bits for the set of encoded bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for adding and/or code for adding as described with reference to FIG. 9.
In some aspects, the different column of the matrix for which the respective LLR is generated includes at least one padding bit; determining the first power value for the second subset of bits is based on a first value of the at least one padding bit; and determining the second power value for the third subset of bits is based on the first value of the at least one padding bit.
In some aspects, the method 700 further includes determining a third power value for the second subset of bits based on a second value of the at least one padding bit. In some cases, the operations of this step refer to, or may be performed by, circuitry for determining and/or code for determining as described with reference to FIG. 9.
In some aspects, the method 700 further includes determining a fourth power value for the third subset of bits based on the second value of the at least one padding bit. In some cases, the operations of this step refer to, or may be performed by, circuitry for determining and/or code for determining as described with reference to FIG. 9.
In some aspects, the method 700 further includes determining a first difference between the first power value and the second power value. In some cases, the operations of this step refer to, or may be performed by, circuitry for determining and/or code for determining as described with reference to FIG. 9.
In some aspects, the method 700 further includes determining a second difference between the third power value and the fourth power value. In some cases, the operations of this step refer to, or may be performed by, circuitry for determining and/or code for determining as described with reference to FIG. 9.
In some aspects, generating the respective LLR for that different column of the matrix is based on an average of the first difference and the second difference.
In some aspects, the method 700 further includes transmitting, to the receiving device, configuration information indicating: the number of PBRs configured for transmitting the second set of bits; and an MCS index value of the MCS configured for transmitting the second set of bits, the MCS index value corresponding to an entry in an MCS lookup table that indicates: a modulation order; and the FEC code rate. In some cases, the operations of this step refer to, or may be performed by, circuitry for transmitting and/or code for transmitting as described with reference to FIG. 9.
In some aspects, the method 700 further includes transmitting, to the receiving device, information indicating the shaping code rate. In some cases, the operations of this step refer to, or may be performed by, circuitry for transmitting and/or code for transmitting as described with reference to FIG. 9.
In some aspects, the information indicating the shaping code rate is included in the MCS lookup table and is provided by the MCS index value.
In one aspect, method 700, or any aspect related to it, may be performed by an apparatus, such as communications device 900 of FIG. 9, which includes various components operable, configured, or adapted to perform the method 700. Communications device 900 is described below in further detail.
Note that FIG. 7 is just one example of a method, and other methods including fewer, additional, or alternative steps are possible consistent with this disclosure.
Example Operations of a Receiving Device
FIG. 8 shows an example of a method 800 of wireless communication by a receiving device. In some examples, the receiving device is a user equipment, such as a UE 104 of FIGS. 1 and 3. In some examples, the receiving device is a network entity, such as a BS 102 of FIGS. 1 and 3, or a disaggregated base station as discussed with respect to FIG. 2.
Method 800 begins at step 805 with receiving, from a transmitting device, a sequence of shaped symbols corresponding to a set of bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for receiving and/or code for receiving as described with reference to FIG. 10.
Method 800 then proceeds to step 810 with converting the sequence of shaped symbols to a sequence of bit-level LLRs. In some cases, the operations of this step refer to, or may be performed by, circuitry for converting and/or code for converting as described with reference to FIG. 10.
Method 800 then proceeds to step 815 with decoding, based on a transport block size associated with the set of bits, the sequence of bit-level LLRs, using a FEC code rate, to obtain a set of decoded bits, the set of decoded bits including a sequence of shaping bits, a sequence of shaped bits of the set of bits, and a remaining subset of non-shaped bits of the set of bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for decoding and/or code for decoding as described with reference to FIG. 10.
Method 800 then proceeds to step 820 with performing, using a shaping code rate, a deshaping operation on the sequence of shaped bits based on the sequence of shaping bits to obtain a sequence of deshaped bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for performing and/or code for performing as described with reference to FIG. 10.
Method 800 then proceeds to step 825 with concatenating the sequence of deshaped bits with the remaining subset of non-shaped bits to obtain the set of bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for concatenating and/or code for concatenating as described with reference to FIG. 10.
In some aspects, the method 800 further includes encoding, according to the shaping code rate, the sequence of shaping bits using a block code to obtain a deshaping codeword. In some cases, the operations of this step refer to, or may be performed by, circuitry for encoding and/or code for encoding as described with reference to FIG. 10.
In some aspects, performing the deshaping operation on the sequence of shaped bits comprises applying the deshaping codeword to the sequence of shaped bits to deshape the sequence of shaped bits and to obtain the sequence of deshaped bits.
In some aspects, the method 800 further includes determining a size of a set of information bits (K) associated with FEC encoding of the set of bits based on a number of PRBs configured to transmit the set of bits and a MCS configured to transmit the set of bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for determining and/or code for determining as described with reference to FIG. 10.
In some aspects, the method 800 further includes determining a number of resource elements (H) associated with a transport block used to transmit the set of bits based on a modulation order (Qm) and a configured number of encoded bits (E) corresponding to the set of information bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for determining and/or code for determining as described with reference to FIG. 10.
In some aspects, the method 800 further includes determining a number of shaping bits (S) in the sequence of shaping bits based on the number of resource elements (H) and the shaping code rate (Rs) . In some cases, the operations of this step refer to, or may be performed by, circuitry for determining and/or code for determining as described with reference to FIG. 10.
In some aspects, the method 800 further includes determining the transport block size for decoding the sequence of bit-level LLRs based on the number of shaping bits (S) and the size of the set of information bits (K) associated with the FEC encoding of the set of bits. In some cases, the operations of this step refer to, or may be performed by, circuitry for determining and/or code for determining as described with reference to FIG. 10.
In some aspects, decoding the sequence of bit-level LLRs comprises segmenting, based on the transport block size associated with the set of bits, the sequence of shaping bits from the sequence of shaped bits and the remaining subset of non-shaped bits.
In some aspects, the method 800 further includes receiving, from the transmitting device, configuration information indicating: the number of PBRs configured for transmitting the set of bits; and an MCS index value of the MCS configured for transmitting the set of bits, the MCS index value corresponding to an entry in an MCS lookup table that indicates: a modulation order; and the FEC code rate. In some cases, the operations of this step refer to, or may be performed by, circuitry for receiving and/or code for receiving as described with reference to FIG. 10.
In some aspects, the method 800 further includes receiving, from the transmitting device, information indicating the shaping code rate. In some cases, the operations of this step refer to, or may be performed by, circuitry for receiving and/or code for receiving as described with reference to FIG. 10.
In some aspects, the information indicating the shaping code rate is included in the MCS lookup table and is provided by the MCS index value.
In one aspect, method 800, or any aspect related to it, may be performed by an apparatus, such as communications device 1000 of FIG. 10, which includes various components operable, configured, or adapted to perform the method 800. Communications device 1000 is described below in further detail.
Note that FIG. 8 is just one example of a method, and other methods including fewer, additional, or alternative steps are possible consistent with this disclosure.
Example Communications Devices
FIG. 9 depicts aspects of an example communications device 900. In some aspects, communications device 900 is a user equipment, such as UE 104 described above with respect to FIGS. 1 and 3. In some aspects, communications device 900 is a network entity, such as BS 102 of FIGS. 1 and 3, or a disaggregated base station as discussed with respect to FIG. 2.
The communications device 900 includes a processing system 902 coupled to the transceiver 942 (e.g., a transmitter and/or a receiver) . In some aspects (e.g., when communications device 900 is a network entity) , processing system 902 may be coupled to a network interface 946 that is configured to obtain and send signals for the communications device 900 via communication link (s) , such as a backhaul link, midhaul link, and/or fronthaul link as described herein, such as with respect to FIG. 2. The transceiver 942 is configured to transmit and receive signals for the communications device 900 via the antenna 944, such as the various signals as described herein. The processing system 902 may be configured to perform processing functions for the communications device 900, including processing signals received and/or to be transmitted by the communications device 900.
The processing system 902 includes one or more processors 904. In various aspects, the one or more processors 904 may be representative of one or more of receive processor 358, transmit processor 364, TX MIMO processor 366, and/or controller/processor 380, as described with respect to FIG. 3. In various aspects, one or more processors 904 may be representative of one or more of receive processor 338, transmit processor 320, TX MIMO processor 330, and/or controller/processor 340, as described with respect to FIG. 3. The one or more processors 904 are coupled to a computer-readable medium/memory 922 via a bus 940. In certain aspects, the computer-readable medium/memory 922 is configured to store instructions (e.g., computer-executable code) that when executed by the one or more processors 904, cause the one or more processors 904 to perform the method 700 described with respect to FIG. 7, or any aspect related to it; and the method 800 described with respect to FIG. 8, or any aspect related to it. Note that reference to a processor performing a function of communications device 900 may include one or more processors 904 performing that function of communications device 900.
In the depicted example, computer-readable medium/memory 922 stores code (e.g., executable instructions) , such as code for generating 924, code for decoding 926, code for transmitting 928, code for encoding 930, code for performing 932, code for concatenating 934, code for adding 936, and code for determining 938. Processing of the code for generating 924, code for decoding 926, code for transmitting 928, code for encoding 930, code for performing 932, code for concatenating 934, code for adding 936, and code for determining 938 may cause the communications device 900 to perform the method 700 described with respect to FIG. 7, or any aspect related to it; and the method 800 described with respect to FIG. 8, or any aspect related to it.
The one or more processors 904 include circuitry configured to implement (e.g., execute) the code stored in the computer-readable medium/memory 922, including circuitry for generating 906, circuitry for decoding 908, circuitry for transmitting 910, circuitry for encoding 912, circuitry for performing 914, circuitry for concatenating 916, circuitry for adding 918, and circuitry for determining 920. Processing with circuitry for generating 906, circuitry for decoding 908, circuitry for transmitting 910, circuitry for encoding 912, circuitry for performing 914, circuitry for concatenating 916, circuitry for adding 918, and circuitry for determining 920 may cause the communications device 900 to perform the method 700 described with respect to FIG. 7, or any aspect related to it; and the method 800 described with respect to FIG. 8, or any aspect related to it.
Various components of the communications device 900 may provide means for performing the method 700 described with respect to FIG. 7, or any aspect related to it;and the method 800 described with respect to FIG. 8, or any aspect related to it. For example, means for transmitting, sending or outputting for transmission may include transceivers 354 and/or antenna (s) 352 of the UE 104 illustrated in FIG. 3, transceivers 332 and/or antenna (s) 334 of the BS 102 illustrated in FIG. 3, and/or the transceiver 942 and the antenna 944 of the communications device 900 in FIG. 9. Means for receiving or obtaining may include transceivers 354 and/or antenna (s) 352 of the UE 104 illustrated in FIG. 3, transceivers 332 and/or antenna (s) 334 of the BS 102 illustrated in FIG. 3, and/or the transceiver 942 and the antenna 944 of the communications device 900 in FIG. 9.
FIG. 10 depicts aspects of an example communications device 1000. In some aspects, communications device 1000 is a user equipment, such as UE 104 described above with respect to FIGS. 1 and 3. In some aspects, communications device 1000 is a network entity, such as BS 102 of FIGS. 1 and 3, or a disaggregated base station as discussed with respect to FIG. 2.
The communications device 1000 includes a processing system 1002 coupled to the transceiver 1038 (e.g., a transmitter and/or a receiver) . In some aspects (e.g., when communications device 1000 is a network entity) , processing system 1002 may be coupled to a network interface 1042 that is configured to obtain and send signals for the communications device 1000 via communication link (s) , such as a backhaul link, midhaul link, and/or fronthaul link as described herein, such as with respect to FIG. 2. The transceiver 1038 is configured to transmit and receive signals for the communications device 1000 via the antenna 1040, such as the various signals as described herein. The processing system 1002 may be configured to perform processing functions for the communications device 1000, including processing signals received and/or to be transmitted by the communications device 1000.
The processing system 1002 includes one or more processors 1004. In various aspects, the one or more processors 1004 may be representative of one or more of receive processor 358, transmit processor 364, TX MIMO processor 366, and/or controller/processor 380, as described with respect to FIG. 3. In various aspects, one or more processors 1004 may be representative of one or more of receive processor 338, transmit processor 320, TX MIMO processor 330, and/or controller/processor 340, as described with respect to FIG. 3. The one or more processors 1004 are coupled to a computer-readable medium/memory 1020 via a bus 1036. In certain aspects, the computer-readable medium/memory 1020 is configured to store instructions (e.g., computer-executable code) that when executed by the one or more processors 1004, cause the one or more processors 1004 to perform the method 700 described with respect to FIG. 7, or any aspect related to it; and the method 800 described with respect to FIG. 8, or any aspect related to it. Note that reference to a processor performing a function of communications device 1000 may include one or more processors 1004 performing that function of communications device 1000.
In the depicted example, computer-readable medium/memory 1020 stores code (e.g., executable instructions) , such as code for receiving 1022, code for converting 1024, code for decoding 1026, code for performing 1028, code for concatenating 1030, code for encoding 1032, and code for determining 1034. Processing of the code for receiving 1022, code for converting 1024, code for decoding 1026, code for performing 1028, code for concatenating 1030, code for encoding 1032, and code for determining 1034 may cause the communications device 1000 to perform the method 700 described with respect to FIG. 7, or any aspect related to it; and the method 800 described with respect to FIG. 8, or any aspect related to it.
The one or more processors 1004 include circuitry configured to implement (e.g., execute) the code stored in the computer-readable medium/memory 1020, including circuitry for receiving 1006, circuitry for converting 1008, circuitry for decoding 1010, circuitry for performing 1012, circuitry for concatenating 1014, circuitry for encoding 1016, and circuitry for determining 1018. Processing with circuitry for receiving 1006, circuitry for converting 1008, circuitry for decoding 1010, circuitry for performing 1012, circuitry for concatenating 1014, circuitry for encoding 1016, and circuitry for determining 1018 may cause the communications device 1000 to perform the method 700 described with respect to FIG. 7, or any aspect related to it; and the method 800 described with respect to FIG. 8, or any aspect related to it.
Various components of the communications device 1000 may provide means for performing the method 700 described with respect to FIG. 7, or any aspect related to it; and the method 800 described with respect to FIG. 8, or any aspect related to it. For example, means for transmitting, sending or outputting for transmission may include transceivers 354 and/or antenna (s) 352 of the UE 104 illustrated in FIG. 3, transceivers 332 and/or antenna (s) 334 of the BS 102 illustrated in FIG. 3, and/or the transceiver 1038 and the antenna 1040 of the communications device 1000 in FIG. 10. Means for receiving or obtaining may include transceivers 354 and/or antenna (s) 352 of the UE 104 illustrated in FIG. 3, transceivers 332 and/or antenna (s) 334 of the BS 102 illustrated in FIG. 3, and/or the transceiver 1038 and the antenna 1040 of the communications device 1000 in FIG. 10.
Example Clauses
Implementation examples are described in the following numbered clauses:
Clause 1: A method for wireless communication by a transmitting device, comprising: generating a first set of bits for transmission; generating and attaching a plurality of CRC bits to the first set of bits to obtain a second set of bits for transmission; generating a set of LLRs corresponding to the second set of bits, wherein a size of the set of LLRs depends on a number of PRBs configured for transmitting the second set of bits and a MCS configured for transmitting the second set of bits; decoding, according to a shaping code rate, the set of LLRs using a block code to obtain a sequence of shaping bits; generating a sequence of shaped symbols based, at least in part, on the sequence of shaping bits and the second set of bits; and transmitting the sequence of shaped symbols to a receiving device.
Clause 2: The method of Clause 1, further comprising: encoding, according to the shaping code rate, the sequence of shaping bits using the block code to obtain a shaping codeword; performing, using the shaping codeword, a shaping operation on a subset of bits of the second set of bits to generate a sequence of shaped bits; concatenating the sequence of shaped bits, a remaining subset of non-shaped bits of the second set of bits, and the sequence of shaping bits to obtain a set of information bits; encoding, using a FEC code rate, the set of information bits; and generating the sequence of shaped symbols based on the set of encoded bits.
Clause 3: The method of Clause 2, wherein: a first number of bits in the shaping codeword is equal to a second number of bits in the subset of bits of the second set of bits; and performing the shaping operation comprises bit-masking the second number of bits in the subset of bits using the first number of bits in the shaping codeword.
Clause 4: The method of Clause 3, wherein bit-masking the second number of bits in the subset of bits comprises shifting at least some of the bits in the second number of bits to zero.
Clause 5: The method of Clause 2, wherein generating the set of LLRs comprises arranging the second set of bits into a matrix having dimensions Qm/2 and H, where Qm is a modulation order for transmitting the second set of bits and H is two times a number of bits of the set of encoded bits (E) divided by the modulation order (Qm) .
Clause 6: The method of Clause 5, wherein generating the set of LLRs further comprises generating a respective LLR for each different column in the matrix.
Clause 7: The method of Clause 6, wherein generating the respective LLR for each different column of the matrix comprises: determining a first power value for a second subset of bits of second set of bits arranged in that different column of the matrix; flipping a value of a first bit of the second subset of bits arranged in that different column of the matrix to obtain a third subset of bits arranged in that different column of the matrix; and determining a second power value for the third subset of bits arranged in that different column of the matrix.
Clause 8: The method of Clause 7, wherein generating the respective LLR for that different column of the matrix based on the first power value and the second power value.
Clause 9: The method of Clause 7, further comprising: adding one or more padding bits to the second set of bits prior to arranging the second set of bits into the matrix when the second set of bits includes less bits than a configured number of bits for the set of encoded bits.
Clause 10: The method of Clause 9, wherein: the different column of the matrix for which the respective LLR is generated includes at least one padding bit; determining the first power value for the second subset of bits is based on a first value of the at least one padding bit; and determining the second power value for the third subset of bits is based on the first value of the at least one padding bit.
Clause 11: The method of Clause 10, further comprising: determining a third power value for the second subset of bits based on a second value of the at least one padding bit; and determining a fourth power value for the third subset of bits based on the second value of the at least one padding bit.
Clause 12: The method of Clause 11, further comprising: determining a first difference between the first power value and the second power value; and determining a second difference between the third power value and the fourth power value.
Clause 13: The method of Clause 12, wherein generating the respective LLR for that different column of the matrix is based on an average of the first difference and the second difference.
Clause 14: The method of Clause 2, further comprising: transmitting, to the receiving device, configuration information indicating: the number of PBRs configured for transmitting the second set of bits; and an MCS index value of the MCS configured for transmitting the second set of bits, the MCS index value corresponding to an entry in an MCS lookup table that indicates: a modulation order; and the FEC code rate.
Clause 15: The method of Clause 14, further comprising: transmitting, to the receiving device, information indicating the shaping code rate.
Clause 16: The method of Clause 15, wherein the information indicating the shaping code rate is included in the MCS lookup table and is provided by the MCS index value.
Clause 17: A method for wireless communication by a receiving device, comprising: receiving, from a transmitting device, a sequence of shaped symbols corresponding to a set of bits; converting the sequence of shaped symbols to a sequence of bit-level LLRs; decoding, based on a transport block size associated with the set of bits, the sequence of bit-level LLRs, using a FEC code rate, to obtain a set of decoded bits, the set of decoded bits including a sequence of shaping bits, a sequence of shaped bits of the set of bits, and a remaining subset of non-shaped bits of the set of bits; performing, using a shaping code rate, a deshaping operation on the sequence of shaped bits based on the sequence of shaping bits to obtain a sequence of deshaped bits; and concatenating the sequence of deshaped bits with the remaining subset of non-shaped bits to obtain the set of bits.
Clause 18: The method of Clause 17, further comprising: encoding, according to the shaping code rate, the sequence of shaping bits using a block code to obtain a deshaping codeword.
Clause 19: The method of Clause 18, wherein performing the deshaping operation on the sequence of shaped bits comprises applying the deshaping codeword to the sequence of shaped bits to deshape the sequence of shaped bits and to obtain the sequence of deshaped bits.
Clause 20: The method of any one of Clauses 17-19, further comprising: determining a size of a set of information bits (K) associated with FEC encoding of the set of bits based on a number of PRBs configured to transmit the set of bits and a MCS configured to transmit the set of bits; determining a number of resource elements (H) associated with a transport block used to transmit the set of bits based on a modulation order (Qm) and a configured number of encoded bits (E) corresponding to the set of information bits; determining a number of shaping bits (S) in the sequence of shaping bits based on the number of resource elements (H) and the shaping code rate (Rs) ; and determining the transport block size for decoding the sequence of bit-level LLRs based on the number of shaping bits (S) and the size of the set of information bits (K) associated with the FEC encoding of the set of bits.
Clause 21: The method of Clause 20, wherein decoding the sequence of bit-level LLRs comprises segmenting, based on the transport block size associated with the set of bits, the sequence of shaping bits from the sequence of shaped bits and the remaining subset of non-shaped bits.
Clause 22: The method of Clause 20, further comprising: receiving, from the transmitting device, configuration information indicating: the number of PBRs configured for transmitting the set of bits; and an MCS index value of the MCS configured for transmitting the set of bits, the MCS index value corresponding to an entry in an MCS lookup table that indicates: a modulation order; and the FEC code rate.
Clause 23: The method of Clause 22, further comprising: receiving, from the transmitting device, information indicating the shaping code rate.
Clause 24: The method of Clause 23, wherein the information indicating the shaping code rate is included in the MCS lookup table and is provided by the MCS index value.
Clause 25: An apparatus, comprising: a memory comprising executable instructions; and a processor configured to execute the executable instructions and cause the apparatus to perform a method in accordance with any one of Clauses 1-24.
Clause 26: An apparatus, comprising means for performing a method in accordance with any one of Clauses 1-24.
Clause 27: A non-transitory computer-readable medium comprising executable instructions that, when executed by a processor of an apparatus, cause the apparatus to perform a method in accordance with any one of Clauses 1-24.
Clause 28: A computer program product embodied on a computer-readable storage medium comprising code for performing a method in accordance with any one of Clauses 1-24.
Additional Considerations
The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. The examples discussed herein are not limiting of the scope, applicability, or aspects set forth in the claims. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. For example, changes may be made in the function and arrangement of elements discussed without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For instance, the methods described may be performed in an order different from that described, and various actions may be added, omitted, or combined. Also, features described with respect to some examples may be combined in some other examples. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method that is practiced using other structure, functionality, or structure and functionality in addition to, or other than, the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.
The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP) , an ASIC, a field programmable gate array (FPGA) or other programmable logic device (PLD) , discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, a system on a chip (SoC) , or any other such configuration.
As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c) .
As used herein, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure) , ascertaining and the like. Also, “determining” may include receiving (e.g., receiving information) , accessing (e.g., accessing data in a memory) and the like. Also, “determining” may include resolving, selecting, choosing, establishing and the like.
The methods disclosed herein comprise one or more actions for achieving the methods. The method actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of actions is specified, the order and/or use of specific actions may be modified without departing from the scope of the claims. Further, the various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component (s) and/or module (s) , including, but not limited to a circuit, an application specific integrated circuit (ASIC) , or processor.
The following claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language of the claims. Within a claim, reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more. ” Unless specifically stated otherwise, the term “some” refers to one or more. No claim element is to be construed under the provisions of 35 U.S.C. §112 (f) unless the element is expressly recited using the phrase “means for” . All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims.

Claims

A method for wireless communication by a transmitting device, comprising:

generating a first set of bits for transmission;

generating and attaching a plurality of cyclic redundancy check (CRC) bits to the first set of bits to obtain a second set of bits for transmission;

generating a set of log likelihood ratios (LLRs) corresponding to the second set of bits, wherein a size of the set of LLRs depends on a number of physical resource blocks (PRBs) configured for transmitting the second set of bits and a modulation and coding scheme (MCS) configured for transmitting the second set of bits;

decoding, according to a shaping code rate, the set of LLRs using a block code to obtain a sequence of shaping bits;

generating a sequence of shaped symbols based, at least in part, on the sequence of shaping bits and the second set of bits; and

transmitting the sequence of shaped symbols to a receiving device.
The method of claim 1, further comprising:

encoding, according to the shaping code rate, the sequence of shaping bits using the block code to obtain a shaping codeword;

performing, using the shaping codeword, a shaping operation on a subset of bits of the second set of bits to generate a sequence of shaped bits;

concatenating the sequence of shaped bits, a remaining subset of non-shaped bits of the second set of bits, and the sequence of shaping bits to obtain a set of information bits;

encoding, using a forward error correction (FEC) code rate, the set of information bits; and

generating the sequence of shaped symbols based on the set of encoded bits.
The method of claim 2, wherein:

a first number of bits in the shaping codeword is equal to a second number of bits in the subset of bits of the second set of bits; and

performing the shaping operation comprises bit-masking the second number of bits in the subset of bits using the first number of bits in the shaping codeword.
The method of claim 3, wherein bit-masking the second number of bits in the subset of bits comprises shifting at least some of the bits in the second number of bits to zero.
The method of claim 2, wherein generating the set of LLRs comprises arranging the second set of bits into a matrix having dimensions Qm/2 and H, where Qm is a modulation order for transmitting the second set of bits and H is two times a number of bits of the set of encoded bits (E) divided by the modulation order (Qm) .
The method of claim 5, wherein generating the set of LLRs further comprises generating a respective LLR for each different column in the matrix.
The method of claim 6, wherein generating the respective LLR for each different column of the matrix comprises:

determining a first power value for a second subset of bits of second set of bits arranged in that different column of the matrix;

flipping a value of a first bit of the second subset of bits arranged in that different column of the matrix to obtain a third subset of bits arranged in that different column of the matrix; and

determining a second power value for the third subset of bits arranged in that different column of the matrix.
The method of claim 7, wherein generating the respective LLR for that different column of the matrix based on the first power value and the second power value.
The method of claim 7, further comprising adding one or more padding bits to the second set of bits prior to arranging the second set of bits into the matrix when the second set of bits includes less bits than a configured number of bits for the set of encoded bits.
The method of claim 9, wherein:

the different column of the matrix for which the respective LLR is generated includes at least one padding bit;

determining the first power value for the second subset of bits is based on a first value of the at least one padding bit; and

determining the second power value for the third subset of bits is based on the first value of the at least one padding bit.
The method of claim 10, further comprising:

determining a third power value for the second subset of bits based on a second value of the at least one padding bit; and

determining a fourth power value for the third subset of bits based on the second value of the at least one padding bit.
The method of claim 11, further comprising:

determining a first difference between the first power value and the second power value; and

determining a second difference between the third power value and the fourth power value.
The method of claim 12, wherein generating the respective LLR for that different column of the matrix is based on an average of the first difference and the second difference.
The method of claim 2, further comprising transmitting, to the receiving device, configuration information indicating:

the number of PBRs configured for transmitting the second set of bits; and

an MCS index value of the MCS configured for transmitting the second set of bits, the MCS index value corresponding to an entry in an MCS lookup table that indicates:

a modulation order; and

the FEC code rate.
The method of claim 14, further comprising transmitting, to the receiving device, information indicating the shaping code rate.
The method of claim 15, wherein the information indicating the shaping code rate is included in the MCS lookup table and is provided by the MCS index value.
A method for wireless communication by a receiving device, comprising:

receiving, from a transmitting device, a sequence of shaped symbols corresponding to a set of bits;

converting the sequence of shaped symbols to a sequence of bit-level log likelihood ratios (LLRs) ;

decoding, based on a transport block size associated with the set of bits, the sequence of bit-level LLRs, using a forward error correction (FEC) code rate, to obtain a set of decoded bits, the set of decoded bits including a sequence of shaping bits, a sequence of shaped bits of the set of bits, and a remaining subset of non-shaped bits of the set of bits;

performing, using a shaping code rate, a deshaping operation on the sequence of shaped bits based on the sequence of shaping bits to obtain a sequence of deshaped bits; and

concatenating the sequence of deshaped bits with the remaining subset of non-shaped bits to obtain the set of bits.
The method of claim 17, further comprising encoding, according to the shaping code rate, the sequence of shaping bits using a block code to obtain a deshaping codeword.
The method of claim 18, wherein performing the deshaping operation on the sequence of shaped bits comprises applying the deshaping codeword to the sequence of shaped bits to deshape the sequence of shaped bits and to obtain the sequence of deshaped bits.
The method of claim 17, further comprising:

determining a size of a set of information bits (K) associated with FEC encoding of the set of bits based on a number of physical resource blocks (PRBs) configured to transmit the set of bits and a modulation and coding scheme (MCS) configured to transmit the set of bits;

determining a number of resource elements (H) associated with a transport block used to transmit the set of bits based on a modulation order (Qm) and a configured number of encoded bits (E) corresponding to the set of information bits;

determining a number of shaping bits (S) in the sequence of shaping bits based on the number of resource elements (H) and the shaping code rate (Rs) ; and

determining the transport block size for decoding the sequence of bit-level LLRs based on the number of shaping bits (S) and the size of the set of information bits (K) associated with the FEC encoding of the set of bits.
The method of claim 20, wherein decoding the sequence of bit-level LLRs comprises segmenting, based on the transport block size associated with the set of bits, the sequence of shaping bits from the sequence of shaped bits and the remaining subset of non-shaped bits.
The method of claim 20, further comprising receiving, from the transmitting device, configuration information indicating:

the number of PBRs configured for transmitting the set of bits; and

an MCS index value of the MCS configured for transmitting the set of bits, the MCS index value corresponding to an entry in an MCS lookup table that indicates:

a modulation order; and

the FEC code rate.
The method of claim 22, further comprising receiving, from the transmitting device, information indicating the shaping code rate.
The method of claim 23, wherein the information indicating the shaping code rate is included in the MCS lookup table and is provided by the MCS index value.
A transmitting device, comprising:

a memory comprising executable instructions; and

a processor configured to execute the executable instructions and cause the transmitting device to:

generate a first set of bits for transmission;

generate and attaching a plurality of cyclic redundancy check (CRC) bits to the first set of bits to obtain a second set of bits for transmission;

generate a set of log likelihood ratios (LLRs) corresponding to the second set of bits, wherein a size of the set of LLRs depends on a number of physical resource blocks (PRBs) configured for transmitting the second set of bits and a modulation and coding scheme (MCS) configured for transmitting the second set of bits;

decode, according to a shaping code rate, the set of LLRs using a block code to obtain a sequence of shaping bits;

generate a sequence of shaped symbols based, at least in part, on the sequence of shaping bits and the second set of bits; and

transmit the sequence of shaped symbols to a receiving device.
The transmitting device of claim 25, wherein the processor is further configured to cause the transmitting device to:

encode, according to the shaping code rate, the sequence of shaping bits using the block code to obtain a shaping codeword;

perform, using the shaping codeword, a shaping operation on a subset of bits of the second set of bits to generate a sequence of shaped bits;

concatenate the sequence of shaped bits, a remaining subset of non-shaped bits of the second set of bits, and the sequence of shaping bits to obtain a set of information bits;

encode, using a forward error correction (FEC) code rate, the set of information bits; and

generate the sequence of shaped symbols based on the set of encoded bits.
The transmitting device of claim 26, wherein:

in order to generate the set of LLRs, the processor is further configured to cause the transmitting device to arrange the second set of bits into a matrix having dimensions Qm/2 and H, where Qm is a modulation order for transmitting the second set of bits and H is two times a number of bits of the set of encoded bits (E) divided by the modulation order (Qm) ; and

in order to generate the set of LLRs, the processor is further configured to cause the transmitting device to generate a respective LLR for each different column in the matrix.
A receiving device, comprising:

a memory comprising executable instructions; and

a processor configured to execute the executable instructions and cause the receiving device to:

receive, from a transmitting device, a sequence of shaped symbols corresponding to a set of bits;

convert the sequence of shaped symbols to a sequence of bit-level log likelihood ratios (LLRs) ;

decode, based on a transport block size associated with the set of bits, the sequence of bit-level LLRs, using a forward error correction (FEC) code rate, to obtain a set of decoded bits, the set of decoded bits including a sequence of shaping bits, a sequence of shaped bits of the set of bits, and a remaining subset of non-shaped bits of the set of bits;

perform, using a shaping code rate, a deshaping operation on the sequence of shaped bits based on the sequence of shaping bits to obtain a sequence of deshaped bits; and

concatenate the sequence of deshaped bits with the remaining subset of non-shaped bits to obtain the set of bits.
The receiving device of claim 28, wherein:

the processor is further configured to cause the receiving device to encode, according to the shaping code rate, the sequence of shaping bits using a block code to obtain a deshaping codeword; and

in order to perform the deshaping operation on the sequence of shaped bits, the processor is further configured to cause the receiving device to apply the deshaping codeword to the sequence of shaped bits to deshape the sequence of shaped bits and to obtain the sequence of deshaped bits.
The receiving device of claim 28, wherein the processor is further configured to cause the receiving device to:

determine a size of a set of information bits (K) associated with FEC encoding of the set of bits based on a number of physical resource blocks (PRBs) configured to transmit the set of bits and a modulation and coding scheme (MCS) configured to transmit the set of bits;

determine a number of resource elements (H) associated with a transport block used to transmit the set of bits based on a modulation order (Qm) and a configured number of encoded bits (E) corresponding to the set of information bits;

determine a number of shaping bits (S) in the sequence of shaping bits based on the number of resource elements (H) and the shaping code rate (Rs) ; and

determine the transport block size for decoding the sequence of bit-level LLRs based on the number of shaping bits (S) and the size of the set of information bits (K) associated with the FEC encoding of the set of bits.