EP4666591A1

EP4666591A1 - Global shutter solid-state imaging device

Info

Publication number: EP4666591A1
Application number: EP24705146.9A
Authority: EP
Inventors: Golan Zeituni; Noam Zeev ESHEL
Original assignee: Sony Europe BV; Sony Semiconductor Solutions Corp
Current assignee: Sony Europe BV; Sony Semiconductor Solutions Corp
Priority date: 2023-02-16
Filing date: 2024-02-14
Publication date: 2025-12-24
Also published as: CN120677715A; WO2024170634A1

Abstract

A solid-state imaging device (90) includes a pixel circuit (100) that includes a radiation sensitive portion (110), a front stage amplifier transistor (118) and a voltage storage portion (160). A constant current source (350) and the front stage amplifier transistor (118) form a source follower configured to pass an analog voltage signal with a voltage level related to an intensity of detected radiation from the radiation sensitive portion (110) to the voltage storage portion (160) in a global operation period, wherein a constant current provided by the constant current source (350) is a capacitor charging current.

Description

GLOBAL SHUTTER SOLID-STATE IMAGING DEVICE

The present disclosure relates to a solid-state imaging device that performs analog-to-digital conversion of analog pixel signals output from pixel circuits on data signal lines. In particular, the present disclosure relates to a solid-state imaging device with voltage domain global shutter pixels.

BACKGROUND

Solid-state imaging devices have photoelectric conversion elements that generate a photocurrent proportional to the received radiation intensity. Pixel circuits convert the small photocurrents into analog pixel signals and output the analog pixel signals on common data signal lines. In solid-state imaging devices with global shutter (GS) pixels, each pixel circuit of a pixel array captures image information during a global operation period and buffers the image information until the pixel circuit is read out. Solid-state imaging devices with voltage domain global shutter pixels have a radiation sensitive portion and a voltage storage portion. In the global operation period, the radiation sensitive portion generates analog voltage signals with a voltage level that depends continuously (stepless) on the illumination intensity. A source follower passes the analog voltage signals to the voltage storage portion that stores a noise signal obtained in a reset phase and a data signal obtained in a data phase. A constant current source sinking the full source current of the source follower suppresses a feedback effect of the source follower output voltage and improves linearity of the source follower.

SUMMARY

Constant current sources sinking the source current of the source follower between radiation sensitive portion and voltage storage portion of a GS pixel are typically based on field effect transistors (FETs) with constantly biased gate. Integration in the pixel circuits requires FETs with lateral dimensions where technological limitations lead to comparatively large variations in the lateral dimensions and transistor characteristics. Deviations between constant current sources assigned to different pixel circuits can lead to significant deviations between the required transfer times from the radiation sensitive portions to the voltage storage portions.

The present disclosure mitigates such shortcomings of the prior art. In particular, the present disclosure provides a solid-state imaging device having pixel circuits that use a constant capacitor charging current to sink the source current of the source follower between the radiation sensitive portion and the voltage storage portion. Such a constant capacitor charge current can be provided to the pixel circuits of a pixel array with no or little variation from pixel to pixel due to manufacturing.

Accordingly, a solid-state imaging device in accordance with the present disclosure includes a pixel circuit and a constant current source. The pixel circuit includes a radiation sensitive portion, an amplifier transistor and a voltage storage portion. The amplifier transistor and the constant current source form a source follower configured to pass an analog signal with a voltage level related to an intensity of detected radiation from the radiation sensitive portion to the voltage storage portion in a global operation period. A current delivered by the constant current source is a capacitor charging current.

Embodiments of the present disclosure provide a constant capacitor charging current for sinking the source current of the source follower between the radiation sensitive portion and the voltage storage portion. Pixel- to-pixel variations in the required minimum time for the signal transfer from the radiation sensitive portion to the voltage storage portion can be reduced. A global hold time that must be waited for reliably moving the image information completely to the voltage storage portion can be reduced. The capacitive current source can reduce pixel-to-pixel variations and/or latency of GS pixels.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

FIG. 1 is a simplified block diagram of a solid-state imaging device using a constant capacitor charging current for sinking the source current of a source follower between radiation sensitive portion and voltage storage portions of GS pixels in accordance with an embodiment of the present technology.

FIG. 2 is a simplified circuit diagram of a GS pixel circuit using a constant capacitor charging current for sinking the source current of a source follower between radiation sensitive portion and voltage storage portion in accordance with an embodiment of the present technology.

FIG. 3 is a simplified circuit diagram of a portion of a solid-state imaging device including a voltage ramp circuit and a current source capacitor for supplying a constant capacitor charging current in accordance with an embodiment of the present technology.

FIG. 4 is a simplified block diagram of a solid-state imaging device with a voltage ramp circuit supplying a constant capacitor charge current for GS pixel circuits in accordance with an embodiment of the present technology.

FIG. 5 is a circuit diagram of a GS pixel circuit and a voltage ramp circuit supplying a constant capacitor charge current for the GS pixel circuit in accordance with an embodiment of the present technology.

FIG. 6 is a circuit diagram of a GS pixel circuit with an auxiliary transistor for temporarily separating the buffer paths of the voltage storage portion in accordance with an embodiment of the present technology.

FIG. 7 illustrates time diagrams for a variable global bias voltage AMD supplied to the GS pixel circuits of FIG. 5 and FIG. 6 according to an embodiment. FIG. 8 schematically illustrates a layout for distributing the global bias voltage AMD in a pixel array according to an embodiment.

FIG. 9 illustrates time diagrams for a variable auxiliary voltage VRG supplied to the GS pixel circuits of FIG. 5 and FIG. 6 according to an embodiment.

FIG. 10 schematically illustrates a layout for distributing the auxiliary voltage VRG in a pixel array according to an embodiment.

FIG. 11 illustrates time diagrams for a ramp signal RMP output by the voltage ramp circuits of FIG. 5 and FIG. 6 according to an embodiment.

FIG. 12 schematically illustrates a layout for distributing the ramp signal RMP in a pixel array according to an embodiment.

FIG. 13 illustrates a further time diagram for the ramp signal RMP according to an embodiment using the ramp signal for controlling the voltages in buffer paths of the voltage storage portion according to an embodiment.

FIG. 14A and FIG. 14B show time diagrams for control signals and internal signals of GS pixel circuits in a global operating period in accordance with embodiments of the present technology.

FIG. 15A and FIG. 15B show time diagrams for control signals and internal signals of GS pixel circuits in a readout waiting period in accordance with embodiments of the present technology.

FIG. 16A and FIG. 16B show time diagrams for control signals and internal signals of GS pixel circuits in a row readout period in accordance with embodiments of the present technology.

FIG. 17 and FIG. 18 show voltages at both sides of buffer switches in buffer paths of the GS pixel circuits to discuss effects of the embodiments.

FIG. 19 is a simplified circuit diagram illustrating a part of a voltage ramp circuit generating a voltage ramp signal by DA conversion.

FIG. 20 is a simplified circuit diagram illustrating a part of a voltage ramp circuit generating a voltage ramp signal by DA conversion.

FIG. 21 is a simplified circuit diagram illustrating a configuration example of a ramp generator including a counter unit.

FIG. 22 is a diagram showing an example of a laminated structure of a solid-state imaging device according to an embodiment of the present disclosure. FIG. 23 is a schematic circuit diagram of a pixel circuit with elements of the pixel circuit formed on a first chip of a solid-state imaging device with laminated structure according to an embodiment.

FIG. 24 to FIG. 28 are schematic circuit diagrams of GS pixel circuits using a constant capacitor charging current for a signal transfer between radiation sensitive portion and voltage storage portion in accordance with further embodiments of the present technology.

FIG. 29 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

FIG. 30 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section of the vehicle control system of FIG. 29.

DETAILED DESCRIPTION

Embodiments for implementing techniques of the present disclosure (also referred to as “embodiments” in the following) will be described below in detail using the drawings. The techniques of the present disclosure are not limited to the described embodiments, and various features in the embodiments are illustrative only. The same elements or elements with the same functions are denoted by the same reference signs. Duplicate descriptions are omitted.

Connected electronic elements may be electrically connected through a direct, permanent low-resistive connection, e.g., through a conductive line. The terms “electrically connected” and “signal-connected” may also include a connection through other electronic elements provided and suitable for permanent and/or temporary signal transmission and/or transmission of energy. Electronic elements can be electrically connected or signal-connected via resistors, capacitors, electronic switches such as FETs (field effect transistors), or transistor circuits such as transmission gates. The load path of a transistor is the controlled path of a transistor. For example, a voltage applied to a gate of a FET controls by field effect the current flow in the load path between source and drain.

Though in the following a technology for improving image quality and/or frame rate of solid-state imaging devices with GS pixels is described in the context of certain types of voltage domain GS pixels, the technology may also be used for other types of GS pixel.

FIG. 1 illustrates a configuration example of a solid-state imaging device 90 in accordance with embodiments of the present technology. The solid-state imaging device 90 includes an image sensor assembly 70 and a signal processing unit 80. The image sensor assembly 70 includes a pixel array 10, a column signal processing unit 20, a vertical scanning unit 30, a readout buffer memory 40 and a sensor controller 50.

The pixel array unit 10 includes a plurality of identical pixel circuits 100 adapted for global shutter operation. Each pixel circuit 100 includes a radiation sensitive portion 110 and a voltage storage portion 160. The radiation sensitive portion 110 converts incident radiation into analog voltage signals and may broadly correspond to any active pixel sensor for intensity readout having one or two photoelectric conversion elements and three, four or more FETs.

The radiation sensitive portion 110 includes a front stage amplifier transistor 118 for passing the analog voltage signals to the voltage storage portion 160. The front stage amplifier transistor 118 is in a source follower configuration. A drain of the front stage amplifier transistor 118 is electrically connected to a positive voltage. A constant current source 350 delivers a constant capacitor charging current and sinks the source current of the front stage amplifier transistor 118 that outputs the analog voltage signals to the voltage storage portion 160 in a global operation period.

The voltage storage portion 160 buffers the received analog voltage signals until readout. A post stage amplifier transistor 168 outputs pixel signals derived from the buffered analog voltage signals on one or two data signal lines 19 connecting a group of pixel circuits 100 with the column signal processing unit 20.

The photoelectric conversion elements of the pixel array 10 may be arranged matrix-like in columns and rows. A subset of pixel circuits 100 assigned to the same column of photoelectric conversion elements 101 form a pixel column. A subset of pixel circuits 100 assigned to the same row of photoelectric conversion elements 101 form a pixel row.

The vertical scanning unit 30 generates pixel control signals for operating and selecting groups of pixel circuits 100. The pixel control signals control pixel reset, pixel exposure, pixel-internal temporal storage of illumination information, transmission of the analog voltage signals from the radiation sensitive portion 110 to the voltage storage portion 160, and output of the pixel signals through the data signal lines 19.

The vertical scanning unit 30 controls all pixel circuits 100 of a selected group of pixel circuits 100 synchronously. The selected group of pixel circuits 100 may include some pixel circuits 100 of one pixel row, all pixel circuits 100 of one pixel row, or some or all pixel circuits 100 of more than one pixel row. In the following part of the description, “pixel row” is often referred to as an example of “group of pixel circuits” for simplicity. The vertical scanning unit 30 outputs the control signals for operation of the FETs according to driver timing signals provided by the sensor controller 50.

The voltage storage portions 160 of a pixel output group sequentially route the pixel signals to one or two data signal lines (vertical signal lines) 19. Each pixel output group may include some pixel circuits 100 of one pixel column, all pixel circuits 100 of one pixel column, or some or all pixel circuits 100 of more than one pixel column. In the following part of the description, “pixel column” is often referred to as an example of “pixel output group” for simplicity.

The post stage amplifier transistor 168 may be in a source follower configuration with elements of the column signal processing unit 20, wherein a load path of the post stage amplifier transistor 168 is electrically connected between a positive logic supply voltage VDD and the data signal line 19. Each data signal line 19 sequentially transmits pixel signals from the pixel circuits 100 of one of the pixel columns to the column signal processing unit 20.

The column signal processing unit 20 includes a column signal processing circuit 200 for each data signal line 19 or for each pair of data signal lines 19. The column signal processing circuit 200 converts the pixel signals into digital pixel values, may preprocess the digital pixel values and outputs the digital pixel values or the preprocessed digital pixel values to the readout buffer memory 40. The readout buffer memory 40 temporarily stores the digital pixel values.

The sensor controller 50 generates the driver timing signal and outputs the driver timing signals to the vertical scanning unit 30. The sensor controller 50 generates column control signals for controlling the column signal processing unit 20 and may generate a readout control signal that controls the readout of the digital pixel values from the readout buffer memory 40 to the signal processing unit 80 and/or to a digital interface.

FIG. 2 shows components of a solid-state imaging device 90 with voltage domain global shutter pixels.

The solid-state imaging device 90 includes a pixel circuit 100. The pixel circuit 100 includes a radiation sensitive portion 110, a front stage amplifier transistor 118 and a voltage storage portion 160. A constant current source 350 and the front stage amplifier transistor 118 form a source follower configured to pass an analog voltage signal having a voltage level dependent on an intensity of detected radiation from the radiation sensitive portion 110 to the voltage storage portion 160 in a global operation period. A constant current leap delivered from the constant current source 350 is a capacitor charging current.

The radiation sensitive portion 110 may include a single photodetector or two or more photodetectors, e.g., photodetectors having different sensitivities. The radiation sensitive portion 110 may include four, five or more transistors configured to control resetting, exposure time and internal readout of the photodetector(s) according to an arbitrary intensity readout scheme. A floating diffusion potential Vfd at the gate of the a front stage amplifier transistor 118 decreases steadily with steadily increasing intensity of the radiation received by the photodetector.

The front stage amplifier transistor 118 outputs the analog voltage signals at a transfer node 120 between the source of the front stage amplifier transistor 118 and the constant current source 350 in a global operation period, wherein the constant current source 350 sinks the source current of the front stage amplifier transistor 118 by charging a capacitance at a constant rate. The constant current source 350 includes one or more elements forming part of the pixel circuit 100 and/or one or more elements shared by some or all pixel circuits 100. The transfer node 120 forms a signal interface between the radiation sensitive portion 110 and the voltage storage portion 160.

The constant current source 350 and the front stage amplifier transistor 118 complement each other to form a source follower. In the global operation periods, the constant current source 350 provides an active load for the front stage amplifier transistor 118. Outside the global operation periods, the front stage amplifier transistor 118 can be separated from the constant current source 350.

The voltage storage portion 160 receives and buffers the analog voltage signals for a readout waiting period. In the readout waiting period, the voltage storage portion 160 holds the analog voltage signals in one or more voltage storage elements. The voltage storage elements may be buffer capacitors with low leakage current. The capacitor electrodes of the buffer capacitors may include metallic structures separated from each other and from a semiconductor portion of the pixel circuit 100 by dielectric layers. For example, the voltage storage elements are metal -insulator-metal capacitors (MIM capacitors).

The voltage storage portion 160 outputs analog pixel signals imaging the analog voltage signals to a data signal line 19 in a row readout period. A column signal processing circuit 200 receives the pixel signals through the data signal line 19 and converts the analog pixel signals into digital pixel values.

The global operation period applies to all pixel circuits 100 of the pixel array at the same time. The row readout period is the same for all pixel circuits 100 of a same group of pixel circuits, e.g., the same pixel row. The pixel rows are read out successively.

Each pixel circuit 100 operates as a voltage domain global shutter pixel. An electronic global shutter provides simultaneous exposure of the radiation sensitive portions 110 of all pixel circuits 100 during an exposure period. Each radiation sensitive portion 110 generates an analog voltage signal with a voltage level related to an intensity of the radiation detected during the exposure period. In a part of the global operation period after the exposure period, each radiation sensitive portion 110 transmits the analog voltage signal to the voltage storage portion 160. The voltage storage portion 160 holds the analog voltage signals until the corresponding pixel signals are read out through the data signal line 19, which is shared by a plurality of pixel circuits 100 assigned to the same pixel column. The voltage storage portions 160 facilitate a row-by-row readout for pixel circuits 100 that use a global shutter.

Typically, constant current sources for single pixel circuits are based on transistors with biased gate. For constant currents in the range of few nanoamperes as required for the source follower transferring the analog voltage signals from the radiation sensitive portion 110 to the voltage storage portion 160, the dimensions of the transistors are comparatively small. Then manufacturing constraints can result in comparatively high variations between the channel widths of the transistors. The channel width variations can result in high deviations between the currents delivered by the transistor-based constant current sources. The different constant currents in the pixel circuits 100 of an image sensor can lead to image distortions and/or long transfer periods. The constant current source 350, which excites a constant capacitor charging current, does not require additional transistors with biased gate in the pixel circuits 100. Image defects caused by such transistors can be avoided. A constant current source based on a biased gate transistor generates large 1/f noise, wherein the smaller the transistor area, the larger the 1/f noise can be. Instead, a constant current source built of MIM capacitors does not generate 1/f noise. In FIG. 3, the constant current source 350 includes a current source capacitor 351 for each pixel circuit 100 and a voltage ramp circuit 352. The current source capacitor 351 is electrically connected between a source of the front stage amplifier transistor 118 of the pixel circuit 100 and an output of the voltage ramp circuit 352. The voltage ramp circuit 352 is configured to supply a linear voltage ramp to the current source capacitors 351 in ramp phases of the global operation period.

A load path of a front stage select transistor 119 is electrically connected in series between the source of the front stage amplifier transistor 118 and the current source capacitor 351. The transfer node 120 is between the front stage select transistor 119 and the current source capacitor 351. The front stage select transistor 119 can be an nFET. In the global operation period, an active global select signal SW turns on the front stage select transistor 119. For the readout waiting period and the row readout period, the global select signal SW is inactive and turns off the front stage select transistor 119 to separate the front stage amplifier transistor 118 from the transfer node 120.

Alternatively, the current source capacitor 351 may be directly connected to the source of the amplifier transistor 118, or more intervening elements may be electrically connected between the current source capacitor 351 and the source of the amplifier transistor 118, wherein the intervening elements may include transistors operated as switches.

An output of the voltage ramp circuit 352 may be directly connected to the current source capacitors 351. Alternatively, one, two, or more intervening elements may be electrically connected between the current source capacitors 351 and the output of the voltage ramp circuit 352. The intervening elements may include one or more transistors operated as switches and/or buffers.

For each pixel circuit 100, a load path between source and drain of the front stage amplifier transistor 118, the current source capacitor 351, and a drive path of the voltage ramp circuit 352 may be electrically connected in series between a conductor having a positive potential, e.g., a global bias voltage AMD and a conductor having a reference potential VSS. The current path between the conductors for the global bias voltage AMD and the reference potential VSS through the front stage amplifier transistor 118 may include further electronic elements.

The current source capacitor 351 has a capacitance C in the source path of the front stage amplifier transistor 118. In the global operation period, the voltage ramp circuit 352 applies a linear voltage ramp with a constant slope ratio Vrmp/Trmp to a first electrode of the current source capacitor 351 (first capacitor electrode). When the front stage amplifier transistor 118 maintains a constant output voltage at a second electrode of the current source capacitor 351 (second capacitor electrode), then the second capacitor electrode sinks a constant charge current Ic = (Vrmp*C)/Trmp.

During the global operation period, the front stage amplifier transistor 118 forces a voltage at the transfer node 120 to a voltage level that is a function of the floating diffusion potential Vfd at the gate of the front stage amplifier transistor 118. Provided that simultaneously a sufficiently steep voltage ramp is supplied to the first capacitor electrode, the current source capacitor 351 sinks the required constant current through the second capacitor electrode.

For the constant current source using a capacitor charge current, the amplitude of the supplied or sunk constant current depends on the capacitance C of the current source capacitor and a slope ratio of a voltage ramp supplied to the current source capacitor. The same ramp signal can be supplied to a plurality of current source capacitors. The process for forming capacitors with a capacitance in the pertinent value range between 5 and 500fF, e.g., in a range from 35fF to lOOfF on a semiconductor substrate is well controllable. Capacitance fluctuations among capacitors manufactured on the same semiconductor substrate are comparatively low. The source followers in the pixel circuits 100 can be formed with comparatively little effort with only negligible deviations for the constant currents. The constant current source 350 with the voltage ramp circuit 352 and current source capacitors 351 can improve image quality.

In the voltage storage portion 160, a load path of a post stage amplifier transistor 168 and a load path of a post stage select transistor 169 are electrically connected in series between a conductor having a positive logic supply voltage VDD and the data signal line 19. A current source circuit 210 supplying a constant current is electrically connected between the data signal line 19 and the reference potential VSS. Internal voltages V2 imaging the buffered analog voltage signals are sequentially applied to the gate of the post stage amplifier transistor 168. The post stage amplifier transistor 168 and the current source circuit 210 form a source follower that outputs analog pixel signals to the data signal line 19, wherein the current source circuit 210 sinks a constant current.

The post stage select transistor 169 can be an nFET. In the row readout period, an active row select signal SEL turns on the post stage select transistor 169 to connect the post stage amplifier transistor 169 with the data signal line 19. Outside the row readout periods, the row select signal SEL is inactive and turns off the post stage select transistor 169 to separate the post stage amplifier transistor 168 from the data signal line 19.

FIG. 4 shows a column signal processing unit 20 having a column signal processing circuit 200 for each data signal line 19 or for each pair of data signal lines 19, a voltage ramp generator 25, and a counter circuit 26. The pixel circuits 100 may output the pixel signals for a reset phase (noise signal) and a data phase (data signal) sequentially on the same data signal line 19 or simultaneously on a pair of data signal lines 19. Each column signal processing circuit 200 includes a current source circuit 210, a comparator circuit 220, and a digital circuit 230.

The current source circuit 210 complements the post stage amplifier transistor 168 to a source follower that outputs the pixel signals of a selected pixel circuit 100 to a first input of the comparator circuit 220 in a row readout period. The current source circuit 210 sinks a constant current.

The voltage ramp generator 25 outputs a voltage ramp signal in response to an active ramp enable signal. The voltage ramp signal falls from a high voltage level to a low voltage level continuously or in small steps. The voltage ramp signal is applied to the second inputs of the comparator circuits 220 in the row readout periods. The comparator circuit 220 outputs an active comparator output signal when the voltage level of the voltage ramp signal falls below the voltage level of the pixel signal applied to the first input of the comparator circuit 220.

The counter circuit 26 outputs a digital count value of a digital counter on a digital bus to data inputs of the digital circuits 230 in response to an active count enable signal. The active count enable signal and the active ramp enable signal have a predetermined temporal relationship to each other and to the start of the row readout period. The digital circuit 230 latches the current count value applied to the data inputs with a transition from an inactive comparator output signal to the active comparator output signal. The latched count value represents the digital pixel value of the pixel signal obtained from the pixel circuit 100 in the row readout period.

Instead of one counter circuit 26 whose counter values are applied to all digital circuits 230, the column signal processing unit 20 may include one counter circuit for each digital circuit 230 or for each subset of digital circuits 230. Instead of one voltage ramp generator 25 whose voltage ramp signal is applied to all comparator circuits 220, the column signal processing unit 20 may include one voltage ramp generator 25 for each comparator circuit 220 or for each subset of comparator circuits 220.

The digital circuit 230 may include an arithmetic logic unit for preprocessing the digital pixel values. For each row readout period, the arithmetic logic unit may calculate corrected pixel values from a digital pixel value obtained in the reset phase (P phase) and a digital pixel value obtained from the same pixel circuit 100 in the data phase (D phase). The arithmetic logic unit may perform DCDS (digital correlated double sampling) and subtract the digital pixel value obtained in the reset phase from the digital pixel value obtained from the same pixel circuit 100 in the data phase to obtain the corrected pixel value. The data phase follows the reset phase in the same global operation period.

The column signal processing circuits 200 output the digital pixel values to a readout buffer memory 40. The readout buffer memory 40 temporarily stores the digital pixel values.

The constant current source 350 includes one current source capacitor 351 per each pixel circuit 100 and a single voltage ramp circuit 352. In each pixel circuit 100, the current source capacitor 351 is electrically connected in a path connecting a source of the front stage amplifier transistor 118 of the pixel circuit 100 and an output of the voltage ramp circuit 352.

The solid-state imaging device 90 further includes a vertical scanning unit 30 configured to output a variable global bias voltage AMD and to pass the variable global bias voltage AMD to drains of the front stage amplifier transistors 118.

In particular, the drains of the front stage amplifier transistors 118 and an output of the vertical scanning unit 30 are electrically connected to an AMD conductor for the global bias AMD. All pixel circuits 100 can be electrically connected to the same AMD conductor. The AMD conductor can include a plurality of column sections, wherein each column section runs parallel to a pixel column and is connected to all pixel circuits 100 of the pixel column.

The global bias voltage AMD is transmitted to all pixel circuits 100 simultaneously. The global bias voltage AMD changes between at least two, e.g., three different voltage levels to support and/or improve the functionality of the voltage storage portion.

The vertical scanning unit 30 outputs further control signals for controlling the pixel circuits 100, such as the global select signal SW and the row select signals SEL for the various pixel rows. In addition, the vertical scanning unit 30 can output a control signal for controlling the voltage ramp circuit 352 to control the output of a linear voltage ramp in ramp phases of the global operating period, wherein the linear voltage ramp and the global select signal SW applied to the front stage select transistors 119 have a predetermined time relationship. The constant current source 350 with the voltage ramp circuit 352 and the current source capacitor 351 provides a switched capacitor current source supplying at least temporarily a constant current to the transfer node 120 of the pixel circuit 100.

The vertical scanning unit 30 may be configured to change the global bias voltage AMD between a low level in pre-charge phases and a high level outside the pre-charge phases in the global operation period.

In the global operation period, each pre-charge phase precedes a ramp phase. In a first ramp phase (reset phase, P phase), the front stage amplifier transistor 118 passes a reset signal for a correlated double sampling readout (CDS readout) to the voltage storage section 160. In a second ramp phase (data phase, D phase), the front stage amplifier transistor 118 passes a data signal for the CDS readout to the voltage storage section 160. In the pre-charge phases, the front stage amplifier transistors 118 are on and pass the global bias voltage AMD to the transfer nodes 120 of all pixel circuits 100 simultaneously, wherein at that time the global bias voltage AMD has a low voltage level. At the end of the pre-charge phases, the transfer nodes 120 of the pixel circuits 100 are in a defined initial state with a low voltage. In the immediately following reset and data phases, the global bias voltage AMD changes to high level. The transfer node 120 is charged to the data signal level and the reset signal level by the comparatively high current provided by the front stage amplifier transistor 118, which is in a high-efficiency source follower configuration, rather than being discharged by the comparatively low charging current of the current source capacitor. The total time required for a transfer of the analog voltage signals from the radiation sensitive portion 110 to the voltage storage portion 160 can be reduced.

According to another embodiment with the voltage storage portion 160 being configured to pass pixel signals obtained from the analog voltage signals to a data signal line 19 in a row readout period, the vertical scanning unit 30 can be configured to drive the global bias voltage AMD at a medium level in the row readout period.

The medium level is higher than the low level of the global bias voltage AMD in the pre-charge phases and lower than the high level of the global bias voltage AMD in the ramp phases of the global operation period. The medium level may be equal to or may approximate a reset level obtained by subtracting the gate-to- source voltage of the front stage amplifier transistor 118 from a positive pixel supply voltage VDDH to reduce fixed pattern noise (FPN) resulting from a mismatch of two buffer capacitors for buffering the analog voltage signals for the data signal and the noise signal in the voltage storage portion 160. The positive logic supply voltage VDD and the positive pixel supply voltage VDDH may be equal or may be different.

The sensor controller 50 generates the driver timing signal and outputs the driver timing signals to the vertical scanning unit 30. The sensor controller 50 generates column control signals for controlling the column signal processing unit 20. In particular, the sensor controller 50 outputs the ramp enable signal for synchronizing the voltage ramp generator 25 and a counter enable signal for synchronizing the counter circuit 26. The sensor controller 50 may generate a readout control signal that controls the readout of the digital pixel values from the readout buffer memory 40 to the signal processing unit 80 and/or via a digital interface.

FIG. 5 shows an example of a voltage domain GS pixel with a radiation sensitive portion 110 based on a design with six transistors in combination with one photodetector (photoelectric conversion element) 101. Each of the transistors is or includes an nFET.

The photoelectric conversion element 101 photoelectrically converts incident electromagnetic radiation into electric charges. The amount of electric charge generated in the photoelectric conversion element 101 corresponds to the intensity of the incident electromagnetic radiation. The photoelectric conversion element 101 may include or consist of a photodiode which converts electromagnetic radiation incident on a detection surface into a detector current by means of the photoelectric effect. The electromagnetic radiation may include visible light, infrared radiation and/or ultraviolet radiation. The amplitude of the detector current corresponds to the intensity of the incident electromagnetic radiation, wherein in the intensity range of interest the detector current increases approximately linearly with increasing intensity of the detected electromagnetic radiation.

A first electrode of a floating diffusion capacitor 116 stores charge supplied from the photoelectric conversion element 101 in a transfer period. The first electrode of the floating diffusion capacitor 116 may be a floating diffusion region. A floating diffusion voltage Vfd of the first capacitor electrode depends on the state of the radiation sensitive portion 110: In a reset phase, the floating diffusion voltage Vfd is a function of the pixel dark current representing the noise. In a data phase, the floating diffusion voltage Vfd is a function of the brightness (illumination intensity) sampled by the radiation sensitive portion 110.

A front stage amplifier transistor 118 is in a source follower configuration, with the controlled load path electrically connected between a global bias voltage AMD and a transfer node 120 that forms a signal interface between the radiation sensitive portion 110 and a voltage storage portion 160. The first electrode of the floating diffusion capacitor 116 is connected to the gate of the front stage amplifier transistor 118. A potential at the gate of the front stage amplifier transistor 118 is equal to the floating diffusion voltage Vfd. The first electrode of the floating diffusion capacitor 116 functions as the input node of the front stage amplifier transistor 118. A load path of a transfer transistor 112 is electrically connected between a cathode of the photoelectric conversion element 101 and the first electrode of the floating diffusion capacitor 116. The transfer transistor 112 serves as transfer element for transferring charge from the photoelectric conversion element 101 to the first electrode of the floating diffusion capacitor 116 in a transfer period. The floating diffusion capacitor 116 serves as temporary local charge storage. A transfer signal TRG is supplied to the gate (transfer gate) of the transfer transistor 112 through a transfer control line. The transfer signal TRG changes between an active signal level (“active transfer signal”) and an inactive signal level (“inactive transfer signal”). In response to an active transfer signal TRG, the transfer transistor 112 transfers electrons photoelectrically converted by the photoelectric conversion element 101 to the first electrode of the floating diffusion capacitor 116. In the illustrated embodiment, the active signal level is the high level.

A load path of a PD reset transistor (photodetector reset transistor) 113 is electrically connected between a positive pixel supply voltage VDDH and a cathode of the photoelectric conversion element 101. The PD reset transistor 113 serves as a reset element that pre-charges the cathode of the photoelectric conversion element 101. A PD reset signal OFG is supplied to the gate of the PD reset transistor 113 through a PD reset control line. The PD reset signal OFG has an active signal level and an inactive signal level. An active PD reset signal OFG sets the potential at the cathode of the photoelectric conversion element PD equal to or approximately equal to the positive pixel supply potential VDDH.

A load path of an FD reset transistor 114 is connected between a reset potential that may be the positive pixel supply voltage VDDH and the load path of an intervening transistor 115. The load path of the intervening transistor 115 is connected between the load path of the FD reset transistor 114 and the gate of the front stage amplifier transistor 118. A supplementary capacitive structure 117 is electrically connected between a network node between the FD reset transistor 114 and the intervening transistor 115. A capacitance of the supplementary capacitive structure 117 includes at least the parasitic capacitance of the network node between the FD reset transistor 114 and the intervening transistor 115.

A capacitance control signal FDG applied to a gate of the intervening transistor 115 controls the intervening transistor 115. A reset signal RST applied to a gate of the FD reset transistor 114 controls the FD reset transistor 114.

When an active capacitance control signal FDG turns on the intervening transistor 115, the capacitance of the supplementary capacitive structure 117 adds to the capacitance of the floating diffusion capacitor 116. A comparatively high amount of charge can be discharged by the detector current signal such that even under bright illumination conditions the total capacitance is not completely discharged during the exposure period and the dynamic range is high. On the other hand, sensitivity under dark illumination conditions is low.

When an inactive capacitance control signal FDG turns off the intervening transistor 115, the supplementary capacitive structure 117 is decoupled from the floating diffusion capacitor 116. Even a small detector current signal may result in a comparatively high voltage signal swing at the first electrode of the floating diffusion capacitor 116 under dark illumination conditions. On the other hand, the comparatively small capacitance of the floating diffusion capacitor 116 alone may be completely discharged before the end of the exposure period under bright illumination conditions such that the dynamic range is low.

In pixel circuits without intervening transistor 115, the load path of the reset transistor 114 can directly connect the positive pixel supply voltage VDDH and the first electrode of the floating diffusion capacitor 116. The reset transistor 114 serves as a reset element that resets the floating diffusion potential Vfd at the gate of the front stage amplifier transistor 118. A pixel reset signal RST is supplied to the gate of the reset transistor 114 through a reset control line. The pixel reset signal RST changes between an active signal level (“active pixel reset signal”) and an inactive signal level (“inactive pixel reset signal”). In the illustrated embodiment, the active signal level is the high level. An active pixel reset signal RST sets the floating diffusion potential Vfd equal to or approximately equal to a pixel reset voltage. The pixel reset voltage may be a fixed voltage, e.g., the positive pixel supply voltage VDDH, or may be adaptively controlled by a compensation circuit.

A load path of a front stage select transistor 119 is electrically connected in series between the source of the front stage amplifier transistor 118 and the transfer node 120. The transfer node 120 is between the front stage select transistor 119 and the current source capacitor 351. The front stage select transistor 119 is an nFET. In the global operation period, an active global select signal SW turns on the front stage select transistor 119. At least for the greater part of the readout waiting period and the row readout period, the global select signal SW is inactive and turns off the front stage select transistor 119 to separate the front stage amplifier transistor 118 from the transfer node 120.

The gates of the transfer transistors 112, the gates of the PD reset transistors 113, the gates of the FD reset transistors 114, and the gates of the intermediate transistors 115 may each be connected for groups of pixel circuits 100, e.g., pixel rows, such that the operations for each of the pixel circuits 100 of one group of pixel circuits 100, e.g., one pixel row are performed simultaneously. One single global select signal SW may control all pixel circuits 100 of a pixel array.

The voltage storage portion 160 includes a first buffer path and a second buffer path. The first buffer path includes a first buffer capacitor 161 and a first buffer switch 163 electrically connected in series. The second buffer path includes a second buffer capacitor 162 and a second buffer switch 164 electrically connected in series. The first buffer path and the second buffer path are electrically connected in parallel between a transfer node 120 and a sample node 170, wherein the transfer node 120 is formed between the amplifier transistor 118 and the current source capacitor 351 of the pixel circuit 100.

A first electrode of the first buffer capacitor 161 is directly connected to the transfer node 120 between the amplifier transistor 118 and the current source capacitor 351. A second electrode of the first buffer capacitor 161 is connected to a first load electrode of the first buffer switch 163. A first electrode of the second buffer capacitor 162 is connected to the transfer node 120 directly or through a switch. A second electrode of the second buffer capacitor 162 is connected to a first load electrode of the second buffer switch 164. The second load electrodes of the first buffer switch 163 and the second buffer switch 164 are connected to the sample node 170. The two buffer paths facilitate to sequentially store a voltage level for a noise signal on the first buffer capacitor 161 in a reset phase and a voltage level for a data signal of a CDS readout on the second buffer capacitor 162 in a data phase.

The voltage storage portion 160 further includes a post stage amplifier transistor 168 configured to output a pixel signal on a data signal line 19, wherein a voltage level of the pixel signal is related to the analog voltage signal passed to the voltage storage portion 160.

The post stage amplifier transistor 168 and a current source circuit 210 of a column signal processing circuit 200 are in a source follower configuration. The sample node 170 is connected to the gate of the post stage amplifier transistor 168. Internal voltages V2 passed to the sample node 170 image the buffered analog voltage signals and are sequentially applied to the gate of the post stage amplifier transistor 168. The post stage amplifier transistor 168 outputs analog pixel signals to the data signal line 19, wherein the current source circuit 210 sinks a constant current.

The load path of a post stage select transistor 169 and the load path of the post stage amplifier transistor

168 are electrically connected in series between a conductor having a positive logic supply voltage VDD and the data signal line 19.

A row select signal SEL is supplied to the gate of the post stage select transistor 169 through a select control line. The row select signal SEL changes between an active signal level (“active select signal”) and an inactive signal level (“inactive select signal”). In the illustrated embodiment, the post stage select transistor

169 is an nFET and the active signal level is the high level.

In the row readout periods, an active row select signal SEL turns on the post stage select transistor 169 to connect the post stage amplifier transistor 169 to the data signal line 19. Outside the row readout periods, the row select signal SEL is inactive and turns off the post stage select transistor 169 to disconnect the post stage amplifier transistor 168 from the data signal line 19. When the post stage select transistor 169 is on, the post stage amplifier transistor 169 operates in a source-follower configuration.

The voltage storage portion 160 further includes a post stage reset transistor 165 configured to temporarily connect the sample node 170 to a variable auxiliary voltage VRG.

The post stage reset transistor 165 temporarily connects the sample node 170 to a VRG line 391, wherein the variable auxiliary voltage VRG of the VRG line 391 is at least temporarily higher than the reference potential VSS. A buffer reset signal RB is supplied to the gate of the post stage reset transistor 165 through a buffer reset line. The buffer reset signal RB changes between an active signal level (“active buffer reset signal”) and an inactive signal level (“inactive buffer reset signal”). In the illustrated embodiment, the post stage reset transistor 165 is an nFET and the active signal level is the high level. In FIG. 6. the pixel circuit 100 includes an auxiliary transistor 121 configured to separate the first buffer capacitor 161 and the second buffer capacitor 162 in a readout waiting period following the global operation period.

Separating the second buffer capacitor 162 from the first buffer capacitor 161 in the readout waiting period facilitates to set different potentials at the first electrodes of the first and second buffer capacitors 161, 162. By applying suitable potentials to the separated first capacitor electrodes and the sample node 170, the potentials at both sides of the first buffer switch 163 and at both sides of the second buffer switch 164 can be approximately equal when the first and second buffer switches 163, 164 are switched off. Gate-induced drain leakage through the first and second (transistor) switches 163, 164 during the readout waiting period can be reduced. Since the readout waiting periods can be comparatively long, the effect can be significant.

The auxiliary transistor 121 can be electrically connected between a first electrode of the first buffer capacitor 161 and a first electrode of the second buffer capacitor 162. An auxiliary signal DIFF applied to a gate of the auxiliary transistor 121 turns off the auxiliary transistor 121 in a readout waiting period following a global operation period.

A load path of the auxiliary transistor 121 is electrically connected between the transfer node 120 and the current source capacitor 351. The auxiliary signal DIFF is supplied to the gate of the auxiliary transistor 121 through an auxiliary line. The auxiliary signal DIFF changes between an active signal level (“active auxiliary signal”) and an inactive signal level (“inactive auxiliary signal”). In the illustrated embodiment, the auxiliary transistor 121 is an nFET and the active signal level is the high level. In at least a portion of the readout waiting period, the auxiliary signal DIFF is inactive and turns off the auxiliary transistor 121 to separate the first buffer capacitor 161 and the second buffer capacitor 162. In at least portions of the global operating periods and the row readout periods or for the complete global operating periods and/or the complete row readout periods, the auxiliary signal DIFF is active and turns on the auxiliary transistor 121 to connect the first buffer capacitor 161 and the second buffer capacitor 162.

The vertical scanning unit 30 may control the auxiliary signal DIFF for the auxiliary transistors 121.

The vertical scanning unit 30 can be configured to output a variable global bias voltage AMD and to pass the variable global bias voltage AMD to drains of the front stage amplifier transistors 118, and to drive the global bias voltage AMD with a lowered level during an initial phase of the readout waiting period.

The lowered level may be lower than the low level of the global bias voltage AMD in the pre-charge phases of the global operation period. The front stage amplifier transistor 118 can pass the lowered level global bias voltage AMD to the first electrode of the first buffer capacitor 161 oriented to the amplifier transistor 118. The potential at a node of the first buffer path between the first buffer capacitor 161 and the first buffer switch 163 decreases accordingly.

The lowered level can be sampled at the first electrode of the first buffer capacitor by using the global select signal SW in the initial phase such that the variable global bias voltage AMD can be increased for the rest of the readout waiting period. A gate induced drain leakage (GIDL) current in the first buffer switch 163 can be reduced provided that a suitable potential is applied to the sample node 170 in the readout waiting period.

The vertical scanning unit 30 can be configured to control the constant current source 350 to apply a lowered signal level to the current source capacitors 351 in the readout waiting period.

The lowered signal level passed to the current source capacitors 351 can be lower than a voltage at the lower end of voltage ramps passed to the current source capacitors 351 in the global operation periods. When the lowered voltage level is applied in a configuration with an auxiliary transistor 121, the potential at the node between the second buffer capacitor 162 and the second buffer switch 164 may decrease accordingly. GIDL current in the second buffer switch 164 can be reduced provided that a suitable potential is applied to the sample node 170 in the readout waiting period.

FIG. 7 shows the timing of the variable global bias voltage AMD applied to the drains of the front stage amplifier transistors 118.

The global bias voltage AMD is transmitted to all pixel circuits 100 simultaneously. In the illustrated embodiment, the global bias voltage AMD changes between four different voltage levels, a low level, a lower medium level, a higher medium level, and a high level.

In the global operating period, the global bias voltage AMD changes between the lower medium level in pre-charge phases and the high level in ramp phases following the pre-charge phases. In the pre-charge phases, the front stage amplifier transistors 118 are on and pass the lower medium level to the transfer nodes 120 to set the transfer nodes 120 to the lower medium level. In the immediately following reset and data phases, the global bias voltage AMD changes to the high level and the front stage amplifier transistor 118, which is in a high-efficiency source follower configuration, efficiently charges the transfer node 120 to the data signal level and the reset signal level.

Outside the global operating period, the global bias voltage AMD has the low level in an initial phase of the readout waiting period and a higher medium level in the rest of the readout waiting period and during the entire row readout period. The low level in the initial phase can be latched to the transfer node 120 by controlling the front stage select transistor 119. In combination with a suitable charged sample node 170, the latched low level reduces the GIDL current in the first buffer switch 163 of FIG. 6.

FIG. 8 shows an AMD buffer circuit 380 for a bias source signal AMD_IN supplied, e.g., by the vertical scanning circuit 30 of FIG. 4. The AMD buffer circuit 380 outputs the buffered global bias voltage AMD on an AMD conductor 381. The AMD conductor 381 includes a plurality of AMD column sections 382, wherein each AMD column section 382 runs parallel to a pixel column and is connected to all pixel circuits 100 of the pixel column. FIG. 9 shows the timing of the variable auxiliary voltage VRG applied to the drain of the post stage reset transistors 165.

The auxiliary voltage VRG is transmitted to all pixel circuits simultaneously. In the illustrated embodiment, the auxiliary voltage VRG changes between a low level and a high level.

The auxiliary voltage VRG has the low level in the initial phase of the readout waiting period and the high level in the rest of the readout waiting period, during the entire row readout period, and during the entire global operating mode. The low level in the initial phase can be latched to the sample node 170 by controlling the post stage reset transistor 165 to reduce, in combination with a suitable charged transfer node 120, the leakage in the first buffer switch 163 and the second buffer switch 164 of FIG. 6. The higher level in the global operation period may contribute to reducing the voltage stress for the first and second buffer capacitors 161, 162 of FIG. 6.

FIG. 10 shows a VRG buffer circuit 390 for an auxiliary source signal VRG IN supplied, e.g., by the vertical scanning circuit 30 of FIG. 4. The VRG buffer circuit 390 outputs the buffered auxiliary voltage VRG on a VRG line 391. The VRG line 391 includes a plurality of VRG column sections 392, wherein each VRG column section 392 runs parallel to a pixel column and is connected to all pixel circuits 100 of the pixel column.

FIG. 11 shows the timing of the ramp signal RMP applied to an electrode of the current source capacitors 351 of FIG. 4. The ramp signal RMP is transmitted to all pixel circuits 100 simultaneously. In the illustrated embodiment, the ramp signal RMP changes between three different voltage levels, a low level, a medium level, and a high level.

In pre-charge phases of the global operating periods, the ramp signal has the high level. In the ramp phases of the reset phase and the data phase, the ramp signal falls linearly from the high level to the low level to sink the current on the other electrode of the current source capacitor. To reduce voltage stress for the current source capacitors, the high level should be about 0.3V higher than the reset level on the transfer node.

The low level in the readout waiting period reduces, in combination with a suitable voltage at the sample node 170, the leakage in the second buffer switch 164 of FIG. 6.

FIG. 12 shows a solid-state imaging device with the constant current source 350 including a switch circuit 360 electrically connected between an output of the voltage ramp circuit 352, first electrodes of the current source capacitors 351 and a reference potential VSS. The switch circuit 360 applies a ramp signal RMP output by the voltage ramp circuit 352 to the current source capacitors 351 at least in the global operation period and applies the reference potential VSS to the current source capacitors 351 in the readout waiting periods. The ramp signal RMP includes linear voltage ramps passed to the current source capacitors 351 in ramp phases ofthe global operation periods. In a configuration with an auxiliary transistor 121, the switch circuit 360 can apply a comparatively low voltage level like the reference potential VSS to the current source capacitors 351 in the readout waiting periods. The potential at the node in the second buffer path between the second buffer capacitor 162 and the second buffer switch 164 can decrease accordingly. GIDL current in the second buffer switch 164 can be reduced.

Selecting for the readout waiting periods appropriate voltage levels for the global bias voltage AMD, the variable auxiliary voltage VRG and the ramp signal RMP output by the voltage ramp circuit, the drain-to- source voltage of the first buffer switch 163 and the drain-to-source voltage of the second buffer switch 164 can be set to low values such that a leakage current between drain and source of the first buffer switch 163 and between drain and source of the second buffer switch 164 can be significantly reduced, independent from the voltage levels of the analog voltage signals buffered in the buffer capacitors 161, 162 of the voltage storage portion 160.

The illustrated embodiment shows a switch circuit 360 that includes first buffer switches 361 and second buffer switches 362. Each first buffer switch 361 is electrically connected between an output of the voltage ramp circuit 352 and a plurality of current source capacitors 351. Each second buffer switch 362 is electrically connected between the plurality of current source capacitors 351 and a reference potential VSS.

The plurality of current source capacitors 351 can include the current source capacitors of one or more complete pixel rows. The vertical scanning unit 30 controls the first buffer switches 361 through a first buffer switch control signal ASW1. The vertical scanning unit 30 controls the second buffer switches 362 through a second buffer switch control signal ASW2.

The constant current source 350 can include a buffer circuit 370 electrically connected between an output of the voltage ramp circuit 352 and the current source capacitors 351.

The buffer circuit 370 may include a plurality of p channel source followers 371. Each p channel source follower 371 is electrically connected between the output of the voltage ramp circuit 352 and a subset of the current source capacitors 351. Each p channel source follower 371 can be electrically connected between the output of the voltage ramp circuit 352 and the switch circuit 360.

Referring again to FIG. 6, the vertical scanning unit 30 can be configured to control the variable auxiliary potential VRG and to pass the variable auxiliary potential VRG to drains of the post stage reset transistors 165, wherein the vertical scanning unit 30 maintains the variable auxiliary potential VRG at a low level during an initial phase of the readout waiting period and at a high level at least in the global operation period.

The post stage reset transistor 165 passes the low voltage level to the sample node 170 in the initial phase of the readout waiting period. The post stage reset transistor 165 can be controlled to sample the low voltage level on the sample node 170 for the rest of the readout waiting period so that the auxiliary potential may be set to a higher voltage for a main phase of the readout waiting period following the initial phase.

Provided a suitable control of the potentials at the transfer node 120, the low voltage level at the sample node 170 can lower the voltages across the first buffer switch 163 and the second buffer switch 164, wherein the GIDL current in the first and second buffer switches 163, 164 can be reduced.

The variable auxiliary potential VRG is transmitted to all pixel circuits 100 simultaneously. In particular, the drains of the post stage reset transistors 165 are electrically connected to a VRG line 391 transmitting the variable auxiliary potential VRG to the pixel circuits 100. All pixel circuits 100 can be electrically connected to the same VRG line 391. The VRG line 391 can include a plurality of column sections, wherein each column section runs parallel to a pixel column and is connected to all pixel circuits 100 of the pixel column.

The voltage ramp circuit 352 generates a falling voltage ramp for each ramp phase to sink the source current of the front stage amplifier transistor. The voltage ramp circuit 352 may be based on an integrator driven by a constant current source. Alternatively, the voltage ramp circuit 352 can be implemented as a digital - to-analog converter generating a falling voltage ramp.

FIG. 13 shows the timing of the ramp signal RMP for a complete cycle including a global operation period, a readout waiting period, and a row readout period.

The following time diagrams show control signals and internal signals of the pixel circuit 100 of FIG. 6, wherein the variable auxiliary potential VRG, the ramp signal RMP and the global bias voltage AMD are controlled to minimize VDS leakage and GIDL as described with reference to FIG. 7, FIG. 9, and FIG. 13.

FIG. 14A and FIG. 14B show the global operating period. The pre-charge of the transfer node 120 through the lower medium level of the global bias voltage is started prior to the active pulse on the transfer signal TRG to ensure that the front stage amplifier transistor 118 turns on regardless of the data signal level.

FIG. 15A and FIG. 15B show the effects of the described control of the variable auxiliary potential VRG, the ramp signal RMP and the global bias voltage AMD for the readout waiting period, and FIG. 16A and FIG. 16B for the row readout period.

FIG. 17 shows the voltage VCR on a first node between the first buffer capacitor 161 and the first buffer switch 163 in the first buffer path and the voltage VCD on a second node between the second buffer capacitor 162 and the second buffer switch 164 in the second buffer path for the global operating period and the readout waiting period.

In order to obtain a low gate-to-drain voltage for the first buffer switch 163, the global bias voltage AMD is pulled down from 2.8V to 1.2V. The 1.2V are sampled at the transfer node 120 by turning off the front stage select transistor 119. In order to obtain a low gate-to-drain voltage for the second buffer switch 164, the ramp signal RMP voltage is pulled down from 1.2V to 0V, wherein the voltage V3 between the second buffer path and the current source capacitor 351 is reduced by 1.IN . The voltage VCR on the first node is about 0.8V and the voltage VCD on the second node is about 0.8V regardless of the illumination intensity, resulting in low GIDL currents for the first and second buffer transistors 163, 164.

FIG. 18 shows the voltage V2 on the sample node 170 in addition to the voltages VCR and VCD illustrated in FIG. 17. As described with reference to FIG. 17, the voltage VCR on the first node is about 0.8V and the voltage VCD on the second node is about 0.8V in the readout waiting period.

Pulling the variable auxiliary potential VRG to about 0.8V and sampling the auxiliary potential VRG on the sample node 170 by turning off the post stage reset transistor 165 sets the voltage V2 to about 0.8V for the readout waiting period. For both the first buffer transistor 163 and the second buffer transistor 164 the drain-to-source voltage is about 0V regardless of the data signal level. Drain-source leakage is reduced in both the first buffer transistor 163 and the second buffer transistor 164.

FIG. 19 is related to a solid-state imaging device that includes a DAC stage 358 with a plurality of switchable current supply cells 35-1, ..., 35-n connected in parallel and an output resistor 353. Each current supply cell 35-1, . . . , 35-n includes a cell current source 354-1, . . . , 354-n and a primary switching element 355-1, ... , 355-n connected in series. The output resistor 353 is connected between the parallel connected current supply cells 35-1, ... , 35-n and a first constant voltage VX1.

The parallel connected current supply cells 35-1, . . . , 35-n are connected in series between a second constant voltage VX2 and the output resistor 353. The first constant voltage VX1 may be the reference potential VSS and the second constant voltage VX2 may be the positive logic supply voltage VDD. Alternatively, the first constant voltage VX1 may be the positive logic supply voltage VDD and the second constant voltage VX2 may be the reference potential VSS.

When the primary switching element 355-x of a switchable current supply cell 35-x is on, the respective cell current source 354-x induces a current flow between the first constant voltage VX1 and the second constant voltage VX2 through the output resistor 353.

The current supply cells 35-1, ... , 35-n may include FETs with constant gate bias, may be essentially identical and may supply the same current. The primary switching elements 355-1, ..., 355-n may be FETs. Switch control signals SW1, ...., SWn control the primary switching elements 355-1, ... , 355-n and turn on selected ones . The switch control signals SW 1 , . . . . , SWn control the current supply cells 35 - 1 , ..., 35-n in a way that the sum current through the output resistor 353 continuously decreases with time in steps at a step height corresponding to the voltage drop, one single of the cell current sources 354-1, ..., 354-n generates at the output resistor 353. For example, a counter supplying the switch control signals SW1, ... ., SWn may count backwards. In the DAC stage 358 illustrated in FIG. 20, each switchable current cell 35-1, ... , 35-n further includes a secondary switching element 356-1, ... , 356-n connected in series between the cell current source 354- 1, . . . , 354-n and the reference potential VSS. The inverted switch control signals SW1. . . . , SWn control the secondary switching elements 356-1, ... , 356-n and turn on selected ones such that during operation each cell current source 354-1, ... , 354-n supplies the same current at any time and the total current consumption remains constant.

The illustrated DAC stages 358 refer to a ground-based type DAC stage, wherein the first constant voltage is equal to the reference potential VSS and the second constant voltage is equal to a positive logic supply voltage VDD. According to a DAC stage of the supply-based type, the switchable current cells 35-1, ... , 35-n may be connected to the reference potential VSS and the output resistor 353 may be connected to the positive logic supply voltage VDD.

FIG. 21 shows a voltage ramp circuit 352 that includes a counter 359 controlling the switchable current supply cells 35-1, ..., 35-n of any of the DAC stages 358 in FIG. 19 or FIG. 20. The counter 359 may be a binary counter, decreasing a digital count value with each rising or trailing edge of a clock signal and outputting the current digital count value in parallel at data outputs DO, . . . , Dn-1. The data outputs DO, . . . , Dn-1 supply the switch control signals SW1, ... ., SWn.

FIG. 22 is a perspective view showing an example of a laminated structure of a solid-state imaging device 23020 with a plurality of pixels arranged matrix-like in array form. Each pixel includes a pixel circuit with at least one photoelectric conversion element.

The solid-state imaging device 23020 has the laminated structure of a first chip (upper chip) 910 and a second chip (lower chip) 920. The laminated first and second chips 910, 920 may be electrically connected to each other through TC(S)Vs (Through Contact (Silicon) Vias) formed in the first chip 910. The solid- state imaging device 23020 may be formed to have the laminated structure in such a manner that the first and second chips 910 and 920 are bonded together at wafer level and cut out by dicing.

In the laminated structure of the upper and lower two chips, the first chip 910 may be an analog chip (sensor chip) including at least one analog component of each pixel circuit, e.g., the photoelectric conversion elements arranged in array form.

For example, the first chip 910 may include only the photoelectric conversion elements of the pixel circuits as described above with reference to the preceding FIGS. Alternatively, the first chip 910 may include further elements of each pixel circuit. For example, the first chip 910 may include, in addition to the photoelectric conversion elements, some or all elements of the radiation sensitive portions. Alternatively, the first chip 910 may include each element of the pixel circuit. In addition to the elements of the pixel circuits, the first chip 910 may include an element of the constant current source as described above.

The second chip 920 may be mainly a logic chip (digital chip) that includes the elements complementing the elements on the first chip 910 to complete pixel circuits and a complete constant current source. The second chip 920 may also include analog circuits, for example circuits that quantize analog signals transferred from the first chip 910 through the TCVs. For example, the second chip 920 may include all or at least some of the components of the constant current source as described with reference to the preceding Figures.

The second chip 920 may have one or more bonding pads BPD and the first chip 910 may have openings OPN for use in wire-bonding to the second chip 920. The solid-state imaging device 23020 with the laminated structure of the two chips 910, 920 may have the following characteristic configuration:

The electrical connection between the first chip 910 and the second chip 920 is performed through, for example, the TCVs. The TCVs may be arranged at chip ends or between a pad region and a circuit region. The TCVs for transmitting control signals and supplying power may be mainly concentrated at, for example, the four comers of the solid-state imaging device 23020, by which a signal wiring area of the first chip 910 can be reduced.

The technology according to the present disclosure may be realized in a light receiving device mounted in a mobile body of any type such as automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility, airplane, drone, ship, or robot.

FIG. 23 shows a TCV 915 passing the analog voltage signals driven by the front stage amplifier circuit 118 from the radiation sensitive portion 110 to the voltage storage portion 160. The voltage storage portion 160 is completely formed in the second chip 920. The current source capacitor 351 is formed in the second chip 920.

FIG. 24 to FIG. 28 show other pixel circuits to which the present invention can be applied, wherein the current source capacitor is indicated by the reference sign CRMP.

FIG. 29 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in FIG.294, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound/image output section 12052, and a vehiclemounted network interface (I/F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 imaging an image of the outside of the vehicle and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section 12031 may be or may include a solid-state imaging device with GS pixel circuits having a radiation sensitive portion, a voltage storage portion and a capacitive current source as active load for a front stage amplifier transistor passing analog voltage signals from the radiation sensitive portion to the voltage storage portion according to the embodiments of the present disclosure. The light received by the imaging section 12031 may be visible light or may be invisible light such as infrared rays or the like.

The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle and may be or may include a solid-state imaging device with GS pixel circuits according to the embodiments of the present disclosure. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that includes the solid-state imaging device and that is focused on the driver. On the basis of detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in- vehicle information detecting unit 12040 and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

In addition, the microcomputer 12051 can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of the information about the outside of the vehicle which information is obtained by the outside vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

The sound/image output section 12052 transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of FIG. 29an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display or a head-up display, wherein each of them may include a solid- state imaging device with CS pixel circuits using a capacitive current source as described with reference to the preceding Figures.

FIG. 30 is a diagram depicting an example of the installation position of the imaging section 12031, wherein the imaging section 12031 may include imaging sections 12101, 12102, 12103, 12104, and 12105.

The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, side-view mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side view mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally, FIG. 30 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the side view mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, imaging element having pixels for phase difference detection or may include a ToF module based on GS pixel circuits using a capacitive current source for transmitting analog voltage signals from the radiation sensitive portion to the voltage storage portion according to the present disclosure.

For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km/hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound/image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound/image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying a solid-state imaging device with GS pixel circuits with a ramp generator circuit according to the present disclosure, the results of image recognition can be more reliable. For example, recognition of pedestrians can be performed on more reliable pixel information. A faulty image sensor can be reliably detected and reported to a higher instance.

Additionally, embodiments of the present technology are not limited to the above-described embodiments, but various changes can be made within the scope of the present technology without departing from the gist of the present technology.

A solid-state imaging device including GS pixel circuits using a capacitive current source for transmitting analog voltage signals from the radiation sensitive portion to the voltage storage portion according to the present disclosure may be any device used for analyzing and/or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, the solid-state imaging device may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like.

Specifically, in the field of image reproduction, the solid-state imaging device may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, the solid-state imaging device may be integrated in an in-vehicle sensor that captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like.

In the field of home appliances, the solid-state imaging device may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly, the solid-state imaging device may be integrated in home appliances such as TV receivers, refrigerators, and air conditioners and/or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the solid-state imaging device may be integrated in any type of sensor provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light. In the field of security, the solid-state imaging device can be integrated in a device provided for use in security, such as a monitoring camera for crime prevention or a camera for person authentication use. Furthermore, in the field of beauty, the solid-state imaging device can be used in a device provided for use in beauty, such as a skin measuring instrument that captures skin or a microscope that captures a probe. In the field of sports, the solid-state imaging device can be integrated in a device provided for use in sports, such as an action camera or a wearable camera for sport use or the like. Furthermore, in the field of agriculture, the solid-state imaging device can be used in a device provided for use in agriculture, such as a camera for monitoring the condition of fields and crops.

The present technology can also be configured as described below:

[1] A solid-state imaging device (90), including: a pixel circuit (100) including a radiation sensitive portion (110), a front stage amplifier transistor (118) and a voltage storage portion (160); and a constant current source (350), the constant current source (350) and the front stage amplifier transistor (118) forming a source follower configured to pass an analog voltage signal with a voltage level related to an intensity of detected radiation from the radiation sensitive portion (110) to the voltage storage portion (160) in a global operation period, wherein a constant current delivered by the constant current source (350) is a capacitor charging current.

[2] The solid-state imaging device according to [1], wherein the constant current source (350) includes a current source capacitor (351) for each pixel circuit (100) and a voltage ramp circuit (352), wherein the current source capacitor (351) is electrically connected between a source of the front stage amplifier transistor (118) of the pixel circuit (100) and an output of the voltage ramp circuit (352), and wherein the voltage ramp circuit (352) is configured to supply a linear voltage ramp to the current source capacitors (351) in ramp phases of the global operation period.

[3] The solid-state imaging device according to any of [1] and [2], further including: a vertical scanning unit (30) configured to output a variable global bias voltage AMD and to pass the variable global bias voltage AMD to drains of the front stage amplifier transistors (118).

[4] The solid-state imaging device according to [3], wherein the vertical scanning unit (30) is configured to change, in the global operation period, the global bias voltage AMD between a low level in pre-charge phases and a high level outside the pre-charge phases.

[5] The solid-state imaging device according to any of [3] and [4], wherein the voltage storage portion (160) is configured to pass a pixel signal obtained from the analog voltage signal to a data signal line (19) in a row readout period, and wherein the vertical scanning unit (30) is configured to drive the global bias voltage AMD at a medium level in the row readout period.

[6] The solid-state imaging device according to any of [1] to [5], wherein the voltage storage portion (160) includes a first buffer path and a second buffer path, the first buffer path including a first buffer capacitor (161) and a first buffer switch (163) electrically connected in series, the second buffer path including a second buffer capacitor (162) and a second buffer switch (164) electrically connected in series, the first buffer path and the second buffer path electrically connected in parallel between a transfer node (120) and a sample node (170), and wherein the transfer node (120) is formed between the front stage amplifier transistor (118) and the current source capacitor (351) of the pixel circuit (100).

[7] The solid-state imaging device according to [6], further including: an auxiliary transistor (121) configured to separate the first buffer capacitor (161) and the second buffer capacitor (162) in a readout waiting period following the global operation period.

[8] The solid-state imaging device according to any of [6] and [7], further including: an auxiliary transistor (121) electrically connected between a first electrode of the first buffer capacitor (161) and a first electrode of the second buffer capacitor (162), wherein the auxiliary transistor (121) is configured such that an auxiliary signal DIFF applied to a gate of the auxiliary transistor (121) turns off the auxiliary transistor (121) in a readout waiting period following the global operation period.

[9] The solid-state imaging device according to any of [7] and [8], further including: a vertical scanning unit (30) configured to output a variable global bias voltage AMD and to pass the variable global bias voltage AMD to drains of the front stage amplifier transistors (118), wherein the vertical scanning unit (30) is configured to drive the global bias voltage AMD at a lowered level during an initial phase of the readout waiting period.

[10] The solid-state imaging device according to any of [7] to [9], further including: a vertical scanning unit (30) configured to control the constant current source (350) to apply a lowered signal level to the current source capacitors (351) in the readout waiting period.

[11] The solid-state imaging device according to [10], wherein the constant current source (350) includes a switch circuit (360) electrically connected between an output of the voltage ramp circuit (352), first electrodes of the current source capacitors (351) and a reference potential VSS, wherein the switch circuit (360) applies a ramp signal RMP output by the voltage ramp circuit (352) to the current source capacitors (351) at least in the global operation period, and applies the reference potential VSS to the current source capacitors (351) in the readout waiting period.

[12] The solid-state imaging device according to [11], wherein the switch circuit (360) includes first buffer switches (361) and second buffer switches (362), each first buffer switch (361) electrically connected between an output of the voltage ramp circuit (352) and a plurality of current source capacitors (351), each second buffer switch (362) electrically connected between the plurality of current source capacitors (351) and a reference potential VSS.

[13] The solid-state imaging device according to any of [11] and [12], wherein the constant current source (350) includes a buffer circuit (370) electrically connected between an output of the voltage ramp circuit (352) and the current source capacitors (351). [14] The solid-state imaging device according to any of any of [6] to [13], wherein the voltage storage portion (160) includes a post stage amplifier transistor (168) configured to output a pixel signal on a data signal line (19), wherein a voltage level of the pixel signal is related to the analog voltage signal passed to the voltage storage portion (160).

[15] The solid-state imaging device according to any of [6] to [14], wherein the voltage storage portion (160) includes a post stage reset transistor (165) configured to temporarily connect the sample node (170) to a variable auxiliary potential VRG.

[16] The solid-state imaging device according to [15], further including: a vertical scanning unit (30) configured to control the variable auxiliary potential VRG and to pass the variable auxiliary potential VRG to drains of the post stage reset transistors (165), wherein the vertical scanning unit (30) is configured to maintain the variable auxiliary potential VRG at a low level during an initial phase of the readout waiting period and at a high level at least in the global operation period.

[17] The solid-state imaging device according to any of [2] to [16], wherein the voltage ramp circuit (352) includes a plurality of switchable current supply cells (35-1, . . . , 35-n) connected in parallel and an output resistor (353), wherein each current supply cell (35-1, . . . , 35-n) includes a cell current source (354-1, . . . , 354-n) and a primary switching element (355-1, ... , 355-n) connected in series, and wherein the output resistor (353) is connected between the parallel connected current supply cells (35-1, ... , 35-n) and a constant voltage.

Claims

1. A solid-state imaging device, comprising: a pixel circuit comprising a radiation sensitive portion, a front stage amplifier transistor and a voltage storage portion; and a constant current source, the constant current source and the front stage amplifier transistor forming a source follower configured to pass an analog voltage signal with a voltage level related to an intensity of detected radiation from the radiation sensitive portion to the voltage storage portion in a global operation period, wherein a constant current delivered by the constant current source is a capacitor charging current.

2. The solid-state imaging device according to claim 1, wherein the constant current source comprises a current source capacitor for each pixel circuit and a voltage ramp circuit, wherein the current source capacitor is electrically connected between a source of the front stage amplifier transistor of the pixel circuit and an output of the voltage ramp circuit, and wherein the voltage ramp circuit is configured to supply a linear voltage ramp to the current source capacitors in ramp phases of the global operation period.

3. The solid-state imaging device according to claim 1, further comprising: a vertical scanning unit configured to output a variable global bias voltage and to pass the variable global bias voltage to drains of the front stage amplifier transistors.

4. The solid-state imaging device according to claim 3, wherein the vertical scanning unit is configured to change, in the global operation period, the global bias voltage between a low level in pre-charge phases and a high level outside the pre-charge phases.

5. The solid-state imaging device according to claim 3, wherein the voltage storage portion is configured to pass a pixel signal obtained from the analog voltage signal to a data signal line in a row readout period, and wherein the vertical scanning unit is configured to drive the global bias voltage at a medium level in the row readout period.

6. The solid-state imaging device according to claim 1, wherein the voltage storage portion comprises a first buffer path and a second buffer path, the first buffer path comprising a first buffer capacitor and a first buffer switch electrically connected in series, the second buffer path comprising a second buffer capacitor and a second buffer switch electrically connected in series, the first buffer path and the second buffer path electrically connected in parallel between a transfer node and a sample node, and wherein the transfer node is formed between the front stage amplifier transistor and the current source capacitor of the pixel circuit.

7. The solid-state imaging device according to claim 6, further comprising: an auxiliary transistor configured to separate the first buffer capacitor and the second buffer capacitor in a readout waiting period following the global operation period.

8. The solid-state imaging device according to claim 6, further comprising: an auxiliary transistor electrically connected between a first electrode of the first buffer capacitor and a first electrode of the second buffer capacitor, wherein the auxiliary transistor is configured such that an auxiliary signal applied to a gate of the auxiliary transistor turns off the auxiliary transistor in a readout waiting period following the global operation period.

9. The solid-state imaging device according to claim 7, further comprising: a vertical scanning unit configured to output a variable global bias voltage and to pass the variable global bias voltage to drains of the front stage amplifier transistors, wherein the vertical scanning unit is configured to drive the global bias voltage at a lowered level during an initial phase of the readout waiting period.

10. The solid-state imaging device according to claim 7, further comprising: a vertical scanning unit configured to control the constant current source to apply a lowered signal level to the current source capacitors in the readout waiting period.

11. The solid-state imaging device according to claim 10, wherein the constant current source comprises a switch circuit electrically connected between an output of the voltage ramp circuit, first electrodes of the current source capacitors and a reference potential, wherein the switch circuit applies a ramp signal output by the voltage ramp circuit to the current source capacitors at least in the global operation period, and applies the reference potential to the current source capacitors in the readout waiting period.

12. The solid-state imaging device according to claim 11, wherein the switch circuit comprises first buffer switches and second buffer switches, each first buffer switch electrically connected between an output of the voltage ramp circuit and a plurality of current source capacitors, each second buffer switch electrically connected between the plurality of current source capacitors and a reference potential.

13. The solid-state imaging device according to claim 11, wherein the constant current source comprises a buffer circuit electrically connected between an output of the voltage ramp circuit and the current source capacitors.

14. The solid-state imaging device according to claim 6, wherein the voltage storage portion comprises a post stage amplifier transistor configured to output a pixel signal on a data signal line, wherein a voltage level of the pixel signal is related to the analog voltage signal passed to the voltage storage portion.

15. The solid-state imaging device according to claim 6, wherein the voltage storage portion comprises a post stage reset transistor configured to temporarily connect the sample node to a variable auxiliary potential.

16. The solid-state imaging device according to the claim 15, further comprising: a vertical scanning unit configured to control the variable auxiliary potential and to pass the variable auxiliary potential to drains of the post stage reset transistors, wherein the vertical scanning unit is configured to maintain the variable auxiliary potential at a low level during an initial phase of the readout waiting period and at a high level at least in the global operation period.

17. The solid-state imaging device according to claim 2, wherein the voltage ramp circuit comprises a plurality of switchable current supply cells connected in parallel and an output resistor, wherein each current supply cell comprises a cell current source and a primary switching element connected in series, and wherein the output resistor is connected between the parallel connected current supply cells and a constant voltage.