EP4659341A1 - Multiple power management integrated circuits (pmics) with shared output - Google Patents

Abstract

Multiple power management integrated circuits (PMICs) with a shared output are disclosed. More particularly, two or more PMICs are capable of producing a shared output while balancing currents provided by the PMICs in spite of device and component mismatches and part-to-part variations. This balance is achieved by giving each PMIC a current feedback loop and a shared voltage loop when multiple PMICs are active. When only a single PMIC is active, switches disable the shared voltage feedback loop and enable a local voltage feedback loop. Using multiple PMICs enables provision of higher supply voltages to power amplifiers in transmission chains to meet the demands of emerging wireless standards while also maintaining better efficiency for the transmission chain.

Description

MULTIPLE POWER MANAGEMENT INTEGRATED CIRCUITS (PMICS) WITH SHARED OUTPUT

PRIORITY APPLICATION

[0001] This application claims the benefit of U.S. Provisional Patent Application Serial Number 63/482,664, filed on February 1, 2023, entitled, “MULTIPLE POWER MANAGEMENT INTEGRATED CIRCUITS (PMICS) WITH SHARED OUTPUT,” the disclosure of which is hereby incorporated herein by reference in its entirety.

BACKGROUND

I. Field of the Disclosure

[0002] The technology of the disclosure relates generally to power management integrated circuits (PMICs) and, more particularly, to systems with multiple PMICs having an optionally shared output.

II. Background

[0003] Computing devices abound in modern society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences. With the advent of the myriad functions available to such devices, there has been increased pressure to find ways to reduce power consumption. One way that power consumption has been reduced is to put power management integrated circuits (PMICs) or other power converters in the transmission chain to assist in providing an optimized supply voltage to power amplifiers in the transmission chain. While traditional PMICs have enabled envelope tracking and average power tracking type supply voltage control, more recent generations of technologies are placing additional burdens on the PMICs, and these additional burdens provide room for innovation. SUMMARY

[0004] Aspects disclosed in the detailed description include multiple power management integrated circuits (PMICs) with a shared output. More particularly, exemplary aspects of the present disclosure contemplate two or more PMICs capable of producing a shared output while balancing currents provided by the PMICs in spite of device and component mismatches and part-to-part variations. This balance is achieved by giving each PMIC a current feedback loop and a shared voltage loop when multiple PMICs are active. When only a single PMIC is active, switches disable the shared voltage feedback loop and enable a local voltage feedback loop. Using multiple PMICs enables the provision of higher supply voltages to power amplifiers in transmission chains to meet the demands of emerging wireless standards while also maintaining better efficiency for the transmission chain.

[0005] In this regard in one aspect, a multi-PMIC system is disclosed. The multi- PMIC system comprises a first PMIC configured to receive a target voltage and generate a first output signal. The multi-PMIC system also comprises a second PMIC configured to receive the target voltage and generate a second output signal. The multi-PMIC system also comprises an output node coupled to the first PMIC and the second PMIC and summing the first output signal and the second output signal to form a combined signal. The multi-PMIC system also comprises a first current feedback loop configured to measure a first current of the first output signal and provide a first feedback signal to the first PMIC. The multi-PMIC system also comprises a second current feedback loop configured to measure a second current of the second output signal and provide a second feedback signal to the second PMIC. The multi-PMIC system also comprises a common voltage feedback loop coupling the output node to the first PMIC and the second PMIC and configured to provide a voltage measurement from the output node to the first PMIC and the second PMIC.

[0006] In this regard, in another aspect, a mobile communication device is disclosed. The mobile communication device includes a transceiver comprising a multiple PMIC (multi-PMIC) system comprising a first PMIC configured to receive a target voltage and generate a first output signal, a second PMIC configured to receive the target voltage and generate a second output signal, and an output node coupled to the first PMIC and the second PMIC and summing the first output signal and the second output signal to form a combined signal. The transceiver also comprising a first current feedback loop configured to measure a first current of the first output signal and provide a first feedback signal to the first PMIC, a second current feedback loop configured to measure a second current of the second output signal and provide a second feedback signal to the second PMIC, and a common voltage feedback loop coupling the output node to the first PMIC and the second PMIC and configured to provide a voltage measurement from the output node to the first PMIC and the second PMIC.

[0007] In this regard, in another aspect, a method of managing power in a power amplifier is disclosed. The method includes receiving, at a first PMIC, a target voltage from a remote location, generating a first output signal responsive to receiving the target voltage, receiving, at a second PMIC, the target voltage, and generating a second output signal responsive to receiving the target voltage. The method also includes summing the first output signal and the second output signal to form a combined signal, measuring a first current of the first output signal, providing a first feedback signal to the first PMIC based on the first current, measuring a second current of the second output signal, providing a second feedback signal to the second PMIC based on the second current, and providing a voltage measurement based on the combined signal to the first PMIC and the second PMIC.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a hybrid circuit and block diagram of a conventional multiple power management integrated circuit (PMIC) (multi-PMIC) system having a shared output and unbalanced current flows;

[0009] Figure 2 is a hybrid circuit and block diagram of a multi-PMIC system having a shared output with balanced current flows according to an exemplary aspect of the present disclosure;

[0010] Figure 3 is a more detailed diagram of the multi-PMIC system of Figure 2 with some of the switching paths presented as well as more details on the control circuit, which help prevent concurrent peak current draws by the multiple current paths;

[0011] Figure 4 is a hybrid circuit and block diagram of a quadrature multi-PMIC system having a shared output with balanced current flows according to another exemplary aspect of the present disclosure; [0012] Figure 5 is a more detailed diagram of the multi-PMIC system of Figure 2 with an alternate switching arrangement for the shared voltage feedback loop;

[0013] Figure 6 is a more detailed diagram of the multi-PMIC system of Figure 2 with dummy switches in the voltage feedback loops to help provide balanced voltage levels from the different PMICs;

[0014] Figure 7 is a more detailed diagram of the multi-PMIC system of Figure 2, where the PMICs use different clocks and are controlled through a tandem circuit to prevent concurrent peak current draws by the multiple current paths;

[0015] Figure 8A is a more detailed diagram of the multi-PMIC system of Figure 2, showing current flows being limited to one of the PMICs by a tandem circuit;

[0016] Figure 8B is a counterpart to Figure 8A, with the current flows being limited to another one of the PMICs by the tandem circuit;

[0017] Figure 8C is a current versus time diagram showing how the current flows in Figures 8A and 8B are toggled so as to prevent concurrent peak current draws by the multiple current paths; and

[0018] Figure 9 is a block diagram of a transceiver such as may be present in a mobile terminal and include a transmission chain with a multi-PMIC system according to exemplary aspects of the present disclosure.

DETAILED DESCRIPTION

[0019] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0020] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

[0021] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0022] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0025] Aspects disclosed in the detailed description include multiple power management integrated circuits (PMICs) with a shared output. More particularly, exemplary aspects of the present disclosure contemplate two or more PMICs capable of producing a shared output while balancing currents provided by the PMICs in spite of device and component mismatches and part-to-part variations. This balance is achieved by giving each PMIC a current feedback loop and a shared voltage loop when multiple PMICs are active. When only a single PMIC is active, switches disable the shared voltage feedback loop and enable a local voltage feedback loop. Using multiple PMICs enables provision of higher supply voltages to power amplifiers in transmission chains to meet the demands of emerging wireless standards while also maintaining better efficiency for the transmission chain.

[0026] Before addressing exemplary aspects of the present disclosure, a brief overview of existing multi-PMIC systems is provided with reference to Figure 1 along with a discussion of the shortcomings thereof. Discussion of exemplary aspects of the present disclosure begins below with reference to Figure 2.

[0027] Within a mobile terminal such as a cellular phone, a PMIC may generally offer output currents up to 1.5 amperes (A). However, with emerging phone architectures, larger currents such as 2.5 A or even 3.0 A may be needed. While a single PMIC may be created that is capable of creating such higher currents, such a monolithic approach is impractical given current size constraints and current battery limitations in mobile terminals. Accordingly, achieving such higher currents may be done by combining outputs from multiple PMICs.

[0028] In this regard, Figure 1 is a hybrid circuit and block diagram of a conventional multi-PMIC system 100. The multi-PMIC system 100 includes a first PMIC 102 and a second PMIC 104. While the term PMIC is used throughout, it should be appreciated that a PMIC is a form of a direct current (DC)-to-DC (DC-DC) converter. Exemplary DC-DC converters are buck converters, boost converters, buck-boost, and the like. The first PMIC 102 produces a first output current loutl that passes through a first effective series resistance (ESRI) 106 and is filtered by a first inductor (Loutl) 108 and a first capacitor (Coutl) 110 to provide a voltage at a first node 112. The first node 112 is coupled to an output node 114 through a first switch 116. The first node 112 is also coupled to the first PMIC 102 through a first voltage feedback loop 118.

[0029] Similarly, the second PMIC 104 produces a second output current Iout2 that passes through a second effective series resistance (ESR2) 120 and is filtered by a second inductor (Lout2) 122 and a second capacitor (Cout2) 124 to provide a voltage at a second node 126. The second node 126 is coupled to the output node 114 through a second switch 128. The second node 126 is also coupled to the second PMIC 104 through a second voltage feedback loop 130.

[0030] The currents from the first PMIC 102 and the second PMIC 104 are combined at the output node 114 and may be provided to an element such as a power amplifier or the like that needs higher currents than a typical single PMIC (i.e., given contemporaneous size and battery constraints) could otherwise provide. However, process variations in the circuitry forming the PMICs 102, 104, tolerance variations in the ESRI 106, ESR2 120, Loutl 108, Lout2 122, Coutl 110, and/or Cout2 124 may all contribute to sizable current mismatches between the two current paths. When there is a current mismatch of this sort, there may be additional strain put on the PMIC providing more current and inefficiencies are generated within the system. Even if the currents are matched, it is possible that all the PMICs in a multi-PMIC system may draw current from a shared battery concurrently. This peak in current draw from the battery may compromise performance or require worst case engineering which also adds to inefficiencies.

[0031] Exemplary aspects of the present disclosure add independent current feedback loops to the current paths of the multiple PMICs while providing a shared voltage feedback loop. The shared voltage feedback loop helps ensure that the desired supply voltage is generated at the output node, while the individual current feedback loops help regulate the currents to compensate for mismatches in the current paths. Variations on this concept include turning on and off a voltage feedback loop for the additional PMICs depending on whether a summed current is being generated or only a single PMIC is being used. A further variation is the use of a tandem circuit to manage which PMIC is drawing current from the battery at a given time to help prevent concurrent peak current draws from multiple PMICs. [0032] In this regard, Figure 2 is a hybrid circuit and block diagram of a multi-PMIC system 200 having a shared output node 202 with balanced current flows according to an exemplary aspect of the present disclosure. In particular, the multi-PMIC system 200 includes a first PMIC 204 and a second PMIC 206. The first PMIC 204 provides an output signal that passes through a filter 208 formed from a first inductor (Loutl) 210 and a first capacitor (Coutl) 212 to the output node 202 through a first switch 214. A current detector 216 measures current across the first inductor 210 to provide a first current feedback loop 218 for the first PMIC 204.

[0033] Similarly, the second PMIC 206 provides an output signal that passes through a second filter 220 formed from a second inductor (Lout2) 222 and a second capacitor (Cout2) 224 to the output node 202 through a second switch 226. A second current detector 228 measures current across the second inductor 222 to provide a second current feedback loop 230 for the second PMIC 206. A single voltage measurement is made at a node 232, which, when the switches 214 and 226 are closed, is a common voltage node relative to the output node 202. The measurement from the node 232 is passed back to both the first PMIC 204 and the second PMIC 206 as a common voltage feedback loop 234. This voltage feedback may be compared to a target voltage (Vtarget) to drive the PMICs 204, 206 to provide the desired output voltage. Meanwhile, the current feedback loops are used to balance current loads between the two PMICs 204, 206.

[0034] While not shown in Figure 2 and the subsequent figures, it should be appreciated that the filters 208 and 220 may include ESRs as described above in reference to Figure 1. However, the ESR is omitted for simplicity.

[0035] As might be expected, there are a variety of ways in which the loops may be implemented. In this regard, Figure 3 is a more detailed diagram of the multi-PMIC system 200 of Figure 2 with some of the switching paths presented as well as more details on the control circuit which help prevent concurrent peak current draws by the multiple current paths. In particular, a control circuit 300 may be coupled to the PMICs 204 and 206 as well as to switches 214, 226, 302, and 304. The common voltage feedback loop 234 of Figure 2 is actually a first voltage feedback loop 306 and a second voltage feedback loop 308.

[0036] In a first mode controlled by the control circuit 300, the first PMIC 204 may operate as an individual converter and the second PMIC 206 may be off. Thus, the control circuit 300 may drive the switch 214 to an output node (outl) 310. The switch 214 may be a single pole, dual throw (SPDT) switch. Concurrently, the switch 226 may be open, decoupling the second PMIC 206 from any output node. Likewise, the switch 302 may be closed, and the switch 304 may be open, decoupling the first voltage feedback loop 306 from the second voltage feedback loop 308.

[0037] In a second mode controlled by the control circuit 300, the second PMIC 206 may operate as an individual converter, and the first PMIC 204 may be off. Thus, the control circuit 300 may drive the switch 226 to an output node (out2) 312. The switch 226 may likewise be a SPDT switch. Concurrently, the switch 214 may be open, decoupling the first PMIC 204 from any output node 202, 310, 312. Likewise, the switch 302 may be closed and the switch 304 may be open, decoupling the second voltage feedback loop 308 from the first voltage feedback loop 306.

[0038] In a third mode, and of more interest to the present disclosure, the PMICs 204, 206 may combine to provide a summed output. Thus, the control circuit 300 may drive both switches 214, 226 to the output node 202. The switch 302 is open and the switch 304 is closed so that the second voltage feedback loop 308 is disabled, but both comparators 314 and 316 receive the same voltage signal from node 318. The comparators 314 and 316 compare the voltage signal from the node 318 to respective current signals and drive the PMICs accordingly.

[0039] The control circuit 300 also includes a tandem circuit 320, which works with state machines 322, 324 and a common clock signal 326. The tandem circuit 320 manipulates the state machines 322, 324 such that only one PMIC 204, 206 draws current from the battery at a time. For example, the first PMIC 204 may draw on even cycles and the second PMIC 206 may draw on odd cycles (or vice versa). A better illustration of this concept is provided below with reference to Figures 8A-8C.

[0040] While the above discussion has mentioned that these are multiple PMIC systems, the above figures only show two PMICs. It should be appreciated that the concepts of the present disclosure are scalable to more than two PMICs. One such more than two PMIC system is shown in Figure 4 by a quadrature multi-PMIC system 400 having four PMICs 402(1 )-402(4). Each PMIC 402(l)-402(4) has a respective filter 404(l)-404(4) including respective inductors 406(l)-406(4) and capacitors 408(1)- 408(4). Switches 410(l)-410(4) couple the PMICs 402(l)-402(4) to a common output node 412. Current detectors 414(1)-414(4) are associated with the respective inductors 406(l)-406(4) and provide current feedback loops 416(1)-416(4) while a single voltage feedback loop 418 is shared by the PMICs 402(l)-402(4). A control circuit 420 operates to control the switches 410(l)-410(4) as well as the various switches (not shown) which enable and disable various independent voltage feedback loops. Likewise, the control circuit 420 may also include a tandem circuit (not shown in Figure 4) that controls activation of the PMICs 402(l)-402(4) in such a manner that concurrent draws on the battery are avoided or minimized.

[0041] While the switching arrangement of Figure 3 is one option, there are other possible switching arrangements for the multi-PMIC system 200. Thus, Figure 5 provides a more detailed diagram of the multi-PMIC system 200 with an alternate switching arrangement for the shared voltage feedback loop. In particular, the switches 302, 304 are combined into one SPDT switch 500, which allows the input to the comparator 316 to be from the voltage feedback loop 306 or the voltage feedback loop 308 as dictated by the mode being used.

[0042] It should also be appreciated that the presence of a switch, whether it be switches 302, 304, or switch 500 may introduce a non-trivial resistance in one branch of the common voltage feedback loop 234 that is not present in the other branch. Such extra resistance may create different values in the inputs of the comparators 314, 316 such that it may be argued that the comparators 314, 316 are no longer using the same values to assist in balancing. While it may be possible to create a switch large enough to reduce the resistance to a trivial level, such a solution is impractical from a size and power consumption point of view. Another solution is the use of mirrored dummy switches so that each branch of the common voltage feedback loop 234 has the same amount of resistance. In this regard, Figure 6 is a more detailed diagram of the multi-PMIC system 200 with dummy switches 600, 602, and 604. The dummy switches 600, 602 make sure that the current feedback loops 218, 230 have the same number of switches in place and are balanced with the switches in the voltage feedback loops 306, 308. Similarly, the switch 604 balances the switch 304. Use of the dummy switches 600, 602, 604 is one solution. Alternatively, resistors or the like could be used. While there is some power and space cost to the dummy switches 600, 602, 604, the use of the dummy switches 600, 602, 604 is a space and power saver compared to a single large, low resistance switch. [0043] In the preceding discussion, it has been assumed that there is a single clock providing a single clock signal with a single frequency to both PMICs 204, 206. The use of a single clock signal at a single frequency makes toggling between the different PMICs 204, 206 relatively simple as the control circuit 300 only has to consider one period.

[0044] There may be situations, however, in which different ones of the multi-PMIC system rely on different clock signals as better illustrated in Figure 7. Specifically, the state machine 322 receives a first clock signal 700 and the second state machine 324 receives a second clock signal 702. If the different clock signals are at the same frequency, then a tandem circuit 320 may still find preventing concurrent current draws relatively easy to schedule. This prevention may be possible even in situations where the PMICs 204, 206 are both operating but not being summed as shown in Figure 7 where the switch 214 is coupling the first PMIC 204 to the output node 310 and the switch 226 is coupling the second PMIC 206 to the output node 312. Switch 302 is closed and switch 304 is open in this situation allowing each PMIC 204, 206 to have its respective voltage feedback loop 306, 308.

[0045] Note that the tandem circuit 320 may also operate relatively efficiently when the frequency of the first clock signal 700 (Fl) is an integer multiple of the frequency of the second clock signal 702 (F2) (or vice versa). When this sort of proportional relationship (Fl = F2x or F2 = xFl) exists, the tandem circuit 320 may divide drawing on the battery by using the lower frequency and, for example, on even cycles of the lower frequency drawing with the first PMIC 204 and on the odd cycles drawing with the second PMIC 206 (or vice versa).

[0046] Note that even when the frequencies are not proportional to one another, it may still be possible to lower instances of concurrent draws on the battery. That is, the tandem circuit 320 may make a best fit sequence of toggling the multiple PMICs. While there may still be instances where two or more PMICs draw on the battery concurrently, the overall number of instances when that happens compared to a conventional multi- PMIC system 100 is reduced, improving overall efficiency although not as much as when the frequencies are the same or are proportional.

[0047] A more explicit depiction of how the tandem circuit 320 works is provided in Figures 8A-8C. Specifically, the multi-PMIC system 200 is coupled to a battery or voltage source (Vbatt) 800. The PMICs 204, 206 may draw from the voltage source 800 through a voltage source input node (not specifically labeled, but the node between the voltage source 800 and the PMICs 204, 206). In Figure 8A, the tandem circuit 320 controls switches within the PMICs 204, 206 so that the first PMIC 204 draws current 802 from the voltage source 800. In contrast, the second PMIC 206 draws no current (i.e., 804(null)).

[0048] After some amount of time (e.g., the difference between an even and an odd cycle) as illustrated in Figure 8B, the tandem circuit 320 instructs the switches within the PMICs 204, 206 so that the first PMIC 204 stops drawing current (i.e., 802(null)) while the second PMIC 206 draws current 804 from the voltage source 800.

[0049] Figure 8C shows this concept in a different way with graph 806, which shows current draws 802 and 804 operating in opposition within windows 810, 812, respectively. That is, current 802 is drawn in windows 810 and current 804 is drawn in windows 812. [0050] It should be appreciated that there are myriad use cases for the multi-PMIC system 200 of the present disclosure. The multi-PMIC system 200 may be used to control power amplifiers being used concurrently by a single transmission, such as when carrier aggregation is used (e.g., low band and high band), when two different technologies are used (e.g., WIFI and Bluetooth), or the like.

[0051] With reference to Figure 9, the concepts described above may be implemented in various types of user elements 900, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user elements 900 will generally include a control system 902, a baseband processor 904, transmit circuitry 906, receive circuitry 908, antenna switching circuitry 910, multiple antennas 912, and user interface circuitry 914. In a non-limiting example, the control system 902 can be a field- programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. In this regard, the control system 902 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 908 receives radio frequency signals via the antennas 912 and through the antenna switching circuitry 910 from one or more base stations. A low noise amplifier and a filter of the receive circuitry 908 cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0052] The baseband processor 904 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed on greater detail below. The baseband processor 904 is generally implemented in one or more digital signal processors (DSPs) and ASICs.

[0053] For transmission, the baseband processor 904 receives digitized data, which may represent voice, data, or control information, from the control system 902, which it encodes for transmission. The encoded data is output to the transmit circuitry 906, where a digital-to-analog converter(s) (DAC) converts the digitally-encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 912 through the antenna switching circuitry 910 to the antennas 912. The multiple antennas 912 and the replicated transmit and receive circuitries 906, 908 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0054] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0055] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

What is claimed is:

1. A multiple power management integrated circuit (PMIC) (multi-PMIC) system comprising: a first PMIC configured to receive a target voltage and generate a first output signal; a second PMIC configured to receive the target voltage and generate a second output signal; an output node coupled to the first PMIC and the second PMIC and summing the first output signal and the second output signal to form a combined signal; a first current feedback loop configured to measure a first current of the first output signal and provide a first feedback signal to the first PMIC; a second current feedback loop configured to measure a second current of the second output signal and provide a second feedback signal to the second PMIC; and a common voltage feedback loop coupling the output node to the first PMIC and the second PMIC and configured to provide a voltage measurement from the output node to the first PMIC and the second PMIC.

2. The multi-PMIC system of claim 1, further comprising a first filter positioned serially between the first PMIC and the output node.

3. The multi-PMIC system of claim 2, further comprising a first current detector in the first current feedback loop, the first current detector configured to measure current across an inductor in the first filter.

4. The multi-PMIC system of claim 1 , further comprising a second voltage feedback loop coupling the output node to the second PMIC.

5. The multi-PMIC system of claim 4, further comprising at least one switch positioned in the common voltage feedback loop and configured to couple the common voltage feedback loop to the second PMIC when the at least one switch is closed and isolate the second PMIC from the common voltage feedback loop when the at least one switch is opened.

6. The multi-PMIC system of claim 1, further comprising a control circuit coupled to the first PMIC and the second PMIC.

7. The multi-PMIC system of claim 6, further comprising a voltage source input node coupled to the first PMIC and the second PMIC, wherein the control circuit is configured to prevent the first PMIC from drawing current from the voltage source input node at the same time that the second PMIC draws current from the voltage source input node.

8. The multi-PMIC system of claim 1, further comprising a third PMIC and a fourth PMIC arranged in a quadrature arrangement with the first PMIC and the second PMIC.

9. The multi-PMIC system of claim 1 , wherein the first PMIC and the second PMIC share a clock source.

10. The multi-PMIC system of claim 1, wherein the first PMIC is configured to receive a first clock signal and the second PMIC is configured to receive a separate second clock signal.

11. The multi-PMIC system of claim 10, wherein the first clock signal has approximately the same frequency as the second clock signal.

12. The multi-PMIC system of claim 10, wherein the first clock signal has a first frequency that is an integer multiple of a second frequency of the second clock signal.

13. The multi-PMIC system of claim 1, further comprising an output switch configured to couple the first PMIC to the output node or a second output node isolated from the second PMIC.

14. The multi-PMIC system of claim 1, further comprising a comparator coupled to the first PMIC, wherein the comparator is configured to compare signals from the first current feedback loop and the common voltage feedback loop.

15. The multi-PMIC system of claim 1, further comprising a dummy switch in the first current feedback loop.

16. The multi-PMIC system of claim 15, further comprising a second dummy switch in the common voltage feedback loop.

17. A mobile communication device comprising: a transceiver comprising a multiple power management integrated circuit (PMIC) (multi-PMIC) system comprising: a first PMIC configured to receive a target voltage and generate a first output signal; a second PMIC configured to receive the target voltage and generate a second output signal; an output node coupled to the first PMIC and the second PMIC and summing the first output signal and the second output signal to form a combined signal; a first current feedback loop configured to measure a first current of the first output signal and provide a first feedback signal to the first PMIC; a second current feedback loop configured to measure a second current of the second output signal and provide a second feedback signal to the second PMIC; and a common voltage feedback loop coupling the output node to the first PMIC and the second PMIC and configured to provide a voltage measurement from the output node to the first PMIC and the second PMIC.

18. The mobile communication device of claim 17, wherein the multi-PMIC system further comprises a first filter positioned serially between the first PMIC and the output node. 18

19. The mobile communication device of claim 18, wherein the multi-PMIC system further comprises a first current detector in the first current feedback loop, the first current detector configured to measure current across an inductor in the first filter.

20. A method of managing power in a power amplifier, comprising: receiving, at a first power management integrated circuit (PMIC), a target voltage from a remote location; generating a first output signal responsive to receiving the target voltage; receiving, at a second PMIC, the target voltage; generating a second output signal responsive to receiving the target voltage; summing the first output signal and the second output signal to form a combined signal; measuring a first current of the first output signal; providing a first feedback signal to the first PMIC based on the first current; measuring a second current of the second output signal; providing a second feedback signal to the second PMIC based on the second current; and providing a voltage measurement based on the combined signal to the first PMIC and the second PMIC.