EP4659283A1

EP4659283A1 - Composite semiconductor substrates and processes of manufacturing

Info

Publication number: EP4659283A1
Application number: EP24703484.6A
Authority: EP
Inventors: Jürgen CARSTENSEN; Ala Cojocaru; Catarina Schmidt; Rainer Adelung
Original assignee: Umicore NV SA
Current assignee: Umicore NV SA
Priority date: 2023-01-30
Filing date: 2024-01-30
Publication date: 2025-12-10
Also published as: WO2024160851A1; CN120858434A; JP2026505288A; TW202449856A; DE202024100459U1

Abstract

A compound semiconductor wafer, comprising a composite layer structure with a stack (2) of layers (2a, 2b). The stack comprises a substrate layer of a semiconductor material and a porous layer extending over the substrate layer. The semiconductor material is one of the group consisting of In, GaAs, GaP or Ge. The porous layer is of InP and has a volume porosity of not more than 20%.

Description

COMPOSITE SEMICONDUCTOR SUBSTRATES AND PROCESSES OF MANUFACTURING

TECHNICAL FIELD

This invention relates to composite semiconductor substrates, and processes and methods of manufacturing such substrates.

INTRODUCTION

Porous semiconductors can exhibit new and unexpected mechanical, electrical and optical properties compared to the bulk materials. For example, in III-V semiconductors, porous semiconductors exhibiting optical properties have emerged during the last few years for certain pore morphologies. However, known processes used to manufacture porous III-V semiconductor structures are complicated, and either result in a specific layer stack or can only be applied when forming the semiconductor devices in the semiconductor substrate.

For example, Ukrainian utility model UA 54 800 discloses a method of making films of InN, which comprises the preparation of a porous single crystal InP film on an InP substrate by electrochemical etching in a hydrochloric acid solution (5%) in the dark at a direct current density of 150 mA/cm² for 10 min or in a hydrofluoric acid solution (HF: H2 ChCzHsOH = 1 : 1 : 1), current density 80 mA/cm², etching time: 5 min, and subsequent growth of an InN film of 1.2 micron on the porous single crystal InP film by radical-beam epitaxy in a stream of atomic nitrogen at a temperature of 300 to 400°C for 1.5 hours. This method though is specific to making films of InN, and results in a specific layer stack of materials in which the porous InP is buried. There is further a significant mismatch in crystal lattices because the InN film has a Wurtzite structure and InP has a Zincblende structure.

In particular, for devices with a heterostructure comprising a porous, crystalline, compound semiconductor layer on a foreign crystalline substrate of another semiconductor material only device specific processes are known. For example, Chinese patent application publication CN 110 299 435 describes a method for preparing a InP film with a distributed Bragg mirror. This known method comprises the steps of performing electrochemical etching on a InP substrate in an electrolyte to obtain a porous InP and then increasing a voltage to prepare a stripped large-area porous InP film. Etching is performed for 10 to 15 minutes at etching rates of 1 pm/min to 4 pm/min. A distributed Bragg mirror is formed by electrochemical etching on an n- GaN/u-GaN periodic structure. Subsequently, the porous InP film is peeled off the InP substrate and transferred to the distributed Bragg mirror using a PDMS (Polydimethylsiloxane) transfer technique. This process is therefore specific to making the Bragg mirror on a GaN substrate. In addition, this process takes a long period of time.

Accordingly, it has been found by the present inventors that there is a need for engineered substrates with a porous semiconductor layer which are not embedded in a specific layer stack or dedicated to a specific type of device, and for processes of making such engineered substrates.

It is known from Suchikova, Yana & Kidalov, Valeriy & Sukach, G.A.. (2013). "Morphology of porous n-InP (100) obtained by electrochemical etching in HCI solution", Functional Materials. 17. 1 - 4. to make pores on all surfaces of an ingot of InP. In this respect, Suchikova further discloses that the etching rate differs on different surfaces and that the form of pores is defined by the crystal orientation at the surface, with these on mono-crystal InP oriented (100) having in cross-section the form close to a correct quadrangle and oriented (111) being triangular. Suchikova discloses that after electrochemical etching in a solution of a hydrochloric acid a nano-porous layer of InP with a degree of porosity of approximately 30% appeared on the (100) surface. The diameter of the pores averaged 40 nm with the walls between pores being between 5 and 10 nm. Depth of germination of the channels of the pores was approximately 35 pm. Suchikova further discloses that the smaller the size of pores and the higher the porosity range is, the more qualitatively porous the structure is and that photoluminescence is only observed for structure in the order of nanometres.

However, an ingot is not suitable to form electronic devices thereon with the customary techniques used in the semiconductor industry, such as photolithography, and currently no substrates exist on which subsequently electronic devices can be made with these customary techniques, nor are there processes available to make such substrates. The high cost of indium phosphide (InP) substrate, combined with its low mechanical strength and susceptibility to breakage during handling, presents significant challenges in production and ultimately results in production losses and waste, particularly for larger diameter substrates or wafers. Additionally, indium and phosphorus, being critical materials, pose concerns regarding long-term availability. Therefore, there is a pressing need for the development of new production methods that prioritize material efficiency and high productivity while addressing these issues.

SUMMARY

The present invention provides composite semiconductor substrates and processes or methods of manufacturing such substrates as described in the detailed description and in particular as described in the accompanying claims.

It is found that such substrates have a porous layer which is suitable to make electronic devices, because such a layer allows growing other layers, in particular homo- or heteroepitaxial layers while maintaining mechanical, electrical and optical properties of porous materials.

Specific embodiments of the invention are set forth in the dependent claims and described in the detailed description.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

DESCRIPTION OF THE FIGURES

Further details, aspects and embodiments of the invention will be described, by way of example only, with reference to the drawings. In the drawings, like reference numbers are used to identify like or functionally similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

FIG. l(a)-(c) schematically show views an example of an embodiment of a semiconductor wafer in various stages of manufacturing devices thereon.

FIG. 2 shows a cross-sectional view of an example of an embodiment of a semiconductor wafer. FIG. 3 (a)-(f) schematically show cross-sectional side-views of an example of an embodiment of a semiconductor wafer in a various stages of an example of a process of making a wafer, such as the example of FIG. 2.

FIG. 4 shows an electron microscope image of an example of a porous InP layer stack in a stage of manufacturing a porous layer.

FIG. 5 shows etching current and potential as a function of time in an example of a process of electrochemical etching pores in an InP wafer, whereby said etching current and potential are applied to a wafer surface of 0.2 cm².

FIG. 6 shows a scanning electron microscope image of the porous surface of an InP wafer obtained with the process of FIG. 5.

FIG. 7 shows etching current and potential as a function of time in another example of a process of electrochemical etching pores in an InP wafer, whereby said etching current and potential are applied to a wafer surface of 0.2 cm².

FIG. 8 shows a scanning electron microscope image of the porous surface of an InP wafer obtained with the process of FIG. 7.

FIG. 9 shows etching current and potential as a function of time in another example of a process of electrochemical etching pores in an InP wafer, whereby said etching current and potential are applied to a wafer surface of 0.2 cm².

FIG. 10 shows a scanning electron microscope image of the porous surface of an InP wafer obtained with the process of FIG. 9.

FIG. 11 shows a scanning electron microscope image of the porous surface of an InP wafer after exposing a lower porosity sublayer by chemical-mechanical polishing.

DETAILED DESCRIPTION OF THE INVENTION

Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary as illustrated for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

FIG. 1(a) shows as an example of a semiconductor substrate suitable for forming semiconductor devices with the customary techniques used in the semiconductor in- dustry a semiconductor wafer 10. The wafer 10 comprises two major, generally parallel surfaces 11, 12, one of which is a front surface 11 of the wafer and the other of which is a back surface 12 of wafer. A circumferential edge 13 joins the front and back surfaces 11, 12 of the wafer 10. In FIG. 1(a), the circumferential edge 13 is circular and the wafer 10 is shaped like a circular disc. The edge 13 has in this example a flattened or straight section 14 where a circular segment of the circle is absent, each of the surfaces 11, 12 is therefore geometrically speaking a disk-segment. Semiconductor wafers are generally prepared from a mono-crystalline ingot (e.g. a InP or GaAs ingot), which is sliced into individual wafers. Typically but not necessarily, prior to slicing the ingot is trimmed and ground to have one or more flats or notches for proper orientation of the wafer in subsequent procedures, resulting in this example in the straight section 14.

Referring to FIG. 1(b), multiple die areas 100 are indicated on the wafer 1. The die areas have a rectilinear shape and are arranged in a matrix array. However, other shapes and arrangements may be used as well. The manufacturing of semiconductor devices and electronic circuits typically involves the shaping of multiple independent devices or circuits on the semiconductor wafer, in a manner that the devices or circuits can be separated in a later stage of the manufacturing, e.g. by singulating ("dicing") the semiconductor wafer in individual pieces (dice) of semiconducting material, each with a given electronic circuit or electronic device. The shaping of the multiple separate circuits or devices in the die areas normally involves the formation of a variety of patterned and un-patterned insulating, semi-conductive and conductive device regions and layers on a substrate formed by the unprocessed wafer. Such a patterning involves transferring a predefined pattern, e.g. in case of photolithography projecting an image of the desired pattern on the wafer surface. As part of the patterning, a photoresist layer is typically deposited on the top-surface of the wafer and patterned by a photolithographic or other process, thus creating regions in which the top-surface of the wafer is exposed and regions where the top-surface is not exposed. By depositing other layers on the photo-resist and subsequent processing such as partial removal thereof or exposing the top-surface to e.g. etchants or other processes, patterns may be formed on the wafer to form the semiconductor devices. As shown in FIG. 1(c) after singulation, the semiconductor wafer 10 is no longer an integral block with multiple independent circuits or devices but is separated in individual dice 101 of semiconducting material, each with a respective electronic circuit or electronic device. The singulated dice 101 can be subject to further processing, if so desired, such as testing and packaging the singulated circuits into an integrated circuit package. The die areas 100 indicate the areas corresponding to the individual dice after manufacturing the circuits and singulation. Dice will typically have dimensions of a width between 1 mm and less than 5 cm and a length of between 1 mm and less than 5 cm, although other dimensions may also be used, and in FIG. 1, the dicing is illustrated on an simplified scale.

In the following, reference will be made to an un-patterned wafer, that is a wafer prior to forming device structures thereon. The wafer may be the initial wafer, that is the un-diced, disk-shaped, sliced part of the ingot. However, instead of forming the circuits and then dicing, the un-patterned slice may be diced first and the, unpatterned, die or dice be provided with a blanket porous layer thereon, e.g. by subjecting to a process of manufacturing as described. In the example, the processes are applied prior to forming devices in the wafer, to provide an un-patterned wafer with a blanket, un-patterned porous layer. However, instead the wafer may be patterned to have individual die areas provided with a blanket layer and separated by gaps between the die areas where the porous layer is absent to facilitate dicing and which e.g. define the scribe lines. Also, the processes described may be used in other applications and be applied to in other processes, e.g. to pattern locally a porous structure as part of forming of the devices.

Referring now to FIG. 2, the semiconductor substrate shown is preferably a wafer 10. In this example, the substrate is an un-patterned and/or un-diced semiconductor wafer. The substrate comprises a composite layer structure with a stack 2 of layers 2a, 2b comprising a substrate layer 2a, also referred to as bulk layer, on top of which one or more other layers 2b are provided which differ in structure, specifically in porosity, from the bulk layer 2a. These other layers comprise a porous layer of a compound semiconductor material. In this example, the layer stack is a two layer stack consisting of the substrate layer 2a and the porous layer 2b. The layer stack 2 is shown with an exposed surface of the porous semiconductor layer 2b forming the frontside 11 of the wafer 10, and the porous layer 2b forming a surface layer of the wafer. An exposed surface of the substrate layer 2a faces away from the frontside 11 and forms a backside 12 of the wafer. Both exposed surfaces 11, 12 may be, temporarily, covered by covering layers or films, e.g. for protection during transport or handling, which in subsequent processing are removed prior to growing other layers on the exposed surfaces. The backside 12 may be formed by another layer than the substrate layer 2a, e.g. one or more backing layers may have been provided on the backside of the wafer. In FIG. 3, the backing layer 1 is indicated, and may consist of a supporting layer preferably having a similar thermal coefficient as the substrate layer 2a and/or 2b. Preferably, the backside of the wafer is provided with a uniform, homogeneous ohmic contact.

The semiconductor wafer 10 has a central plane, indicated with the dashed line in FIG. 2, between the front surface 11 and the back surface 12. The central plane extends through the bulk layer 2a, substantially parallel to the surfaces 11, 12. A top layer, also referred to as surface layer 2b extends parallel to the front surface 11. Seen in the stacking direction from the front surface 11 to the bottom surface 12, the surface layer extends from the front surface 11 up to a depth d into the wafer 10. The surface layer 2b lies on top of the substrate layer 2a and in this example is in direct contact with the substrate layer 2a. In this context, the surface layer 2b is the same material as substrate layer 2a, and is comprised of InP, preferably monocrystalline InP. This structure corresponds to the multilayer structure (c) in FIG.3. The substrate layer 2a can be of the same material as the surface layer 2b or of a different material. Examples of suitable materials for the substrate layer 2a are e.g. InP, Ge, GaN, GaP or GaAs.

The substrate layer 2a is in this example a monocrystalline semiconductor material but instead may be of a polycrystalline or amorphous material. While reference will be made herein to semiconductor wafers with a substrate layer 2a of InP or GaAs, the bulk layer 2a may be of another material, such as germanium, gallium phosphide and other alloys of Group III and Group V elements, such as gallium nitride or indium phosphide, or alloys of Group II and Group IV elements, such as cadmium sulphide or zinc oxide. Furthermore, the substrate layer 2a may be doped or undoped. For example, the substrate layer 2a may be doped with a p-type dopant or with an n- type dopant. The surface layer 2b is a porous surface layer of a compound semiconductor material (e.g. InP or other III-V semiconductor). Because the porous layer 2b has one or more of the following properties, the porous layer is suitable to grow other layers on, in particular homo- or heteroepitaxial layers 3 (as illustrated in FIG. 3(f), for example). It is found that each of these properties on the one hand results in a porous layer which can exhibit new and unexpected mechanical, electrical and optical properties compared to the bulk materials, whereas this still allows a sufficient self-ordering to grow other layers, in particular homo- or heteroepitaxial layers.

A first property is that the porous layer 2b has a surface porosity, at the porous surface facing away from the substrate layer 2a (which in this example is the front surface 11), of not more than 50% and/or a volume porosity of not more than 10%. Preferably, the surface porosity is not more than 30%. It is currently preferred that the surface porosity is at least 10 %, more preferably at least 20%. The volume porosity of the porous semiconductor layer is preferably less than 5%. The charge carrier density may for instance be in the range of 1 to 1.7-10¹⁷/cm³. It is found that this results in a porosity that allows for good bonding to another substrate and accordingly particularly easy transfer of the porous layer to a foreign substrate. Moreover, it is found that this results in a porosity that allows for good growth of an overlayer, i.e., an epitaxially grown layer, grown through, e.g., CVD.

A second property is that the porous layer is of a compound semiconductor material and is provided with pores having different geometries, i.e., a tubular geometry where the tube is in the direction of the current flow during the etching process, and a triangular geometry, which is a result of the crystallographic orientation of the pores. "Tubular pores" and "triangular pores" are also referred to as "current line pores" and "crystallographically oriented pores," respectively. These geometries can exist in a mixed form, where the pores exhibit both tubular and triangular shapes. This is because the pores are both current line and crystallographic in nature, as evidenced by their branching morphology and preferential orientation perpendicular to the surface of the wafer. In the context of the present invention, a porosity type consisting of multiple morphologies, specifically comprising the "tubular type" and the "triangular type" will be referred to as a "mixed-type" porosity. A compound semiconductor porous layer having a "mixed-type" porosity is preferred. These pores may comprise one or more pore-types of the group consisting of: macro-pores, meso-pores and micro-pores. In the field of semiconductor etching and in the context of the current invention, the term "macro-pores" refers to pores having a median diameter in the range of 500 nm to 50 pm; the term "meso-pores" refers to pores having a median diameter in the range of 10 nm to 500 nm; the term "nano-pores" refers to pores having a median diameter of less than 10 nm. In this example, the pores are all, or at least predominantly, meso-pores. It is currently preferred that the median diameter of meso-pores is in the range of 70 nm to 150 nm. As can be seen in FIG. 2, the tubular pores can extend from a pore entrance located at the porous surface into the porous layer, towards the substrate layer. Some or all of the tubular pores may form a branched channel, such as a branched channel which branches from the porous surface towards the substrate layer.

A third property is that the porous layer is provided with current line oriented pores extending from the porous surface (etched around 6V). Crystallographically oriented pores can be used as well (etched around 4V). Even the combination of both pore types, the mixed pores, can be used for this approach when applying an intermediate voltage (of around 5V). In this respect, current line oriented pores do not follow the crystallographic planes, contrary to crystallographically oriented pores. Reference is made to section 4.4. of Foil, H., Langa, S., Carstensen, J., Christophersen, M. and Tiginyanu, I. (2003), Pores in III— V Semiconductors. Adv. Mater., 15: 183-198. https://doi.org/10.1002/adma.200390043 in this respect. Current line pores in the porous layer are less preferred because they require larger etching currents and result in a higher porosity. This makes the etching process less efficient and may cause unwanted etching in other areas of the surface. Therefore, the porous layer is preferably provided with mixed pores, as described above. This arrangement of mixed pores reduces the required etching current and provides a more uniform and controlled etching process.

A fourth property is that the pores extend from the porous surface up to a depth less than the thickness of the semiconductor wafer and the substrate layer is non-porous. The porous layer can for example have a thickness of 50 pm or less and/or 5 pm or more. In an example, the ratio of the thickness of the porous layer to the thickness of the substrate layer is not more than 25%, preferably not more than 18%. A fifth property is that the porous layer is a mono-crystalline layer, and/ or the substrate layer is a mono-crystalline layer and/or the substrate layer and the porous layer have the same type of crystal structure. In a preferred example, the crystal structure of at least one, more preferably both, of the substrate layer and the porous layer is of the Zincblende type.

Although in this example the porous layer is a blanket, un-patterned layer, in other applications the porous layer may be a patterned layer and/or be formed locally. In particular, the porous layer is suitable for use in the manufacture of forming semiconductor devices on the un-patterned substrate.

The substrate, in this example the wafer 10, with the porous layer 2b is particularly suitable as a starting point for further processing to manufacture semiconductor devices in case the substrate has a compound semiconductor layered structure. In such a case, the layer stack 2 can comprise a porous InP surface layer 2b in direct contact with a substrate layer 2a of InP, GaAs, Ge or GaP, for example. Preferably, the porous InP surface layer 2b has a thickness of 5 to 50 pm and a volume porosity of not more than 10%, as determined by SEM. Most preferred is that the porous InP surface layer 2b has a thickness of 5 to 50 pm and a volume porosity of not more than 5%.

The porous layer 2b can be formed in an exposed surface of the substrate layer 2a and the porous layer can form a mono-composition structure with the substrate layer, as illustrated in FIG. 2. In such a case, the substrate layer and the porous layer may form a single crystal. In case the porous layer 2b and the substrate layer 2a form a mono-composition structure, the thickness of the porous layer is determined by the depth up to which the pores extend into the substrate.

Alternatively, the porous layer can be an additive layer, e.g. a layer which has been transferred onto the substrate layer with a layer transfer process. In such a case, the semiconductor substrate layer can have a flat, unprofiled side facing the porous semiconductor layer 2b at which the porous semiconductor layer 2b is bonded onto the substrate layer. Vice-versa, the porous semiconductor layer 2b may then comprise a surface facing towards the substrate layer at which the porous layer is bonded. A bonding interface may extend between the porous semiconductor layer and the substrate layer. For example, this surface may be bonded to the semiconductor substrate by a thermal bond, and for instance a thin transitional thermal bonding layer may extend between the porous layer and the substrate resulting from the thermal bonding. In case of a transferred layer, the porous semiconductor layer may have an exposed side with traces of a lift-off process where the porous semiconductor layer has been separated from an initial wafer.

The porous layer may have been thinned, that is the thickness thereof be reduced, and traces thereof be present. For instance, the top surface may have been removed up to a certain depth to remove a part with undesired properties, such as with a different porosity. In the shown example, at the porous surface, that this the exposed side facing away from the substrate layer 2a, traces of a removal process can be present. In case of a porous layer 2a transferred onto the substrate layer, the traces of the removal process of a part of the porous semiconductor layer may be present at a bonding side of the porous semiconductor layer, which faces the substrate layer. The traces may e.g. be traces of grinding, polishing, e.g. chemical-mechanical polishing (CMP) or other wafer thinning processes applied to partially remove the porous layer 2b and reduce its thickness. CMP can for example leave scratches, particle residues or debris at the polished surface.

The porous surface may have a more or less uniform surface porosity, as for example seen in FIG. 10 where the porosity is more or less a homogenous in two-dimensions. Although the latter is currently preferred, in an alternative example, the porous surface can have a pattern of areas with different surface porosity. As can be more clearly seen in FIG. 6 for example, straight line-shaped limited porosity areas may be present, which are defined by a non-porous area extending between two parallel, spaced apart, straight line shaped boundaries. In the non-porous area a straight line shaped pattern of pores, extending parallel to the parallel boundaries is present. The pattern is more or less in the middle between the parallel boundaries. Outside these areas, homogenous two-dimensional patterns extend, which are thus distanced from the straight line shaped pattern by the non-porous regions. Surprisingly, it has been found that such areas do not affect the suitability mentioned above. In additional it has been found that even with limited porosity areas as described the porous layer can be transferred to another substrate. On the porous surface of the semiconductor substrate, epitaxial layers 3 may be provided, as illustrated in FIG. 3(f). Thus, a semiconductor layered structure may be obtained which comprises a composite wafer, such as described above, and an epitaxial layer 3 extending over the porous surface of the composite wafer. The epitaxial layer 3 can e.g. be grown directly on the porous layer 2b, with the porous layer forming a seed layer for the epitaxial layer. The epitaxial layer can be of the same semiconductor material as the substrate but other materials are also possible. The epitaxial layer and the substrate can e.g. form a heterostructure, with preferably the same crystal type. Although other materials may be used, it is currently preferred that the epitaxial semiconductor layer comprises an epitaxial compound semiconductor layer, optionally an epitaxial binary semiconductor layer, further optionally an epitaxial III-V semiconductor layer, and preferably an epitaxial indium phosphide (InP) layer. After forming the epitaxial layer further blanked processing may be performed and e.g. additional layers be grown as deemed suitable for the specific type of semiconductor device to be manufactured in and on the substrate.

Method

Referring to FIG. 3, FIGs. (a)-(c) illustrate a first process, for producing a porous surface layer on an initial wafer, e.g. a mono-crystalline semiconductor wafer, such as a mono-crystalline compound semiconductor wafer. Advantageously, the method of the present invention provides a composite substrate with a porous layer that is suitable to grow other layers, in particular homo- or heteroepitaxial layers, and for use in the manufacture of semiconductor devices.

As illustrated in FIG. 3(a), the first process may start with providing an initial semiconductor a substrate, such as the wafer 10. The initial semiconductor substrate comprises a substrate layer 2a. For instance, the substrate may be the slice as obtained from the ingot, cleaned, polished etc. to be a wafer but not further processed or modified, and in particular not patterned to form semiconductor devices.

As illustrated in FIG. 3(b), the substrate can then be provided with a porous layer of a compound semiconductor material comprising a higher porosity sublayer 2c and a lower porosity sublayer 2b. FIG. 3(b) shows the porous layer extending over a substrate layer 2a, with the lower porosity sublayer 2b extending between a substrate side of the higher porosity sublayer 2c and the substrate layer 2a. The lower porosity sublayer 2b has a porosity lower than a porosity of the higher porosity sublayer 2c. In an example, the lower porosity sublayer 2b has a porosity higher than a porosity of the semiconductor substrate layer 2a and lower than the porosity of the higher porosity sublayer 2c. For instance, the substrate layer 2a may be non-porous. The lower porosity sublayer 2b may have a volume porosity of not more than 10%, as determined by SEM, such as of not more than 5%. The higher porosity sublayer 2c may have a volume porosity of not less than 20%, as determined by SEM, for example. The exposed top surface of the resulting layer stack may be formed by a thin layer of film with a lower porosity than the higher porosity sublayer 2c, as can be seen in FIG. 4. There the porous layer 2 comprises a thin layer or film of between about 0.5 pm to 1 pm. The thin layer or film forms the exposed top surface, and contacts the higher porosity sublayer 2c.

The porous layer may be provided in any suitable manner. For instance, the substrate layer of the initial substrate may be etched or otherwise provided with pores, e.g. by electrochemical (EC) etching. This results in a substrate layer 2a which has a reduced thickness compared to the initial substrate layer. Alternatively a porous layer may be grown on the initial substrate, e.g. by homo-epitaxy and subsequent etching. As shown, a first surface of the porous layer may face away from the substrate layer 2a and a second surface faces towards the substrate layer 2a. In this example the second surface contacts the substrate layer 2a.

FIG. 4 shows a SEM image of a structure which can be obtained. Shown therein is the porous layer. As can be seen, the porous layer comprises at the front surface the higher porosity sublayer 2c, covered by a film or thin layer of lower porosity. The film or thin layer is about 1 pm thick and forms the front surface layer. The film or thin layer has, compared to the higher porosity sublayer 2c, a relatively low porosity and low self-organisation. The higher porosity sublayer in this example has in the vertical direction, from the front surface to the bottom surface, a layered structure. Below the film and up to the low porosity sublayer 2b, several layers, in this experiment 3 to 4 layers, of pore cells with a relatively large diameter and short length, which may also be referred to as neck or wide-body pores are located. The vertical (i.e. in the direction from front surface to bottom surface) sequence of cavities and bottle-necks formed by these layers are thought to form a nucleation layer which allows to very precisely and reproductively control formation of the lower porosity layer.

In addition, it is found that the cavities and bottle-necks still allow for high etching rates and current densities and contrary to what would be expected they do not increase the duration of an (electrochemical) etching process. This is particularly advantageous in combination with a doping with a charge carrier density of not less than 5-10¹⁶/ cm³ and not more than 1.0-10¹⁸/ cm³, preferably not less than 1-10¹⁷/ cm³ and not more than 4-10¹⁷/ cm³, and more preferably not less than 1-10¹⁷/ cm³ and not more than 2.0- 10¹⁷/ cm³, and most preferably about 1.5- 10¹⁷/ cm³ since this allows to obtain a porous layer with good homogeneity, especially on large wafers, in a relatively short period of time. For example, as illustrated in FIGs. 5, 7 and 9, an etching process may be performed in about 1 min. In particular for InP substrates, it is believed that with the prior art methods doping with a charge carrier density in the range of 2 to 4-10¹⁷/ cm³ (and higher) is required for a commercially acceptable period of time but that this may on large wafers result in an inhomogeneous distribution of pores, e.g. due to large currents, ohmic losses and gas bubbles during electrochemical etching.

After providing the porous layer, the lower porosity sublayer 2b lies buried in the substrate, between the substrate layer 2a and the higher porosity sublayer 2c. The lower porosity sublayer 2b may be exposed, and the semiconductor wafer may be provided with an exposed low porosity surface facing away from the substrate layer. FIG. 3(c) shows the substrate after exposing the lower porosity sublayer. As can be seen, this exposing may comprises partially removing the porous layer, from the front surface to a depth less than the thickness of the porous layer and more than a depth at which a substrate-side of the higher porosity sublayer 2c is located. Preferably, the reduction in thickness is such that the thickness of the lower porosity sublayer remains intact but the lower porosity sublayer may be reduced in thickness without being removed completely in this process. In the example of FIG. 4, for instance, at least 2 pm of the porous layer may be removed from the front surface. After exposing, the higher porosity sublayer 2c is removed, and the lower porosity sublayer 2b becomes the porous surface layer. After producing the porous surface layer on the initial wafer, the obtained engineered or composite substrate may e.g. be used to form semiconductor devices thereon. For example, the processing may stop. For instance, the engineered wafer may be subjected to finishing steps such as cleaning, planarization etc and may be subjected to end of line metrology inspections and cleaned a final time. These steps may be omitted and exposing the porosity layer may be sufficient to finalize the engineered wafer.

In another example, the wafer comprising the porous surface layer can be used as a donor wafer in the production of a composite wafer with a hetero-composition structure of layers of different materials which comprises a porous surface layer. Figs.3(d)- (f) illustrate a second process of transferring the porous surface layer 2b from the donor wafer to a foreign wafer with a foreign substrate layer 1, also referred to as bulk layer, of a semiconductor material different from the porous layer. In the shown example, the foreign wafer is a monolayer structure. The foreign wafer may be an engineered wafer with a multilayer stack onto which at least the porous layer but optionally other layers of the donor wafer, is transferred or be a mono-layer wafer consisting of a single substrate layer. The foreign substrate may be monocrystalline.

The layer transfer may comprise bonding the donor substrate to an initial foreign substrate to obtain a bonded layer stack, and separating one of more layers of the donor substrate from the bonded layer stack. FIG. 3(d) shows the bonded layer stack with the donor substrate 2 and the initial foreign substrate 1 bonded to each other. As can be seen the porous surface layer 2b becomes buried in the bonded stack, and lies between the bonded donor substrate layer and the initial foreign substrate layer. The porous surface directly contacts the initial front surface of the foreign substrate 1.

After bonding, the donor substrate layer 2a is in this example separated from the porous layer 2b. The donor substrate layer 2a may then be re-used in a similar process and be provided again with a porous layer, as indicated with the arrow from FIG. 3(e) to FIG. 3(b). FIG. 3(e) shows the substrates after separation. As shown, the porous layer remains bonded to the foreign substrate layer 1 and becomes the surface layer of the foreign substrate. The exposed surface is the side that faced the substrate layer of the donor substrate and the side of the porous semiconductor layer 2b that faces the foreign substrate layer was previously the front surface of the donor wafer.

The foreign wafer may after transferring be used "as is" in processes to shape semiconductor devices thereon, and be patterned, etc. but alternatively, as illustrated in FIG. 3(f) one or more blanket layers may be grown or be deposited thereon to increase the number of layers in the stack 2. Thereby a further engineered un-pat- terned wafer is obtained. On the porous surface of the semiconductor substrate, one or more epitaxial layers may be grown for instance. In such a case a semiconductor layered structure may be obtained which comprises a composite wafer, such as described above and an epitaxial layer extending over the porous surface. The epitaxial layer can e.g. be grown directly on the porous layer, with the porous layer forming a seed layer for the epitaxial layer. The epitaxial layer can be of the same semiconductor material as the substrate but other materials can be possible as well. The epitaxial layer and the substrate can e.g. form a heterostructure, with preferably the same crystal type, such as Zincblende. Although other materials may be used, it is currently preferred that the epitaxial semiconductor layer comprises an epitaxial compound semiconductor layer, optionally an epitaxial binary semiconductor layer, further optionally an epitaxial III-V semiconductor layer, and preferably an epitaxial InP layer.

Stages of the processes described above are explained in more detail below. For each stage, the optional aspects described may be combined with one or more optional aspects of the other stages.

Providing wafer

As the initial substrate, any suitable substrate may be used. The substrate may be of a semiconductor material. The semiconductor material may have been doped, e.g. the charge carrier density may for instance be in the range of 1 to 1.7-10¹⁷/cm³, such as charge carrier density of not more than 1.5-10¹⁷/cm³. In this example, as a suitable substrate a wafer is provided, such as described above with reference to FIG. 1.

The wafer may be a mono-layer or multilayer structure. In the examples described and experiments a monocrystalline monolayer wafer of a compound semiconductor material is used. Specifically the wafer was of a III-V compound with a Zincblende crystal structure, more specifically an InP wafer. However, other types of wafers or substrates may be used as well.

Prior to forming the pores, a blanket layer, e.g. homo-epitaxial, may have been grown over the front surface of the initial substrate. For instance, an InP homo-epitaxial layer may have been grown on a monocrystalline InP substrate, e.g. with a molecular beam epitaxy process as known in the art.

In this example, the surface of the substrate was non-porous and more specifically the entire substrate layer was non-porous.

Preparing pores

The substrate provided is subject to a process to form a porous layer in the front surface of the substrate. The described examples and experiments may also be applied in other processes, e.g. to prepare a porous layer with a porosity gradient and/or to better control the reproducibility of the preparation of porous.

In some embodiments, the front surface of the semiconductor foreign wafer is treated to form a porous layer. The porous layer may be formed by contacting the front surface of a mono-crystalline semiconductor handle substrate with an etching solution. The porous layers may form a single crystal with the substrate layer, and in the described examples, the pores are provided in the exposed surface of the initial mono-crystalline substrate.

Although other processes, such purely chemical etching, plasma etching or otherwise, may be used, in these examples and experiments, the substrate layer 2a is electrochemically etched to form a porous layer in the front surface region of the substrate. In the case of InP as a substrate layer, electrochemical etching may for example be performed in a solution of HCI. The electrochemical etching conditions may be set as required for the specific type of pores. The properties of porous compound semiconductors, such as porosity, thickness, pore diameter and microstructure, depend on anodization conditions. These conditions include electrolyte concentration, current density, wafer type and resistivity, anodization duration, illumination, temperature, and drying conditions. Choosing proper conditions to get a desired porosity and pore size is described in previous art. Reference is made to Foil, H., Langa, S., Carstensen, J., Christophersen, M. and Tiginyanu, I. (2003), Pores in III— V Semiconductors. Adv. Mater., 15: 183-198. https://doi.org/10.1002/adma.200390043 in this respect.

During the electrochemically etching the difference between the applied voltage and the open circuit voltage may be maintained constant by periodically applying offset voltages to the non-porous semiconductor wafer. Such a voltage control may be applied to other electrochemical etching of pores, e.g. of preparing a porous layer in a compound semiconductor. This is found to allow to increase reproducibility of the etching conditions and therefore allows a more constant manufacturing, especially when large areas are to be provided with pores. In particular, for preparing porous InP, such as InP-layers with different porosities galvanostatic control is not sufficient and a very accurate potentiostatic control needed. Such layers may e.g. be used in a layer transfer process.

The electrochemical process may be controlled to etch a porous layer in successive etching stages. In various stages of the electrochemical porosification, the open circuit potential may be measured and offset voltages be applied as an offset to the open circuit potential to maintain the difference between the applied voltage and the open circuit potential constant. The measurement of the open circuit potential allows in addition for a monitoring of the state of the etching experiment/system (e.g. aging of electrolyte, doping of wafers) and can be used for an in-situ feedback to adapt for individual etching profiles.

For example, the etching cell may be disconnected for short times from the power supply and the applied potential between sense-and reference-contacts be measured (e.g. with a 4 probe arrangement). Such a measurement is easy to apply to all sizes of etching systems (for small and large InP wafers) and allows to take various electrical potential influencing phenomena into account with a single measurement. This is especially advantageous where reproducible etching conditions e.g. for large area etching, are difficult to achieve with potentiostatic control. For example, electrical potentials in an etching cell may add up in series and depend strongly on e.g. electrolyte composition, temperature, wafer doping, surface defects, ohmic contacts, and etching cell geometry. In such as case, this measurement of the open circuit potential can take into account all of the potentials in series. Subsequently, electrical potential offsets may be applied to the measured open circuit potentials (after reconnecting working counter electrodes to the cell). This is found to drastically increase the reproducibility of the etching results. In this respect, the off-set may be applied intermittently, such that sequence of electrical potential offsets (duration and values) does not change, but the actually applied absolute potentials do change to keep the difference constant.

The electrochemical process may be controlled to etch a porous layer in successive etching stages. The etching stages may comprise surface preparation, pore nucleation and subsequent etching of a low porous layer, and etching a thin highly porous zip layer. In this respect, not all stages have to be performed. For example, the zip layer is a mechanically or otherwise weakened film between the porous layer and the substrate which reduces the adherence to the substrate layer and facilitates separation of the substrate layer and the porous layer from each other, thus e.g. allowing transfer from a donor substrate to a foreign substrate, such as a handle substrate or a device substrate. Thus, the thin highly porous zip layer may be omitted in case a layer transfer is not intended, or in case such a layer is not needed for separation of the layers (e.g. in case the bond between the layers is already intrinsically weak enough, weakened by ion implant or otherwise).

Surface preparation may comprise cleaning and surface activation. In the shown examples, surface preparation comprises exposure to a series of voltage pulses in the electrochemical cell. More specifically, each pulse can have a duration of less than 1 s and a voltage of not more than 10 V, the total period being less than 0.25 min. In a preferred example for InP substrates, preparation comprises exposing the substrate to two 4 V pulse-trains of 5 pulses with an interval of at least 1.5 between pulsetrains. Surface preparation of a wafer or substrate for electrochemical etching is generally known and not described in further detail.

In the present examples, prior to the pore nucleation and subsequent etching of a low porous layer a pre-treatment may be performed. The pre-treatment may comprise, prior to providing the porous layer, electrochemically pre-treating the non- porous layer by monotonously increasing a current through the non-porous semiconductor body from 0 mA/cm² to at most 125 mA/cm² for a period of less than 3 seconds, and subsequently reducing the current to its initial level. In a preferred example, the increase is a linear increase from an initial current level of 0 mA/cm², and the current is stopped immediately when it reaches a predetermined maximum current level. It has been found that the maximum current level of less than 50 mA/cm² gives good results. It has been found that such a pre-treatment strongly reduces inhomogeneities in pore growth in the lower porosity layer. As a comparative example, FIGs. 6 and 10 show substrates subject to this pre-treatment, whereas FIG. 8 shows a substrate subject to the pore nucleation and subsequent etching of a low porous layer without such a pre-treatment. The examples used in FIG. 6 and 8 had the same InP substrates with the same doping, with a charge carrier density of l-10¹⁷/cm³. The example of FIG. 10 differed in doping from the example of FIG. 6, with a charge carrier density of 1.5-10¹⁷/cm³ As can be seen, the example of FIG. 8 shows limited porosity areas with a large width and outside these areas, the porous surface present dot-shaped non-porous areas. In FIG. 6 and 10 on the other hand these non-porous areas are absent.

Prior to providing the porous layer, the initial semiconductor wafer may have a non- porous layer of a compound semiconductor material extending over the semiconductor substrate layer. This non-porous layer may be exactly the same as the semiconductor substrate layer and a mono-structure therewith. Pore nucleation and subsequent etching of a low porous layer may then comprise preparing a nucleation sublayer in the non-porous layer. The nucleation sublayer may be made to extend from a surface of the non-porous layer facing away from the substrate layer to an initial depth, the initial depth being less that the thickness of the non-porous layer. The non-porous layer with the nucleation sublayer may thereafter be exposed to an etchant, to form pores in the non-porous layer at a depth lower than the initial depth and obtain the lower porosity sublayer in a region of the non-porous layer between a substrate side surface of the nucleation sublayer and the substrate layer. Although other processes may be suitable, it is currently preferred that the etching is electrochemical etching. This provides a good control of the shape and type of pores and accordingly allows to prepare a nucleation layer particularly suited to make the lower porosity layer as desired. In view of the above disclosure and to be interpreted in the above context, we concisely identify the invention as follows: the present invention provides in a first aspect a compound semiconductor multilayered structure comprising:

- a substrate layer (2a or 1) comprising a semiconductor material, said semiconductor material selected of the group consisting of InP, GaAs, GaP and Ge;

- a porous layer (2b) extending over the substrate layer (2a or 1, respectively), said porous layer consisting of InP and having a volume porosity of not more than 20%, as determined by SEM.

The present invention provides essentially a porous layer of InP having a low volumetric porosity, such as lower than 25% or lower than 20%, as determined by SEM, or lower than 15%, or lower than 10% or even lower than 5%. Specifically, the present invention allows the formation of such porous surface layers in a controlled manner. A low porosity layer of InP provides the advantage that it forms a line of controlled breakage for the formation of thin films, either as such or as bonded or connected to a supporting substrate layer. With reference to FIG. 3, the structure of the first aspect of the invention envisages the concept (b) wherein an InP substrate or substrate wafer is porosified on one surface with the formation of a porous InP layer (2b) on top of the non-porous InP substrate. The inventors found that the activation or nucleation of the wafers substrate surface lead to a first porous layer (2c) with a comparatively higher porosity whereas the subsequent porosification yielded a more dense porous layer (2b) with a comparatively lower porosity. The highly porous layer (2c) is advantageously removed by polishing, preferably chemical-mechanical polishing as described above. After removal of the highly porous layer (2c), structure (c) in FIG. 3 is obtained. Structure (c) provides an InP substrate with a porous layer as described according to the first aspect of the invention. Structure (c) can then be bonded to a foreign substrate (1) consisting of GaAs, GaP or Ge, with the porous layer (2b) oriented towards the foreign substrate (1). Accordingly, the compound semiconductor multilayered structure (d) is obtained. Controlled breakage of the compound semiconductor multilayered structure (d) leads to separation of the porous layer 2b on the foreign substrate 1 with the release of the InP substrate 2a. The InP substrate 2a can subsequently be re-used for a next porosification step. In a preferred embodiment, the present invention provides a compound semiconductor multilayered structure according to the first aspect of the invention, in which the porous layer (2b) has a volume porosity is not more than 10%, as determined by SEM, preferably not more than 5%. Preferably, said porosity is not lower than 0.1%, and higher than 0.5%, and even higher than 1.0%

In a preferred embodiment, the present invention provides a compound semiconductor multilayered structure according to the first aspect of the invention, in which the porous layer (2b) has a thickness between 1 and 50 pm, as determined by SEM, preferably between 5 and 50 pm. More preferably, said thickness is about 5 pm, about 10 pm, about 15 pm, about 20 pm, or about 25 pm, or any thickness there in between.

In a preferred embodiment, the present invention provides a compound semiconductor multilayered structure according to the first aspect of the invention, wherein the porous layer (2b) has mixed pores extending perpendicular to the exposed surface, and wherein said mixed pores have a morphology intermediate to current line oriented pores and crystallographically oriented pores.

In a preferred embodiment, the present invention provides a compound semiconductor multilayered structure according to the first aspect of the invention, wherein the porous layer (2b) has pores extending from a pore entrance located at the porous surface into the porous layer (2b), and the pore entrances have a median diameter in the range of 70 nm to 150 nm. Preferably, said pore entrances have a median diameter in the range of 70 nm, 90 nm, 110 nm, 130 nm, or 150 nm, or any diameter there in between.

In a preferred embodiment, the present invention provides a compound semiconductor multilayered structure according to the first aspect of the invention, wherein said substrate layer (2a) consists of InP.

In a preferred embodiment, the present invention provides a compound semiconductor multilayered structure according to the first aspect of the invention, wherein said substrate layer (1) consists of a material selected of the group consisting of GaAs, GaP and Ge, preferably of the group consisting of GaAs and GaP. In a second aspect, the present invention provides a process of preparing a composite semiconductor multilayered structure, comprising the step of:

- electrochemical etching of an InP compound semiconductor substrate, thereby forming a porous layer (2b) of InP, the porous layer extending over the substrate layer (2a), said porous layer having a volume porosity of not more than 25%, as determined by SEM.

In a preferred embodiment, the present invention provides a process according to the first aspect of the invention, wherein prior to forming a porous layer (2b) of InP through electrochemical etching, the exposed surface of the InP substrate is electrochemically pretreated by electrochemical etching at intermittent voltage pulses, whereby the voltage pulses may be the same of different.

In a preferred embodiment, the present invention provides a process according to the first aspect of the invention, wherein said porous layer (2b) is predominantly formed by electrochemical etching for a period of at least 5 seconds, preferably at least 10 seconds and more preferably at least 15 seconds and preferably at most 120 seconds, preferably at most 60 seconds, more preferably at most 45 seconds, and most preferably for a period of 15 s, 20 s, 25 s, 30 s, 35 s, 40 s, 45 s, or any period there in between.

In a preferred embodiment, the present invention provides a process according to the first aspect of the invention, wherein said porous layer (2b) is predominantly formed by electrochemical etching at a voltage between 4 V and 6 V, not including 4

V and 6 V, more preferably between 4.25 V and 5.75 V, more preferably between 4.5

V and 5.5 V, even more preferably between 4.75 V and 5.25 V, and most preferably at a voltage of about 5 V. The inventors found that electrochemical etching at this specific voltage allowed for optimal morphology of the pores formed, i.e. the formation of pores having a mixed morphology. The inventors also found that electrochemical etching at a voltage of 4 V lead to the formation of pores with a crystallographic morphology, i.e. a morphology in the direction of the crystal orientation, growing in 111 A direction: pore walls with 111 B surfaces, pore tips in 111 A direction. Such pores have a triangular shape. The inventors also found that electrochemical etching at a voltage of 6 V lead to the formation of pores with a current-oriented morphology, i.e. a morphology in the direction of the electrical current: growing parallel in 100 direction. Such pores are hexagonally closed packed and have a round shape. In the preferred embodiment, electrochemical etching at a voltage of about 5 V lead to the formation of pores with a mixed morphology: growing randomly in 100 or 111B direction, and having a roundish or triangular shape. The inventors found that etching under such conditions allowed for most efficient pore etching and is most efficient for forming a porous layer. Such pores are found to have less transport limitations.

In a preferred embodiment, the present invention provides a process according to the first aspect of the invention, wherein said porous layer (2b) is formed by electrochemical etching, and whereby at the final stage of the formation of the porous layer (2b) a region of increased porosity is formed by temporarily electrochemical etching at an increased voltage. Temporarily electrochemical etching at an increased voltage allows for the formation of a controlled structural weakness or a line of controlled breakage. Said increased voltage is preferably between 7 V and 30 V, preferably between 10 V and 30 V. In this context, said temporarily etching can take up to 15 seconds, or can be intermittently up to 15 seconds, preferably up to 10 seconds and also preferably at least 1 second or at least 2 seconds.

In a preferred embodiment, the present invention provides a process according to the first aspect of the invention, wherein said porous layer (2b) is formed to have a volume porosity of not more than 20%, as determined by SEM, preferably not more than 15%, such as lower than 10% or even lower than 5%. Preferably, said porosity is not lower than 0.1%, and higher than 0.5%, and even higher than 1.0%

In a preferred embodiment, the present invention provides a process according to the first aspect of the invention, whereby:

- said substrate is provided with a porous layer (2b, 2c) of InP, the porous layer extending over the substrate layer (2a), the porous layer comprising a higher porosity sublayer (2c) and a lower porosity sublayer (2b) with a volume porosity lower than a volume porosity of the higher porosity sublayer (2c), the lower porosity sublayer (2b) extending between the substrate layer (2a) and a substrate side of the higher porosity sublayer (2c); - providing the semiconductor wafer with an exposed low porosity surface of InP facing away from the substrate layer, said providing comprising the step of removing the higher porosity sublayer (2c) and exposing the lower porosity sublayer (2b).

In a preferred embodiment, the present invention provides a process according to the first aspect of the invention, wherein:

- said providing a porous layer comprises electrochemical etching the substrate layer, thereby obtaining an InP homo-composition structure comprising substrate layer (2a) and the porous layer (2b, 2c); and

- said removing the higher porosity sublayer (2c) comprises chemical-mechanical polishing of the porous layer (2b, 2c) to a depth where the lower porosity sublayer (2b) is exposed.

In a preferred embodiment, the present invention provides a process according to the first aspect of the invention, comprising:

- bringing the exposed lower porosity surface in contact with a surface layer of a foreign substrate, the foreign substrate comprising a substrate layer of GaAs or GaP or Ge, and thermally bonding the low porosity layer to the surface layer of the foreign layer to form a thermally bonded substrate.

- separating the porous layer from one or more layers of the semiconductor substrate, whereby at least the substrate layer (2a) is separated from the thermally bonded substrate, thereby obtaining a substrate with a layer stack comprising a substrate layer (1) of GaAs or GaP or Ge and a porous InP surface layer (2b).

In a preferred embodiment, the present invention provides a process according to the first aspect of the invention, further comprising growing an epitaxial InP semiconductor layer (3) on top of the porous InP surface layer (2b). In a preferred embodiment, the present invention provides a process according to the first aspect of the invention, whereby the porous layer (2b) is formed by electrochemical etching of an InP substrate, whereby the difference between applied voltage and open circuit voltage is kept constant.

In a preferred embodiment, the present invention provides a process according to the first aspect of the invention, whereby the electrochemical etching comprises subjecting the InP substrate to an electrochemical pre-treatment, in which pre-treatment an etching current is increased linearly from 0 mA/cm² to at most 125 mA/cm² in period of less than 3 seconds.

In a more preferred embodiment, the present invention provides a process according to the first aspect of the invention, wherein at the end of said period the etching current is reduced to 0 mA/cm².

In a preferred embodiment, the present invention provides a process according to the first aspect of the invention, whereby the highly porous layer (2c) is subjected to the chemical-mechanical polishing using a slurry comprising an alkaline aqueous solution at pH between 9 and 12 and silica nanoparticles.

In a third aspect, the present invention provides a compound semiconductor layered structure obtained by a process according to the second aspect of the invention.

EXAMPLES

The following examples are intended to further clarify the preparation of the porous layers, and are nowhere intended to limit the scope of the present invention.

EXPERIMENT 1

An n-type sulphur-doped InP wafer is grown by liquid encapsulated Czochralski (LEC) with an epi-ready, polished and cleaned surface on both sides. The wafer was doped to have a charge carrier density of l-10¹⁷/cm³. The wafer is provided with a 2 inch diameter and a thickness of about 300 to 500 pm, and has a (100) orientation. The provided InP wafer was subject to electrochemical etching in a hydrochloric acid solution (3.5 wt.%) in absence of light. The etching cell has an O-ring cell design with high pump rate to maintain a consistent concentration of the electrolyte throughout the etching process. Potential applied to the InP wafer was as shown in FIG. 5 in the following sequence:

(1)A surface preparation was applied (t=0 until t=0.18 min in FIG. 5). Surface preparation consisted of repetitive applying a sequence of pulses of about 5 seconds and an interval of 1 second between successive sequences. Voltage applied was 4 V. Measured current was 0 mA/cm².

(2) A pre-treatment was performed (t=0.18 min to t = 0.22 min in FIG. 5). The etching potential was controlled to linearly increase the current from an initial current level of 0 mA/cm² to 50 mA/cm² in 2.4 s (0.04 min), and the current is stopped immediately when it reached 50 mA/cm².

(3) Pore nucleation and subsequent etching of a low porous layer was performed. Pore nucleation (t = 0.22 min to t = 0.35 min) consisted of applying a sequence of pulses of >10 V. Duration of the sequence was about 0.15 min, duty cycle was about 50%. An initial pulse with highest voltage (19 V) is followed by lower voltage pulses (16 V). Measured etching current varied during the pulses between 250 mA/cm² and 350 mA/cm². The pulses were followed by a long DC voltage period of slightly less than 0.5 min (t= 0.35 min to t = 0.86 min). Potential was about 6 V during this period, etching current started at about 150 mA/cm² to monotonically decrease to 50 mA/cm² at the end.

(4)A highly porous zip layer was prepared between the low porosity layer and the substrate layer (from t= 0.86 min until t= 1.0 min) . Two pulses of 30 V were applied for about 0.05 min. Etching current spiked for each pulse above 500 mA/cm² (measured 1100 mA/cm² and 750 mA/cm²) at the start of the pulse to monotonically decrease to 125 mA/cm².

Results are shown in Figs. 4 and 6. A compound semiconductor layered structure was obtained consisting of a InP monocrystalline substrate with a non-porous substrate layer and a porous surface layer with a porosity gradient, i.e. exhibiting a varying porosity from the front surface towards the bottom surface (see FIG. 4). A highly porous sublayer is on top and a lower porosity sublayer is situated below the highly porous sublayer, extending up to the non-porous substrate layer. The substrate layer is a non-porous substrate layer (not visible in FIG. 4). The lower porosity layer 2b is characterized by vertical channels, which are oriented in the direction of the current lines applied during electrochemical etching. The highly porous higher porosity layer 2c is characterized by a high porosity and three-four cell layers of cell. As is visible in FIG. 6, narrow line-shaped limited porosity areas are present, and outside those areas surface porosity is homogeneous.

EXPERIMENT 2

In this experiment, pre-treatment was omitted, but the wafer the same as in Experiment 1 and otherwise the same electrochemical etching was applied. Voltage and currents are shown in FIG. 7, a SEM image of the resulting wafer surface is shown FIG. 8.

As can be seen in FIG. 6, wide line-shaped limited porosity areas are present, and outside those areas porosity is not homogeneous. Non-porous area or spots are observed.

EXPERIMENT 3

In this experiment, electrochemical etching and wafer were the same as in Experiment 1, except as described below. Hence, pre-treatment was applied. Voltage and currents are shown in FIG. 9. A SEM image of the resulting wafer surface is shown FIG. 10.

The wafer was doped to have a charge carrier density of 1.5-10¹⁷/cm³, further having characteristics as described in Experiment 1. Voltages of the sequence of pulses (between t= 0.25 min and t= 0.4 min) applied after the pre-treatment were slightly lower than in Experiment 1, with the first pulse being 15 V, and the subsequent pulses being 14 V. Etching current in the sequent started with a low first pulse, of about 50 mA/cm² (ignoring the overshoot at the start and end of the pulse), and each of the successive pulses being higher than its directly preceding pulse, successively being 175 mA/cm², 300 mA/cm², 350 mA/cm² and 400 mA/cm².

As shown in FIG. 10, porosity is homogenous over the surface and no line-shaped limited porosity areas are present. Discussion of experiments

From the experiments it is clear that the pre-treatment significantly increases homogeneity of the porous surface. This makes subsequent processing easier. Also, it surprisingly shows that the increased doping results in a more homogeneous porosity. Most surprisingly, it shows that the combination of pre-treatment with a doping in the range of 1 to 1.7-10¹⁷/cm³ gives a very good homogeneity.

Removing top layer

After providing the porous layer, the higher porosity sublayer is removed and the lower porosity sublayer layer 2b is exposed The higher porosity sublayer may for example be removed by chemical-mechanical polishing the front surface.

The chemical-mechanical polishing can for example be performed using a slurry comprising nanoparticles, such as SiOz particles of 250 nm in size, and a basic solution with a pH of between 9 and 12, preferably at a pH of about 11. It is found that such a solution has good selectivity to the higher porosity sublayer and allows to remove that layer without affecting the lower porosity sublayer. In particular, it has been found that such a layer does not chemically etch bulk InP and accordingly is particularly advantageous for selectively etching porous layers on a non-porous InP substrate layer. The slurry may for example comprise a solution with potassium hydroxide (KOH) and SiOz nanoparticles. It is further observed that CMP can widen the pore diameter close to the surface, which does not affect bonding but is highly relevant for CVD/MOCVD. Therefore, a purely mechanical polishing with SiOz particles of 250 nm in size is better for MOCVD. Also, for mechanical polishing, a water-based diamond suspension DiaPro Nap ¹/4 (Struers) and polishing cloth MD-Nap, a soft synthetic fibre cloth can be used.

EXPERIMENTS

EXPERIMENT 4

The following examples are intended to further clarify the removal of the highly porous sublayer, and are nowhere intended to limit the scope of the present invention. The porous wafer obtained in Experiment 1 was subject to chemical-mechanical polishing (CMP) with Nanopure NP6230 Slurry. As polishing cloth a Suba polishing pad as available from DuPont, was used. Polishing was performed for 15 min, with a polishing force of 25 N at 100 rpm.

FIG. 11 shows a SEM image of the resulting surface near the axial centre of the wafer. The low porosity sublayer was observed to be exposed and porous. In FIG. 11 scratch marks (the lines) from the CMP process are visible. Accordingly, after e.g. layer transfer, traces of the process used to remove the highly porous sublayer are still present.

After exposing the lower porosity sublayer, the wafer comprises the substrate layer of the initial wafer and an exposed porous surface layer. In this example, the wafer still has all the layers of the initial wafer in addition to the porous surface layer. The wafer may be subject to further treatments, such as cleaning to clean particulates and residues from the surface, thinning, and/or planarization.

After removing the higher porosity sublayer and exposing the lower porosity layer, the wafer can be used as a compound wafer The wafer may be used as an initial substrate in fabricating semiconductor devices and e.g. be subject to processes to form a variety of patterned and un-patterned insulating, semi-conductive and conductive device regions and layers. For instance, the finished engineered wafer may be subjected to end of line metrology inspections and cleaned a final time. These steps may be omitted and exposing the porosity layer may be sufficient to finalize the engineered wafer.

In the shown example, after removing the top layer, the wafer is an intermediate product and subsequent processing is performed to obtain another type of composite, compound wafer. In this example, the intermediate product is used as a donor wafer in a layer transfer process in which at least the porous layer is transferred to a foreign wafer.

Bonding to foreign wafer In this example, the porous layer is transferred from the initial wafer to a foreign semiconductor wafer. For instance, the porous layer can be transferred on the foreign substrate, which thus after transferring forms the substrate layer, to the exposed front surface or to the exposed backside surface, also referred to as the bottom surface, of the foreign wafer. As part of the layer transfer, the exposed low porosity surface can be bonded to an exposed surface of the foreign substrate. As a result, bonded wafer with a composite layer structure comprising the initial substrate or wafer (hereinafter referred to as the donor wafer), the porous layer and the foreign substrate is obtained.

Although other bonding processes may be suitable to form a bonded wafer, the donor wafer may be bonded to the foreign substrate by thermally bonding the two. For instance, the donor wafer and the foreign wafer may be placed with the exposed porous surface contacting the bottom surface or front surface of the foreign wafer, thereby initiating bonding by Van der Waal's forces, followed by a thermal treatment to strengthen the bond. The thermal treatment may convert the bonds between the materials of the two interfaces, thereby strengthening the bond.

In the shown example, the top surfaces of the donor wafer and the foreign wafer are brought to contact each other and the wafers are pressed together, resulting in a bond between donor wafer and the foreign wafer at the interface between the former top layers of the wafers. The mechanical bond can in such a case be held together by van der Waal's forces, The bonded structure is further annealed to solidify the bond between the donor wafer and the foreign wafer.

In some preferred embodiments, the bonded structure is annealed at a temperature of from about 100°C to about 250°C, from about 125°C to about 200°C, preferably about 150°C. Thermal annealing may occur for a duration of from about a few minutes to about 10 hour, preferably a duration of about 1 hour. Thermal annealing within these temperatures ranges is sufficient to form a thermal bonding interface between the former exposed surface of the porous layer and the respective surface of the foreign wafer.

The foreign wafer can be a single crystal semiconductor substrate, e.g. a single crystal semiconductor wafer. In preferred examples, the semiconductor wafer comprises a semiconductor material selected from the group consisting of germanium, gallium arsenide, gallium phosphide, and indium phosphide and combinations. Preferably, both the foreign substrate and the donor substrate have a zincblende type crystal lattice (cubic close packed) or other face centred cubic lattice. Depending upon the desired properties of the final integrated circuit device, the single crystal semiconductor foreign wafer may be doped with an n- or p-type dopant. The single crystal semiconductor foreign wafer may an un-patterned wafer but be subject to standard process steps such as implant, and post implant cleaning and surface activation, prior to bonding.

Separating foreign wafer from donor wafer

After bonding of the donor wafer to the foreign substrate, a portion of the donor wafer can be separated from the bonded wafers. For example, the substrate layer of the donor wafer may be physically separated from the porous layer. The resulting foreign wafer then comprises the foreign substrate and a porous layer which forms the front surface or the bottom surface of the foreign wafer. The resulting substrate is suitable for use in the manufacture of semiconductor devices. The wafer may be used as an initial substrate in fabricating semiconductor devices and e.g. be subject to processes to form a variety of patterned and un-patterned insulating, semi-con- ductive and conductive device regions and layers.

The separation may comprise mechanically lifting the initial wafer off the porous layer. In the example, after the thermal bonding described above, the bond between the single crystal semiconductor donor substrate and the wafer is strong enough to initiate layer transfer via cleaving the bonded structure at a cleave plane. The donor wafer is thereby cleaved along the cleave plane defined by the zip layer, but other separation techniques may be used. For example, a mechanically locally weakened plane may be formed by ion implant at a depth corresponding to the desired separation plane or laser lift-off or other separation techniques may be used. Cleaving may be carried out by placing the bonded wafer in a fixture in which mechanical force is applied perpendicular to the opposing sides of the bonded wafer in order to pull a portion of the donor wafer apart from the bonded wafer. According to some methods, suction cups can be utilized to apply the mechanical force. The separation of the portion of the donor wafer can e.g. be initiated by applying a mechanical wedge at the edge of the bonded wafer at the cleave plane in order to initiate propagation of a crack along the cleave plane. The mechanical force applied by the suction cups then pulls the portion of the donor wafer from the bonded wafer, thus forming an composite wafer, with in this example a compound semiconductor substrate and a porous top layer. Cleaving removes a portion of the donor wafer, thereby leaving one or more layers thereof, including the porous layer, on the foreign substrate. As a result the foreign substrate is provided with one or more additional layers from the donor substrate and has a composite layer structure.

The removed non-porous portion of the donor substrate may be reused to e.g. to form another porous layer and perform the described process illustrated in FIGs. 3(a)-(c) again, optionally followed by the process of FIGs. 3(d)-(f) described above.

Further processing of engineered substrate

After separation, the foreign wafer comprises the foreign substrate layer (e.g. a single crystal Ge wafer or a compound semiconductor wafer such as GaP, GaAs) and a porous surface layer (e.g. of InP). The foreign wafer with the transferred layer(s) may be subject to further treatments, such as annealing or other, to further strengthen the bond between the transferred layer(s) and the foreign wafer, cleaning to clean particulates and from the surface, thinning or planarization. In an example, after separation one or more unpatterned epitaxial layers 3 are grown, as described above and illustrated in FIG. 3(f). The finished engineered wafer may then be subjected to end of line metrology inspections and cleaned a final time. Also, a covering layer covering the exposed low porosity surface may be applied to temporarily protect the finished wafer, e.g. during transport.

In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein and that the specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.

For example, although in the shown examples the layers are shown in an idealized case where they extend parallel to a frontside surface of the semiconductor wafer and have a constant thickness, in a real world implementation the thickness of one or more layers may vary over the substrate and the layers may not be flat. Also, although the wafer is shown as a flat, un-bend, body with flat front and bottom surfaces, in some cases the wafer may exhibit bending and e.g. have a front and/or bottom surface which although planar are bend in one or two directions and not flat.

Furthermore, although directly after performing the method the semiconductor wafers are un-patterned and un-diced in the examples, in some implementations the wafers are immediately thereafter subject to forming devices therein. However, it is currently contemplated that the engineered wafers are provided by the manufacturer thereof to other parties which subsequently use them as a raw material for manufacturing semiconductor devices.

As a "semiconductor" any material may be used that has an intermediate-sized, nonzero band gap that behaves as an insulator at T=0K but for which at temperatures that are below its melting point, and more specifically at the intended operating temperature (e.g. above -20°C, for example above 0°C and/or below 100°C such as below 50°C, for example below 30°C), some states in the conduction band are occupied, resulting in an electrical conductivity between that of an insulator and that of most metals. An example semiconductor layer is composed of a single semiconductor, such as Germanium (Ge) or a compound semiconductor as explained below. The semiconductor may be a doped or undoped semiconductor.

As a "compound semiconductor" any a semiconductor composed of chemical elements of at least two different species may be used, such as Group III and V elements and Group II and VI elements. These semiconductors typically form in periodic table groups 13-15 (old groups III— V), for example of elements from the Boron group (old group III, boron, aluminium, gallium, indium) and from group 15 (old group V, nitrogen, phosphorus, arsenic, antimony, bismuth). The compound semiconductor can e.g. be a binary (two elements, e.g. Indium phosphide (InP), gallium (III) arsenide (GaAs), ), ternary (three elements, e.g. indium gallium arsenide (InGaAs)) or quaternary (four elements, e.g. aluminium gallium indium phosphide (AlInGaP)) alloys. Typical compound semiconductors are:

Group II-VI : ZnSe

Group III-V: GaAs, GaN, InP, InGaAlP, InGaN Group IV-IV: SiC, SiGe

As a "substrate" or "semiconductor substrate" any type of body can be used onto which deposited layers of a material may be formed or applied to form semiconductor devices, such as with a bulk or substrate layer of semiconductor material, preferably with a porous top surface layer of a compound semiconductor material. Preferably, the substrate is mono-crystalline. The semiconductor substrate may be a wafer, a wafer die or other plate-shaped type of substrate used as a substrate onto which microelectronic devices can be built (which for conciseness are all referred to as "wafers"). Semiconductor substrates may be subjected to different processes such as doping, ion implantation, etching, thin-film deposition or lithographic patterning. A substrate may consist of a single substrate layer or comprise a stack with a substrate or bulk layer and one or more other layers.

Exemplary substrates which may be used include, without limitation: bulk germanium wafers, bulk InP wafers, bulk GaN wafers, bulk GaAs wafers, bulk Ga wafers, which comprise as a bulk layer a single-crystal layer of a homogeneous thickness; simple semiconductor wafers, comprising a substrate or bulk layer with a homogeneous thickness of a monocrystalline, polycrystalline, or amorphous, simple semiconductor, such as Ge. compound semiconductor wafers comprising a substrate or bulk layer with a homogeneous thickness of a monocrystalline, polycrystalline or amorphous compound semiconductor; composite or engineered wafers comprising a layer stack with a bulk layer of a simple or compound semiconductor and one or more layers on top of the bulk layer. Two or more layers may form a homo-composition structure, with layers of the same material and crystal structure but e.g. with different porosity such as a non-porous bulk layer and a porous surface layer, preferably both of InP. Alternatively, two or more of the layers may form a hetero-composition structure of layers of different materials and/or crystal structure, such as a InP on x wafer that comprises a layer of InP that is disposed on a bulk layer of homogeneous thickness of a different, simple or compound, semiconductor material, which may be monocrystalline, polycrystalline or amorphous. The homo-composition or hetero-composition layer stack may form a heterostructure. Preferably, the semiconductor substrate comprises a bulk layer comprising a material selected out of the group consisting of Ge, InP, GaP, GaAs, GaN. More preferably, the bulk layer consists essentially of this material, e.g. of such a material and the composite wafer has a surface layer of porous InP.

However, other modifications, variations and alternatives are also possible.

Unless otherwise defined, all terms, including technical and scientific terms, have the meaning as commonly understood by one of ordinary skill in the art of semiconductor processing. By means of further guidance, term definitions are included to better appreciate the teaching of the present invention.

As used herein, the following terms have the following meanings:

"A", "an", and "the" as used herein refers to both singular and plural referents unless the context clearly dictates otherwise, in the sense of "one, or more than one". The use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to embodiments containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an."

"About" as used herein referring to a measurable value such as a parameter, an amount, a temporal duration, and the like, is considered synonymous to the term "substantially" and is meant to encompass variations of +/-20% or less, preferably +/-10% or less, more preferably +/-5% or less, even more preferably +/-1% or less, and still more preferably +/-0.1% or less of and from the specified value, in so far such variations are appropriate to perform in the disclosed invention. However, it is to be understood that the value to which the modifier "about" refers is itself also specifically disclosed.

"Comprise," "comprising," and "comprises" and "comprised of" as used herein are synonymous with "include", "including", "includes" or "contain", "containing", "contains" and are inclusive or open-ended terms that specifies the presence of what follows e.g. component and do not exclude or preclude the presence of additional, non-recited components, features, element, members, steps, known in the art or disclosed therein. The recitation of numerical ranges by endpoints includes all numbers and fractions subsumed within that range, as well as the recited endpoints. All percentages are to be understood as percentage by weight, abbreviated as "wt.%" or as volume per cent, abbreviated as "vol.%", unless otherwise defined or unless a different meaning is obvious to the person skilled in the art from its use and in the context wherein it is used.

The terms "front," "back," "top," "bottom," "over," "under" and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

Terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements

In the context of the present invention, the term "substrate" generally refers to a material having a thickness of at least 1 pm. Semiconductor substrates as used in the context of the present invention may for example have: a wafer size of 1-inch (25 mm) and having a thickness of typically around 275 pm; a wafer size of 2-inch (51 mm) and having a thickness of typically around 275 pm; a wafer size of 3-inch (76 mm) and having a thickness of typically around 375 pm; a wafer size of 4-inch (100 mm) and having a thickness of typically around 525 pm; a wafer size of 5-inch (125 mm) and having a thickness of typically around 625 pm; a wafer size of 6-inch (150 mm) and having a thickness of typically around 675 pm; a wafer size of 8-inch (200 mm) and having a thickness of typically around 725 pm; a wafer size of 12-inch (300 mm) and having a thickness of typically around 775 pm.

In the context of the present invention, the term "film" or "semiconductor film" refers to a semiconductor material having a substantially-uniform thickness of a material covering a surface. A film can have a porous or a nonporous structure. In the context of the present invention, the term "film" refers to a material having a thickness of 0.01 pm to 1 pm. In the context of the present invention, the term "layer" or "semiconductor layer" refers to a semiconductor material having a substantially-uniform thickness of a material covering a surface. A layer can be either continuous or discontinuous (i.e. having gaps between regions of the material). For example, a layer can completely or partially cover a surface, or be segmented into discrete regions, which collectively define the layer (i.e. regions formed using selective-area epitaxy). Furthermore, a layer can have a porous or a nonporous structure. In the context of the present invention, the term "layer" refers to a material having a thickness of at least 1 pm and at most 800 pm.

A first layer or a first film described and/or depicted herein as "configured on," "deposited on," "on top of," "on" or "over" a second layer or a second film can be immediately adjacent to the second layer, i.e. contact the second layer or film, or one or more intervening layers can be between the first and second layers or films. In a preferred embodiment of the invention, the first layer or a first film is in direct contact with or bonded with or directly to the second layer or the second film. In the context of the present invention, the term "disposed on" means "exists on" an underlying material or layer. This underlying layer may comprise intermediate layers, such as transitional layers, necessary to ensure a suitable surface. For example, if a material is described to be "disposed on a substrate," this can mean either that the material contacts the substrate; or that the material is separated from the substrate by one or more intermediate layers that reside on the substrate.

In the context of the present invention, the term "in direct contact with" is synonymous for the terms "adhered directly to," "bonded directly to," "in direct contact with" and is to be understood as two distinct layers which are distinguishable, e.g. from cross-sectional SEM image analysis, by layer boundaries. The two distinct layers may be connected to each other or bonded to each other, with or without use of a bonding agent such as an organic or inorganic gluing agent. The distinct layers may have similarities, such as have the same composition, crystallinity, porosity. For example, distinct layers may form a mono-crystalline structure but differ in porosity, such as single crystal wafer with a non-porous bulk layer, also referred to as substrate layer, and a porous top layer with an exposed surface. In the context of the present invention, the volume porosity of a material is expressed as volume per cent, abbreviated as "vol.%" or as "%." In the context of the present invention, the term "porous" refers to a layer or film comprising pores, whereby the void volume of the layer or film is at least 1 vol.% of the total volume of the layer or film. Typically, unless specified otherwise, the void volume of a porous layer is up to 30%, 40%, 50%, 60%, or even up to 70%. In the context of the present invention, the term "nonporous" refers to a layer or film preferably devoid of pores or a layer or film having a porosity of at most 1%, preferably at most 0.8%, more preferably at most 0.5% and most preferably 0%.

In the context of the present invention, porosity of a layer or a film can be determined by SEM analysis of the layer or film during multiple stages of an electrochemical etching process. The degree of porosity is analysed with an OpenCV image analysis library, using denoising and adaptive Gaussian image thresholding to determine the degree of porosity.

In the context of the present invention, the term "surface" refers to a two-dimensional outer face or exterior boundary of a body or part of a body, e.g. a layer; the term "surface area" refers to the size of the surface; and the term "surface layer" refers to an exposed, three-dimensional outer layer or exterior boundary of a body or part of a body, e.g. a layer. Hence, in the context of the present invention, the term 'surface' is distinguished from the term 'surface area' and from the term 'surface layer.' A surface is referred to as a "front surface" or a "back surface" merely for convenience and generally to distinguish between the surfaces of the substrate.

Any of the structures depicted and described herein can be part of larger structures with additional layers above and/or below those depicted. For clarity, the figures herein can omit these additional layers, although these additional layers can be part of the structures disclosed. In addition, the structures depicted can be repeated in units, even if this repetition is not depicted in the figures.

The growth and/or deposition described herein may be performed using one or more of chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), organometallic vapor phase epitaxy (OMVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE), halide vapor phase epitaxy (HVPE), pulsed laser deposition (PLD), and/or physical vapor deposition (PVD).

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

In conclusion, in a first aspect, the present invention provides a compound semiconductor wafer, comprising a composite layer structure with a stack (2) of layers (2a, 2b), said stack comprising: a substrate layer of a semiconductor material, the semiconductor material being one of the group consisting of GaAs and GaP and Ge; a porous layer extending over the substrate layer, the porous layer being of InP and having one or more or all of the following: i. the porous InP layer having a surface porosity, at a porous surface facing away from the substrate layer, of not more than 50%, as determined by SEM; ii. the porous InP layer having a volume porosity of not more than 10%, as determined by SEM; iii. the porous InP layer is provided with tubular and triangular pores which extend from the porous surface towards the substrate layer, more specifically features ii. and/or iii.

In a preferred embodiment, the invention provides a compound semiconductor wafer as disclosed above, in which the porous layer (2b) has (ii) and the volume porosity is not more than 5%, as determined by SEM.

In a preferred embodiment, the invention provides a compound semiconductor wafer as disclosed above, wherein the porous surface layer (2b) has (iii) and the tubular, the triangular or the mixed pores extend perpendicular to the exposed surface towards.

In a preferred embodiment, the invention provides a compound semiconductor wafer as disclosed above, wherein the porous surface has (i) and the tubular pores extend from a pore entrance located at the porous surface into the porous layer, and the pore entrances have a median diameter in the range of 70 nm to 150 nm.

In a preferred embodiment, the invention provides a compound semiconductor wafer as disclosed above, wherein some or all of the tubular pores are branched, and the branched pore or pores branch in a direction from the substrate layer towards the porous surface, or vice versa.

In a second aspect, the present invention provides a process of preparing a composite semiconductor structure, comprising: providing a semiconductor substrate which has a substrate layer (2a) of InP; providing the substrate with a porous layer (2b, 2c) of InP, the porous layer extending over the substrate layer (2a), the porous layer comprising a higher porosity sublayer (2c) and a lower porosity sublayer (2b) with a volume porosity lower than a volume porosity of the higher porosity sublayer (2c), the lower porosity sublayer (2b) extending between the substrate layer (2a) and a substrate side of the higher porosity sublayer (2c); providing the semiconductor wafer with an exposed low porosity surface of InP facing away from the substrate layer, said providing comprising partially removing the porous layer and exposing the lower porosity sublayer.

In a preferred embodiment, the invention provides a process as disclosed above, wherein: said providing a porous layer comprises electrochemical etching the substrate layer, thereby obtaining an InP homo-composition structure com-prising substrate layer (2a) and the porous layer (2b, 2c); said partially removing the porous layer comprises chemical-mechanical polishing of the porous layer (2b, 2c) to a depth where the lower porosity sublayer (2b) is exposed.

In a preferred embodiment, the invention provides a process as disclosed above, comprising: bringing the exposed lower porosity surface in contact with a surface layer of a foreign substrate, the foreign substrate comprising a substrate layer of GaAs or GaP, and thermally bonding the low porosity layer to the surface layer of the foreign layer to form a thermally bonded substrate.

In a preferred embodiment, the invention provides a process as disclosed above, comprising: separating the porous layer from one or more layers of the semiconductor substrate, whereby at least the substrate layer (2a) is separated from the thermally bonded substrate, thereby obtaining a substrate with a layer stack comprising a substrate layer (1) of GaAs or GaP and a porous InP surface layer (2b).

In a preferred embodiment, the invention provides a process as disclosed above, further comprising growing an epitaxial InP semiconductor layer (3) on top of the porous InP surface layer (2b).

In a preferred embodiment, the invention provides a process as disclosed above, whereby the porous layer (2b) is formed by electrochemical etching of an InP substrate, whereby the difference between applied voltage and open circuit voltage is kept constant.

In a preferred embodiment, the invention provides a process as disclosed above, whereby the electrochemical etching comprises subjecting the InP substrate to an electrochemical pre-treatment, in which pre-treatment an etching current is increased linearly from 0 mA/cm² to at most 125 mA/cm² in period of less than 3 seconds.

In a preferred embodiment, the invention provides a process as disclosed above, wherein at the end of said period the etching current is reduced to 0 mA/cm².

In a preferred embodiment, the invention provides a process as disclosed above, whereby the highly porous layer (2c) is subjected to the chemical-mechanical polishing using a slurry comprising an alkaline aqueous solution at pH between 9 and 12 and silica nanoparticles.

In a third aspect, the present invention provides a compound semiconductor layered structure obtained by the aforementioned process.

Claims

1. A compound semiconductor multilayered structure comprising:

2. Compound semiconductor multilayered structure according to claim 1, in which the porous layer (2b) has a volume porosity is not more than 10%, as determined by SEM, preferably not more than 5%.

3. Compound semiconductor multilayered structure according to claim 1 or 2, in which the porous layer (2b) has a thickness between 1 and 50 pm, as determined by SEM, preferably between 5 and 50 pm.

4. Compound semiconductor multilayered structure according to any of claims 1 or 3, wherein the porous layer (2b) has mixed pores extending perpendicular to the exposed surface, and wherein said mixed pores have a morphology intermediate to current line oriented pores and crystallographically oriented pores.

5. Compound semiconductor multilayered structure according to any of claims 1 to 4, wherein the porous layer (2b) has pores extending from a pore entrance located at the porous surface into the porous layer (2b), and the pore entrances have a median diameter in the range of 70 nm to 150 nm.

6. Compound semiconductor multilayered structure according to any of claims 1 to 5, wherein said substrate layer (2a) consists of InP.

7. Compound semiconductor multilayered structure according to any of claims 1 to 5, wherein said substrate layer (1) consists of a material selected of the group consisting of GaAs, GaP and Ge, preferably of the group consisting of GaAs and GaP.

8. A process of preparing a composite semiconductor multilayered structure, comprising the step of:

- electrochemical etching of an InP compound semiconductor substrate, thereby forming a porous layer (2b) of InP, the porous layer extending over the substrate layer (2a), said porous layer having a volume porosity of not more than 20%, as determined by SEM.

9. Process of claim 8, wherein said porous layer (2b) is formed by electrochemical etching at a voltage between 4 V and 5 V, preferably at a voltage of about 5 V.

10. Process of claim 8 or 9, wherein said porous layer (2b) is formed to have a volume porosity of not more than 10%, as determined by SEM, preferably not more than 5%.

11. Process of any of claims 8 to 10, whereby:

- said substrate is provided with a porous layer (2b, 2c) of InP, the porous layer extending over the substrate layer (2a), the porous layer comprising a higher porosity sublayer (2c) and a lower porosity sublayer (2b) with a volume porosity lower than a volume porosity of the higher porosity sublayer (2c), the lower porosity sublayer (2b) extending between the substrate layer (2a) and a substrate side of the higher porosity sublayer (2c);

- providing the semiconductor wafer with an exposed low porosity surface of InP facing away from the substrate layer, said providing comprising the step of removing the higher porosity sublayer (2c) and exposing the lower porosity sublayer (2b).

12. Process according to claim 11, wherein:

- said providing a porous layer comprises electrochemical etching the substrate layer, thereby obtaining an InP homo-composition structure comprising substrate layer (2a) and the porous layer (2b, 2c); and said removing the higher porosity sublayer (2c) comprises chemical-mechanical polishing of the porous layer (2b, 2c) to a depth where the lower porosity sublayer (2b) is exposed.

13. Process of claim 11 or 12, comprising:

14. Process of claim 13, comprising:

15. Process of claim 14, further comprising growing an epitaxial InP semiconductor layer (3) on top of the porous InP surface layer (2b).

16. Process of any of claims 8 to 15, whereby the porous layer (2b) is formed by electrochemical etching of an InP substrate, whereby the difference between applied voltage and open circuit voltage is kept constant.

17. Process of any of claims 8 to 16, whereby the electrochemical etching comprises subjecting the InP substrate to an electrochemical pre-treatment, in which pre-treatment an etching current is increased linearly from 0 mA/cm² to at most 125 mA/cm² in period of less than 3 seconds.

18. Process of claim 17, wherein at the end of said period the etching current is reduced to 0 mA/cm².

19. Process of any of claims 11 to 18, whereby the highly porous layer (2c) is subjected to the chemical-mechanical polishing using a slurry comprising an alkaline aqueous solution at pH between 9 and 12 and silica nanoparticles.

20. A compound semiconductor layered structure obtained by a process of any of claims 8 to 19.