EP4652672A1 - Combination of balanced amplifiers for resilience to load impedance variation - Google Patents

Abstract

The resilience of RF power amplifiers (PA) to varying load impedance mismatches is improved by topologies of multiple balanced PAs combined with delay lines to spread phase offsets around a VSWR circle (i.e., over the full range of phase values). Balanced PA circuits – comprising two parallel PAs operating in quadrature with their outputs combined by a Quadrature Hybrid Coupler (QHC) – are arranged in parallel. Delay lines are inserted between the outputs of some or all parallel balanced PAs and the load. The phase offsets introduced by the delay lines, in combination with the inherent 90° phase separation of the PAs, distribute the PAs around a VSWR circle on a Smith Chart. The PAs thus compensate each other, with peak outputs at different impedance phases, yielding a consistent overall RF signal over the full range of impedance mismatch values. The scheme is scalable to more than two balanced amplifiers, allowing for the parallelization of more PAs. In some aspects, the termination impedance at the isolated port of the QHCs may be controlled to cover cases where the circuit requires reconfigurability.

Description

COMBINATION OF BALANCED AMPLIFIERS FOR RESILIENCE TO LOAD IMPEDANCE VARIATION

FIELD OF DISCLOSURE

The present disclosure relates generally to power amplifiers for antenna arrays, and in particular to mitigation of load impedance variations by combining the phase shift of a balanced amplifier with delay lines to distribute impedance phase over the amplifiers.

BACKGROUND

Wireless communication networks are ubiquitous in many parts of the world. These networks continue to grow in capacity and sophistication. To accommodate more users, different types of devices, and different use cases, the technical standards governing the operation of wireless communication networks continue to evolve. The fourth generation (4G) of network standards has been deployed, the fifth generation (5G) is in development and early deployment, and the sixth generation (6G) is in design. With each generation, technological advances improve the capacity and spectral efficiency of the wireless communication system. For example, 5G added new frequency bands, and applied beamforming. This trend is expected to continue in 6G by exploiting additional frequency bands, and applying more advanced beamforming.

5G added a second frequency range, FR2. This provided significant new available spectrum in the range 24.25-52.6 GHz. In this frequency range, beamforming is utilized to improve both coverage and capacity. Because the wavelengths are small at these high frequencies, antenna arrays with hundreds, or even thousands, of antenna elements are feasible.

The Advanced Antenna System (AAS) is a combination of AAS radio and AAS features. AAS radio refers to large antenna arrays of individual antenna elements, together with circuitry such as Phase Locked Loops (PLLs) that provide Radio Frequency (RF) signals with phase control, and RF drivers, including Power Amplifiers (PA). AAS Features refers to multi-antenna features, such as beamforming and Multiple Input, Multiple Output (MIMO) techniques, including spatial diversity and spatial multiplexing, that are executed in the AAS radio.

Spatial diversity refers to transmitting the same signal on different propagations paths (e.g., different transmit/receive antennas), which increases robustness against fading, cochannel interference, and other deleterious effects of RF signal transmission. Spatial multiplexing also uses multiple transmit and receive antennas, and refers to transmitting different portions of data on different propagation paths, using space-time coding, to increase data rates.

Beamforming refers to the use of antennas having increased and controllable directionality, whereby an RF transmission is narrow, and is “aimed” in a specific direction. This is enabled by transmitting or receiving signals with controlled relative phase and gain in the antenna elements (or subarrays of antenna elements). The relative phases of, e.g., transmit signals sent to each antenna element are controlled to create constructive or destructive interference, thus amplifying the signal in some directions, and attenuating it in others, and hence controlling the direction in which the beam is transmitted. Similar phase manipulation of signals from antenna elements (or subarrays) in a receive antenna can also result in beamforming the sensitivity of an antenna array in receiving signals. Also, multiple orthogonal beams can be formed and aimed in different directions, thus simultaneously addressing multiple wireless devices, also known as User Equipment (UE).

To form robust beams, antenna elements are normally placed tightly together. For example, a distance of A/2 is commonly used (where A is the RF wavelength), to form arbitrary beams without folding. However, the tight antenna spacing causes high electromagnetic coupling between the antennas, and additionally signals leak in between the antennas. The beamsteering, combined with the antenna coupling, makes the impedance seen by each power amplifier (PA) driving the antenna elements (or subarrays) deviate from a designed impedance.

The PA is designed assuming a nominal load impedance for optimal output power, linearity, and efficiency. The PA amplifies and delivers electrical power to the antenna element/subarray, which converts it to an electromagnetic signal. However, if the load impedance seen by the PA diverges from its designed (optimum) value, there is an impedance mismatch, which degrades PA performance.

To direct a beam to a desired direction, a phase shift is required between signals sent to different antenna elements (or subarrays). The same signal, except for the phase shift, is present at all antenna elements, and electromagnetic energy of the signal leaks between them. This is seen by the PAs as a mismatch from an optimal (matched) impedance, which is not present when no phase shifts are introduced to steer the beam. The designed impedance seen by the PA is referred to as the impedance in the boresight direction (/.e., where the RF signal is radiated normal to the plane of the antenna element). When coupling is present between the antenna elements (due to spacing), and the same signal is sent on all antennas, but with different phases, this is experienced by the PA as load impedance variation and mismatch, even though it originates from antenna leakage and to the delay introduced by the phase shifter (/.e., the mismatch typically grows higher as the beam-angle increases, since the relative phase shift between antennas increases). Because the impedance mismatch causes a partial reflection of the RF signal from the antenna element (or subarray) back toward the PA, a standing wave is generated along the transmission line connecting the two. This is quantified in the art as an antenna impedance Voltage Standing Wave Ratio (VSWR), which is calculated in terms of the reflection coefficient or return loss (also known as the s11 parameter). Assuming the antenna and PA are impedance-matched for signals transmitted in the boresight direction, the active impedance load, or VSWR, typically grows higher as the beam-angle increases, since the relative phase shift in between antenna elements (or subarrays) increases.

At low frequencies, an isolator can be inserted in between a PA and its antenna element/subarray, to ensure that the VSWR is not transferred to the PA. In high frequency AAS, there is no room to fit an isolator at each PA output.

The PA typically is impedance matched in the boresight direction to optimize efficiency. Also, the PA is operated close to its compression point to maximize efficiency. The boresight impedance match degrades as the system performs beamforming, effectively presenting a time-varying load to the PA. The time-varying impedance mismatch is expressed as VSWR, which degrades the output power, efficiency, and linearity of the PA, which in turn deleteriously effects the phased-array beam and its directional control.

The Background section of this document is provided to place aspects of the present disclosure in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Approaches described in the Background section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.

SUMMARY

The following presents a simplified summary of the disclosure in order to provide a basic understanding to those of skill in the art. This summary is not an extensive overview of the disclosure and is not intended to identify key/critical elements of aspects of the disclosure or to delineate the scope of the disclosure. The sole purpose of this summary is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.

According to one or more aspects of the present disclosure described and claimed herein, the resilience of RF PAs to varying load impedance mismatches is improved by topologies of parallel, balanced PAs combined with delay lines to spread phase offsets of the constituent PAs’ load impedances around a VSWR circle (/.e., over the full range of phase values). As described herein, a balanced PA is a circuit in which two parallel PAs operate in quadrature (/.e., with a 90° phase shift between them). The balanced PA further includes a Quadrature Hybrid Coupler (QHC) as a signal combiner at outputs of the PAs. The QHC combines the quadrature RF signals from the PAs into a single output signal, which drives an antenna element or a sub-array of antenna elements. In the case of impedance mismatch, some RF signal energy is reflected back to the PAs; in this case, the QHC acts as a quadrature splitter, imparting a 90° phase shift to the reflection - effectively placing the PAs’ load impedances at opposite positions on a VSWR circle, as plotted on a Smith Chart. To further spread the PAs’ load impedances PAs in phase, delay lines are selectively interposed between the outputs of some or all parallel balanced PAs and the load. In various circuit topologies disclosed herein, the spread of losses, and the characteristic impedance presented by the load, may be controlled. The use of delay lines offers the advantage of a reduced number of passives, compared to prior art line averaging schemes. The scheme may be scaled to more than two balanced amplifiers, allowing for the parallelization of more PAs, such as for higher power operation. Yet another aspect includes additional implementations of the termination impedance at the isolated port of the QHCs, which covers additional cases where the circuit requires reconfigurability.

One aspect relates to an amplifier circuit configured to drive an antenna element or sub-array of antenna elements with a Radio Frequency (RF) signal. The amplifier circuit includes at least two balanced power amplifiers connected in parallel. Each balanced power amplifier comprises two power amplifiers connected in parallel and operating in quadrature, and an output quadrature hybrid coupler connecting the outputs of the two power amplifiers into a single RF signal. The amplifier circuit also includes a delay line interposed between the output of at least one balanced power amplifier and the antenna element or sub-array. The delay line imparts a phase shift to the connected balanced power amplifier, with respect to at least one other balanced power amplifier.

Another aspect relates to a method of driving an antenna element or sub-array of antenna elements with an RF signal. The RF signal is amplified in each of at least two parallel balanced power amplifiers. Each balanced power amplifier comprises two power amplifiers connected in parallel and operating in quadrature, and an output quadrature hybrid coupler connecting the outputs of the two power amplifiers into a single RF signal. A phase shift is imparted to the output of at least one balanced amplifier. The outputs and phase-shifted outputs of the at least two balanced power amplifiers are combined. An antenna element or sub-array of antenna elements is driven with the combined RF signal.

Still another aspect relates to a wireless device operative in a wireless communication network. The wireless device includes an array of antenna elements; communication circuitry connected to the antenna array and configured to wirelessly communicate with one or more other network nodes; and processing circuitry operatively connected to the communication circuitry. The processing circuitry is configured to implement beamforming on the antenna array. The communication circuitry includes a plurality of amplifier circuits. Each amplifier circuit is configured to drive an antenna element or sub-array of antenna elements. Each amplifier circuit includes at least two balanced power amplifiers connected in parallel. Each balanced power amplifier comprises two power amplifiers connected in parallel and operating in quadrature, and an output quadrature hybrid coupler connecting the outputs of the two power amplifiers into a single RF signal. Each amplifier circuit further includes a delay line interposed between the output of at least one balanced power amplifier and the antenna element or sub-array. The delay line imparts a phase shift to the connected balanced power amplifier, with respect to at least one other balanced power amplifier.

Yet another aspect relates to a base station operative in a wireless communication network. The base station includes an array of antenna elements; communication circuitry connected to the antenna array and configured to wirelessly communicate with one or more other network nodes; and processing circuitry operatively connected to the communication circuitry. The processing circuitry is configured to implement beamforming on the antenna array. The communication circuitry includes a plurality of amplifier circuits. Each amplifier circuit is configured to drive an antenna element or sub-array of antenna elements. Each amplifier circuit includes at least two balanced power amplifiers connected in parallel. Each balanced power amplifier comprises two power amplifiers connected in parallel and operating in quadrature, and an output quadrature hybrid coupler connecting the outputs of the two power amplifiers into a single RF signal. Each amplifier circuit further includes a delay line interposed between the output of at least one balanced power amplifier and the antenna element or sub-array. The delay line imparts a phase shift to the connected balanced power amplifier, with respect to at least one other balanced power amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which aspects of the disclosure are shown. However, this disclosure should not be construed as limited to the aspects set forth herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout.

FIG. 1 depicts an exemplary array of 64 antenna elements, wired into 32 2x1 subarrays.

FIG. 2 is a hardware block diagram of a Radio Frequency Integrated Circuit (RFIC) transceiver for connection to 32 subarrays of antenna elements.

FIG. 3A is a schematic diagram of a Quadrature Hybrid Coupler. FIG. 3B is a Smith chart plot of a 40GHz signal applied to a QHC with a 50Q characteristic impedance, where the load on the output point is set to 17Q.

FIG. 30 is a plot of the VSWR and the real and imaginary impedances at the ports of the QHC as the impedance phase is swept over a full VSWR circle.

FIG. 4 is a schematic diagram of the output stages of a balanced PA.

FIG. 5A is a block diagram of a full balanced PA.

FIG. 5B is a graph of the output power of each PA, and the balanced PA, of FIG. 5A, over a full VSWR circle.

FIG. 6 is a schematic diagram of two balanced PAs connected in parallel.

FIG. 7 is a schematic diagram of two balanced PAs connected in parallel, with the outputs connected via a Wilkinson power combiner.

FIG. 8A is a block diagram showing line averaging by the connecting antenna elements in a column of an array to the RFIC of FIG. 2 via differing-length traces.

FIG. 8B is a block diagram showing the PAs with differing-length traces connected to the outputs represented by different-length transmission lines, and corresponding phase offsets at the inputs.

FIG. 80 is a Smith chart plot showing that the impedances are evenly distributed about a VWSR circle.

FIG. 9A is block diagram showing line averaging, with inverse delays at the inputs and outputs of parallel PAs.

FIG. 9B shows and equivalent circuit of the output combiners of FIG. 9A.

FIG. 90 is a Smith chart plot showing that the impedances are evenly distributed about a VSWR circle.

FIG. 10 is a block diagram showing load modulation of a main amplifier by parallel auxiliary amplifiers, using QHCs rather than an impedance inverter to combine the outputs.

FIG. 11 A is a schematic diagram of two balanced PAs, each built with a QHC, and a delay line in the output of one balanced PA.

FIG. 11 B is a schematic diagram of the balanced PAs of FIG. 11 A, with delay lines on both outputs.

FIG. 110 is schematic diagram of the balanced PAs of FIG. 11 A, with one delay line, and the outputs combined via a Wilkinson power combiner.

FIG. 11 D is a schematic diagram of the balanced PAs of FIG. 11 B, with two delay lines, and the outputs combined via a Wilkinson power combiner.

FIG. 12 is a Smith chart plot showing the ports of the balanced PA of FIG. 110 lie on a VSWR circle.

FIG. 13A is a graph showing the VSWR at ports of the balanced PA of FIG. 110 as output load impedance and mismatch is swept through a full VSWR circle. FIG. 13B is a graph showing the real and imaginary parts of impedances at ports of the balanced PA of FIG. 110 as output impedance mismatch is swept through a full VSWR circle.

FIG. 14A is a schematic diagram of four balanced PAs connected in parallel, with delay lines on the outputs of three of them.

FIG. 14B is a schematic diagram of the four balanced PAs and delay lines of FIG. 14A, with the outputs connected via Wilkinson power combiners.

FIG. 15A is a schematic diagram of the four balanced PAs and delay lines of FIG. 14A, with the isolation terminals of the QHCs connected together and terminated via a resistor.

FIG. 15B is a schematic diagram of the two balanced PAs and delay lines of FIG. 11 A, with the isolation terminals of the QHCs connected together and terminated via a configurable or tunable impedance element.

FIG. 16 is a block and schematic diagram of a PA used for simulation.

FIG. 17A is a graph of the output power variation of the circuit of FIG. 6 over a full VSWR circle.

FIG. 17B is a graph of the output power variation of the circuit of FIG. 7 over a full VSWR circle.

FIG. 17C is a graph of the output power variation of the circuit of FIG. 11C over a full VSWR circle.

FIG. 18 is a flow diagram of a method of driving an antenna element or sub-array of antenna elements with an RF signal.

FIG. 19 is a hardware block diagram of a wireless device in a wireless communication network.

FIG. 20 is a hardware block diagram of a base station in a wireless communication network.

DETAILED DESCRIPTION

For simplicity and illustrative purposes, the present disclosure is described by referring mainly to an exemplary aspect thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be readily apparent to one of ordinary skill in the art that the present disclosure may be practiced without limitation to these specific details. In this description, well known methods and structures have not been described in detail so as not to unnecessarily obscure the present disclosure.

FIG. 1 depicts an example antenna array according to aspects disclosed herein. In this example, the array consists of 8x8 dual-polarized antenna elements. The antenna elements are pairwise interconnected to form 2x1 subarrays, and thus reduce number of active radio chains required to connect to the antenna and apply beamforming. The subarrays are numbered SAO to SA31 (moving left to right and top to bottom). In general, antenna elements of an array may be grouped into any number of subarrays, each comprising any number of individual antenna elements. Subarrays in an antenna array need not be the same - that is, some antennal elements may be grouped into one or more m x n subarrays, and other antennal elements may be grouped into one or more i x j subarrays, where m i and/or n j. As used herein, a subarray may include from one antenna element up to all of the antenna elements in an antenna array.

FIG. 2 depicts relevant portions of a Radio Frequency Integrated Circuit (RFIC) according to one aspect. This RFIC has 8 bidirectional IQ baseband ports, an internal port expansion by four, and thus 32 antenna connections. Each antenna branch, also referred to as an RF tile, has its own PLL, to enable beamforming by controlling the relative phase between antenna elements or subarrays. In transmit mode, the IQ baseband signal is split to four branches, upconverted to RF using an IQ-modulator, and amplified by a PA. An antenna switch connects either the transmitter or the receiver branch to the antenna element subarray. As depicted in FIG. 2, the tile connects to the antenna element subarrays in column 1 of the antenna system depicted in FIG. 1 (that is, subarrays SAO, SA8, SA16, and SA24). In receive mode, each antenna element subarray signal is amplified by the LNA, downconverted to baseband, and added to the other three branches sharing the IQ- interface. The receiver can also be reused as a transmit observation receiver (TOR), to sense the PA output signal, for use in closed-loop DPD operation (alternatively, the RFIC may include separate TOR circuitry).

The transceiver of FIG. 2 can be used together with the exemplary antenna array of FIG. 1. The four RF tiles sharing a baseband IQ-interface are here each connected to antenna element subarrays in one column of the antenna array. For example, the antenna connections depicted in FIG. 2 may connect to the antenna element subarrays of column 1 (SAO, SA8, SA16, and SA24). As discussed above, when coupled to antennas or subarrays as shown in FIG. 2, a time-varying impedance mismatch due to beamforming with coupled antenna array elements impacts PA output power, efficiency, and linearity.

One approach to reducing the sensitivity of PAs to impedance mismatches is a balanced PA circuit, implemented for example with Quadrature Hybrid Couplers (QHC). A QHC is special case of the general class of directional couplers for which the coupling is 3dB. FIG. 3A depicts one implementation of a QHC using transmission lines or microstrips. The transmission lines are of electrical length A/4, where A is the fundamental frequency. In other aspects, the QHC may be built from lumped reactive elements, such as inductive and capacitive devices. Such an implementation may be attractive for integration, as such QHCs may be fabricated in less area than a transmission line or microstrip implementation. For example, Robert C. Frye, et al. describe a CMOS implementation of a QHC suitable for integration on a high frequency RFIC, in the paper A 2GHz Quadrature Hybrid Implemented in CMOS Technology, published at the IEEE 2002 Custom Integrated Circuits Conference a p. 287, the disclosure of which is incorporated herein by reference in its entirety.

An ideal QHC is a symmetric, lossless, passive, four-port network, which imparts a 90° phase shift. Because it is symmetric, a QHC can split an input signal into two output signals (having 90° phase offsets) or combine two input signals (having 90° phase offsets) into one output signal.

FIG. 3B is a Smith chart plot of a 40GHz signal applied to a QHC with a 50Q characteristic impedance, where the load on the output point is set to 17Q. This impedance mismatch generates reflections, quantified as a VSWR=3. The VSWR is the same at the input ports (ports 1 and 2 in Fig. 3B), but the QHC ensures that the impedance of one input has a 90° phase shift to the other, i.e., a half-circle distance on the Smith Chart.

While FIG. 3B shows the PAs’ load impedances for one particular load value, FIG. 3C graphs the impedances as the load is swept over the full VSWR=3 circle. As shown in the upper graph, the VSWR at PA ports is roughly the same. The middle graph (real part) and lower graph (imaginary part) show that the PAs’ load impedances at the inputs are offset in phase by 90°.

As the Frye paper cited above discloses, one known application of a QHC is to implement a balanced PA, which exhibits reduced sensitivity to impedance mismatches by the load. This application is further described by Guiseppe Berretta, et al. in the paper A Balanced CDMA2000 SIGe HBT Load Insensitive Power Amplifier, published by the IEEE in 2006, the disclosure of which is incorporated herein by reference in its entirety. FIGs. 5A and 5B, copied from the Berretta paper, depict a schematic diagram of a balanced amplifier implemented using two QHCs, and a graph of output powers, respectively. As depicted in FIG. 5A, an RF signal is input to port 1 of a first QHC configured as a splitter, with a standard 50Q impedance connected to ground at port 4. The QHC outputs the signal on both output ports 2 and 3, with a 90° phase offset. These are amplified by PAs, which output the amplified quadrature RF signals, through impedance matching circuits, to a second QHC configured as a combiner, at input ports 2 and 3. The combined RF signal is output at port 1, with a standard 50Q impedance connected to ground at port 4.

FIG. 5B shows the output power for each PA as the load impedance varies over the full VSWR=4 circle (i.e., 0-360°). Because of the quadrature operation, the two PAs compensate each other, and the output power of the balanced PA circuit - the top curve in FIG. 5B - is nearly flat. A balanced PA architecture thus exhibits a high insensitivity to impedance mismatch, such as that caused by coupling between antenna array elements in beamforming operations.

FIG. 6 shows the output side of a balanced PA circuit, with characteristic impedances Zo and phases indicated. The inputs to the PAs are not explicitly depicted; those of skill in the art will understand they could comprise a QHC acting as a splitter, as depicted in FIG. 5A, or the quadrature RF signals input to the PAs could be otherwise generated, such as by mixing with a quadrature LO signal. Aspects of the present disclosure relate to combining the outputs of PAs, and hence the PA input circuit is not elaborated. To be clear, as used herein, the term “balanced power amplifier” or “balanced PA” refers to two PAs operating in quadrature (that is, with a 90° phase shift between them), the outputs of which are combined by a QHC. The balanced PA may have another QHC at the input, or the quadrature operation of the PAs may be generated otherwise.

Balanced PA circuits may be operated in parallel. In this case, the balanced PA outputs may be combined in a number of ways. For example, FIG. 6 shows the output ports of the respective QHCs being connected together. If the amplifiers are identical with characteristic impedance Zo, the load impedance has a nominal value of Zo/2.

The output power may be increased by using an additional power combiner, such as a Wilkinson combiner, as depicted in FIG. 7. This doubles the impedance, which will have an impact on the PA sizing. Furthermore, the additional combiner results in additional loss, and requires extra area for implementation. The number of combiners increases with the number of balanced PAs to combine.

Currently, state of the art solutions to dynamic antenna impedance mismatch target single PAs, or include approaches such as digital pre-distortion (DPD), Doherty PA architecture, line-averaging, or load modulation. DPD and Doherty structures are well known.

Line averaging refers to distributing the impedances of multiple PAs over, e.g., a 180° range using delay lines, which may be implemented by intentionally routing conductors, such as PCB traces, to have different physical (and hence, electrical) lengths. U.S. Patent Application Serial No. 63/271 ,910, assigned to the assignee of the present disclosure and incorporated herein by reference in its entirety, describes the technique. FIG. 8A shows unequal trace lengths of traces connecting paired antenna elements in a column of an antenna element array to the outputs of corresponding PAs on an overlying circuit. The traces have lengths L, L-A/8, L-A/4, and L-3A/8. FIG. 8B shows corresponding delay lines imposing offsetting phase shifts in the RF signals applied to the PAs of 0, 45°, 90°, and 135°. When the antenna elements are matched, all PAs see the same load impedance and operate in nominal conditions. In the case of impedance mismatch (such as from antenna element coupling during beamforming operations), each PA receives a difference phase due to non-identical delay lines between the PAs and antenna elements; hence a different load impedance for each PA. As FIG. 80 shows, the impedances are evenly distributed about the VWSR circle in a Smith chart plot.

A similar technique can be implemented per antenna, using delay lines between PAs and power combiners. This is descried by A. Berthier, et al. in Active VSWR Robustness Comparison for Different Phase Combining Topologies in the 2021 19^th IEEE International New Circuits and Systems Conference (NEWCAS), 2021, pp. 1-4, the disclosure of which is incorporated by reference herein in its entirety. FIG. 9A shows the circuit architecture, with splitters dividing an input signal, which is routed through different delay lines to an array of PAs. An inverse set of delay lines on the output realign the amplified signals, which are then combined and applied to an antenna. FIG. 9B is an equivalent circuit view of the output combiners. FIG. 9C shows the amplifier impedances distributed on a VSWR=1.33 circle. Over a VSWR=5 circle, the gain variation between the PAs is lowered by 1.8dB compared to a reference design.

A form of load modulation is described in U.S. Patent No. 6,922,102 to Myer, the disclosure of which is incorporated by reference herein in its entirety. This reference describes the use of auxiliary amplifiers (104, 106, 108) to modulate the load of a main amplifier (102), similarly to a Doherty structure, but without the need for A/4 transmission lines for impedance inversion, which limited integration and operation at lower frequencies. Rather, the reference uses QHCs to impose phase shifts on the auxiliary amplifier paths. Referring to Fig. 10 (reproducing Fig. 9 of the ‘102 patent), as described at col. 7, lines 12- 36, the dummy loads (135, 138, 144) of the QHCs (132, 134, 142) are lines tuned to present an electrical short to the coupler, and to avoid a power split when one of the auxiliary amplifiers is turned off. This arrangement provides load modulation for high PAPR signals, but does not provide a line-averaging effect.

FIG. 11A shows one aspect of the present disclosure, in which two balanced PAs are combined, with at least one delay line. A first balanced amplifier 10, comprising PA1 and PA2, is designed with characteristic impedance Zo. The amplifiers PA1 and PA2 are operated in quadrature - with a 90° relative phase shift. This balanced amplifier 10 is duplicated by a second balanced amplifier 12 comprising PA3 and PA4, so there are four PAs in total. A QHC 14 connected as a signal combiner at the outputs of PA1 and PA2 in the first balanced PA 10 combines the outputs with a -90° phase shift (/.e., a half-circle on the Smith Chart). A QHC 16 in the second balanced PA 12 similarly combines signals having a 90° phase shift between PA3 and PA4. In this aspect, the second balanced PA 12 additionally has a delay line 18 on its output, which introduces a further -45° phase shift to PA3 and PA4, relative to PA1 and PA2. As indicated at the outputs of the PAs, there is a -45° phase shift between all four PAs (0° for PA1, -45° for PA3, -90° for PA2, and -135° for PA4). Note that the delay line 18 could alternatively introduce a +45° phase shift, which would also introduce a delta phase shift of 45° between the two balanced PAs 10, 12. In this case, the phase shifts at the PAs would be -90° for PA2, -45° for PA4, 0° for PA1 , and 45° for PA3. Those of skill in the art will appreciate that it is the delta phase shift between PAs (due to both the delay line and the inherent 90° phase shift of a QHC) that achieves lineaveraging, and whether the phase shift introduced by the delay line 18 is positive or negative is merely an implementation detail. The output currents of the two balanced PAs 10, 12 are combined at the output of the delay line 18 (/.e., at the input to the antenna element of subarray), so the load impedance has a nominal value of Zo/2.

FIG. 11 B shows a different aspect of the present disclosure, in which two balanced PAs 10, 12 are combined, each having a delay line 20, 22 added to its respective output. One delay line 20 each introduces a -22.5° phase shift to the balanced PA 10, and a second delay line 22 introduces a 22.5° phase shift to the balanced PA 12. Accordingly, as indicated at the PA outputs, there is here also a 45° phase shift between all four PAs (22.5° for PA3, -22.5° for PA1, -67.5° for PA4, and -112.5° for PA2). As compared to the aspect depicted in FIG. 11A, in this aspect, the loss introduced by the delay lines 20, 22 is divided between both balanced PAs 10, 12. Those of skill in the art will readily realize that other values for the delay lines may be used, so long as the delta phase shift is +/-45°, for two balanced PAs.

FIG. 11C shows a yet another aspect of the present disclosure, in which two balanced PAs 10, 12 are combined as in the first aspect (FIG. 11A), but with the addition of a power combiner 24, such as a Wilkinson combiner, to combine the PA 10, 12 outputs prior to the load. The impedance phases are distributed as described with respect to the aspect depicted in FIG. 11 A, but in this aspect, the characteristic impedance Zo is preserved.

FIG. 11 D shows still another aspect of the present disclosure, in which two balanced PAs 10, 12 are combined as in the second aspect (FIG. 11B), but with the power combiner 24 (e.g., Wilkinson combiner). The impedance phases are distributed as described with respect to the aspect depicted in FIG. 11B, and the delay line 20, 22 losses are split between the combined PAs 10, 12; however, in this aspect, the characteristic impedance Zo is preserved.

The aspect depicted in FIG. 11C was selected for simulation. The PAs and load were set to 50Q nominal characteristic impedance. This model was simulated with the load impedance angle swept over the full VSWR=3 circle. PA1 to PA4 were modeled by Portl to Port4 respectively, and the load by Port5.

FIG. 12 is a Smith chart plot depicting the distribution of the PA loads corresponding to the simulation point where the load impedance is equal to 17Q. The PAs’ load impedances are evenly distributed on the VSWR circle. While FIG. 12 shows the PAs’ load impedances for one particular load value, FIG. 13 graphs the impedances as the load is swept over the full VSWR=3 circle. In particular, FIG. 13A graphs the VSWR, and FIG. 13B graphs the real and imaginary parts of the impedances, at the antenna (Port5) and PA plane (Portl to Port4), as the impedance sweeps over a complete VSWR circle. As these graphs show, the PAs’ load impedances are evenly distributed over the Smith chart as the load impedance varies over the full range, and the PAs’ load impedances at the inputs are offset in phase by 90°.

The aspects depicted in FIG. 11A-D are scalable. FIG. 14A depicts a combined balanced PA according to one aspect of the present invention. The combined balanced PA comprises four balanced PAs 30, 32, 34, 36, each comprising two PAs and a QHC 38, 40, 42, 44, respectively. Each of balanced PAs 32, 34, 36 has a delay line 46, 48, 50, at its respective output, imparting a further delta of -22.5° of impedance offset. This, combined with the inherent 90° phase shift due to quadrature operation of the PAs in a balanced PA, results in each PA being matched to a different impedance phase, offset by -22.5°, as follows:

PA1 0°

PA3 -22.5°

PA5 -45°

PA7 -67.5°

PA2 -90°

PA4 -112.5°

PA6 -135°

PA8 -157.5°

As discussed above, the delay lines 46, 48, 50 could alternatively impart a successive difference of +22.5° in phase, and still achieve line balancing, to mitigate load impedance variation and spread phase offsets of the PAs’ load impedances around a VSWR circle. The currents of the four balanced PAs 30-36 are combined at the output, so the load impedance has a nominal value of Zo/4.

In general, the amount of phase shift imposed between the balanced PAs may be expressed as 90/N, where N is the number of balanced PAs. For two balanced PAs 10, 12, as depicted in FIGs. 11A-D, N=2, and 90/2=45. The 45° phase shift may be implemented as zero delay on one balanced PA 10 and a +/-45° delay line on the other balanced PA 12 (FIGs. 11A, 11 C) , as two delay lines of -22.5° and +22.5°, or any other combination totaling a delta phase shift of +/-45°. For four balanced PAs 30, 32, 34, 36, as depicted in FIGs. 14A, 14B, N=4, and 90/4=22.5. The delta in phase of 22.5° may be implemented as zero delay on one balanced PA 30 and -22.5°, -45°, and -67.5 on the other balanced PAs 32, 34, 36, as shown in FIGs. 14A, 14B (or, as discussed above, 22.5°, 45°, and 67.5°). Alternatively, each balanced PA 30, 32, 34, 36 could be connected to delay lines imposing phase shifts of 45°, 22.5°, -22.5°, and -45°, respectively, or any other combination yielding a delta between balanced PAs of 22.5°.

FIG. 14B depicts an aspect of the present disclosure in which Wilkinson combiners 52, 54, 56 are used to combine the outputs of balanced PAs 30-36. This aspect employs the same delay lines 46, 48, 50 as the aspect of FIG. 14A, and the PAs in each balanced PA SO- 36 has a 90° phase shift, so the impedance phase offsets are the same as those listed above. In this aspect, however, the Wilkinson combiners 52-56 preserve the characteristic impedance of the system at Zo. As those of skill in the art can readily envision, the number of balanced PAs that can be combined in this manner is not limited to those depicted in the drawings.

In a QHC, the amplitude and phase of the signal reflected are determined by the load impedance at the output port and also the termination impedance at the isolated port. The termination impedance usually consists of a resistor connected to signal ground. However, a solid ground reference for connection of the termination load is not always available, especially at millimeter wave (mmW) frequencies. Aspects of the present disclosure address this issue.

It is possible to combine the isolated ports of multiple QHCs, even if the PAs are in quadrature (90°). Additionally, the termination load can take numerous forms, such as a resistor, an open circuit, a short circuit, a transmission line, an impedance tuner providing a complex impedance, etc.

FIG. 15A depicts an aspect of the present disclosure similar to that shown in FIG. 14A, but where the isolation terminals of QHCs 38, 40, 42, 44 are connected, and terminated to RF signal ground via a single resistor 58 having an impedance Zo/4 (to match the antenna load characteristic impedance of Zo/4). The isolation terminals of input QHCs of the balanced PAs, if present, are not included.

FIG. 15B depicts an aspect similar to that shown in FIG 11A, but where the isolation terminals of QHCs 14, 16 are connected, and terminated to RF signal ground via a single configurable or variable load 60. The load 60 may be implemented as a switch, providing an open or short circuit to RF signal ground, a transmission line, a tuner providing a complex impedance a+/b, or the like.

Simulations of the various aspects presented herein (e.g., shown in FIGs. 11 , 13, and 14) demonstrated that each individual PA in such an inventive circuit is distributed on a VSWR circle in the case of antenna impedance mismatch. Output power is now considered.

The aspect of the present disclosure depicted in FIG. 11 C - two balanced PAs 10, 12, each comprising a PA and a QHC 14, 16, with a -45° delay line on the output of balanced PA 12 and the balanced PA outputs connected via a Wilkinson combiner 24 - was simulated, and compared to the two prior art configurations depicted in FIGs. 6 and 7.

FIG. 16 depicts the simulation model 62 used for each individual PA, comprising baluns 64, 66 at the input and output to convert a single-ended signal to differential and back; input and output impedance matching networks (IMN 68, OMN 70), and a balanced, differential power amplifier 72. As shown, the PA 72 is implemented with a differential crosscoupled common source stage, followed by a common-gate stage.

To evaluate sensitivity to changes in the load impedance, the variation of output power over the VSWR = 3 circle was simulated and the results are presented in Table 1. For an accurate comparison, the input power was adjusted at each simulation to ensure that the PAs operate at 1-dB compression point. The results are also depicted graphically in Figure 16.

Table 1: Simulation Results for Output Power

These results are graphed in FIGs. 17A-C. In particular, FIG. 17A shows the results for the balanced PA of FIG. 6, with an average output power of 18.45 dBm, and a power variation of 1.5 dB, over the VSWR=3 circle.

FIG. 17B shows the results for the two connected balanced PAs of FIG. 7, with an average output power of 21 dBm, and a power variation of 1.4 dB, over the VSWR=3 circle.

FIG. 17C shows the results for the inventive circuit of FIG. 11C, utilizing both the 90° phase shift inherent to a balanced PA 10, 12, and the delay line 18 to implement line averaging across all PAs in the combined circuit. This circuit has an average output power of 21 dBm, and a power variation of only 0.1 dB, over the VSWR=3 circle.

FIG. 18 depicts the steps in a method 100 of driving an antenna element or sub-array of antenna elements with a Radio Frequency (RF) signal. The RF signal is amplified in each of at least two parallel balanced power amplifiers (block 102). Each balanced power amplifier comprises two power amplifiers connected in parallel and operating in quadrature, and an output quadrature hybrid coupler connecting the outputs of the two power amplifiers into a single RF signal. A phase shift is imparted to the output of at least one balanced amplifier (block 104). The outputs and phase-shifted outputs of the at least two balanced power amplifiers are combined (block 106). An antenna element or sub-array of antenna elements is driven with the combined RF signal (block 108).

The method 100 may be performed by any device or node driving antenna arrays that implement beamforming. FIG. 19 for example illustrates a hardware block diagram of a wireless device 80 as implemented in accordance with one or more embodiments. A wireless device 80 is any type of device capable of communicating with a network node and/or access point using radio signals. A wireless device 80 may therefore refer to a machine-to-machine (M2M) device, a machine-type communications (MTC) device, a Narrowband Internet of Things (NB loT) device, etc. The wireless device 80 may also be referred to as a User Equipment (UE), such as a cellular telephone or “smartphone,” however, the term UE should be understood to encompass any wireless device 80. A wireless device 80 may also be referred to as a radio device, a radio communication device, a wireless device, a wireless terminal, or simply a terminal - unless the context indicates otherwise, the use of any of these terms is intended to include device-to-device UEs or devices, machine-type devices, or devices capable of machine-to-machine communication, sensors equipped with a wireless device, wireless-enabled table computers, mobile terminals, smart phones, laptop-embedded equipped (LEE), laptop-mounted equipment (LME), USB dongles, wireless customer-premises equipment (CPE), etc. In the discussion herein, the terms machine-to-machine (M2M) device, machine-type communication (MTC) device, wireless sensor, and sensor may also be used. It should be understood that these devices, although referred to as UEs, but may be configured to transmit and/or receive data without direct human interaction.

In some embodiments, the wireless device 80 includes a user interface 82 (display, touchscreen, keyboard or keypad, microphone, speaker, and the like); in other embodiments, such as in many M2M, MTC, or NB loT scenarios, the wireless device 80 may include only a minimal, or no, user interface 82 (as indicated by the dashed lines of block 82 in FIG. 18). The wireless device 80 also includes processing circuitry 84; memory 86; and communication circuitry 88 to effect wireless communication across an air interface to one or more radio network nodes, such as a base station, and/or access points. The communication circuitry 88 is connected to an antenna element array 89, such as an AAS, which implements beamforming by phase control. As indicated by the dashed lines, the antenna array 89 may protrude externally from the wireless device 80, or the antenna array 89 may be internal. In some embodiments, a wireless device 80 may include a sophisticated user interface 82, and may additionally include features such as a camera, accelerometer, satellite navigation signal receiver circuitry, vibrating motor, and the like (not depicted in FIG. 18).

According to aspects of the present disclosure, the communication circuitry 88 includes parallel constructions of balanced PAs built using QHCs as output combiners, wherein the balanced PAs have an intrinsic 90° phase shift between the PAs, which additionally include one or more delay lines between at least one QHC output and an antenna element in the array 89, to implement line averaging. This makes the balanced PAs less susceptible to the deleterious effects of dynamically varying impedance mismatch at the antenna, such as that caused by beamforming.

Figure 20 depicts a hardware block diagram of a base station 90 operative in a wireless communication network. The base station 90 includes processing circuitry 92; memory 94; and communication circuitry 96 to effect wireless communication across an air interface to one or more wireless devices 80. The communication circuitry 96 is connected to an antenna element array 98, such as an AAS, which implements beamforming by phase control. As indicated by the broken connection to the antenna array 98, the antenna array 98 may be physically located separately from the base station 90, such as mounted on a tower, building, or the like. Although the memory 96 is depicted as being internal to the processing circuitry 94, those of skill in the art understand that the memory 96 may also be external. Those of skill in the art additionally understand that virtualization techniques allow some functions nominally executed by the processing circuitry 94 to actually be executed by other hardware, perhaps remotely located (e.g., in the so-called “cloud”). The base station 90 is known in LTE as an eNodeB or eNB, and in New Radio (NR) as gNB. In general, in other wireless communication networks, the base station 90 may be known as a Radio Base Station, Base Transceiver Station, Access Point, or the like.

According to aspects of the present disclosure, the communication circuitry 96 includes parallel constructions of balanced PAs built using QHCs as output combiners, wherein the balanced PAs have an intrinsic 90° phase shift between the PAs, which additionally include one or more delay lines between at least one QHC output and an antenna element in the array 98, to implement line averaging. This makes the balanced PAs less susceptible to the deleterious effects of dynamically varying impedance mismatch at the antenna, such as that caused by beamforming.

Note that apparatuses described herein may perform the method 100 herein and any other processing by implementing any functional means, modules, units, or circuitry. In one embodiment, for example, the apparatuses comprise respective circuits or circuitry configured to perform the steps shown in the method figures. The circuits or circuitry in this regard may comprise circuits dedicated to performing certain functional processing and/or one or more microprocessors in conjunction with memory. For instance, the circuitry may include one or more microprocessor or microcontrollers, as well as other digital hardware, which may include digital signal processors (DSPs), special-purpose digital logic, and the like. The processing circuitry may be configured to execute program code stored in memory, which may include one or several types of memory such as read-only memory (ROM), random-access memory, cache memory, flash memory devices, optical storage devices, etc. Program code stored in memory may include program instructions for executing one or more telecommunications and/or data communications protocols as well as instructions for carrying out one or more of the techniques described herein, in several embodiments. In embodiments that employ memory, the memory stores program code that, when executed by the one or more processors, carries out the techniques described herein.

Those skilled in the art will also appreciate that aspects herein further include corresponding computer programs.

A computer program comprises instructions which, when executed on at least one processor of an apparatus, cause the apparatus to carry out any of the respective processing described above. A computer program in this regard may comprise one or more code modules corresponding to the means or units described above.

Aspects further include a carrier containing such a computer program. This carrier may comprise one of an electronic signal, optical signal, radio signal, or computer readable storage medium.

In this regard, aspects herein also include a computer program product stored on a non-transitory computer readable (storage or recording) medium and comprising instructions that, when executed by a processor of an apparatus, cause the apparatus to perform as described above.

Aspects further include a computer program product comprising program code portions for performing the steps of any of the embodiments herein when the computer program product is executed by a computing device. This computer program product may be stored on a computer readable recording medium.

Aspects of the present disclosure have been presented in the context of line averaging employing both the 90° phase shift between PAs of a balanced PA, and additionally one or more delay elements at a balanced PA output. These delay elements are represented as phase shifts for the purpose of clarity of explanation. Those of skill in the art will readily understand that in practice, the delays may be introduced by varying the routing lengths between a parallel, balanced PA construction and antenna element/subarray. Alternatively, the phase shifts may be implemented by use of transmission lines, microstrip lines, lumped reactive components, or the like.

Aspects of the present disclosure present numerous advantages over the prior art. By taking advantage of the 90° phase shift inherent in a balanced PA for line-averaging using additional delay elements, the necessary number of passive elements after the parallel, balanced PAs is reduced, hence reducing the overall loss. The distribution of the PA loads provides an averaging effect such that the sum of each PA contributions appears at matched conditions. The approach is scalable, and allows for expansive parallelization of balanced PA circuits. Aspects of the present disclosure increase load resilience for individual amplifiers, i.e., per antenna or antenna element.

Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and/or is implied from the context in which it is used. All references to a/an/the element, apparatus, component, means, step, etc. are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and/or where it is implicit that a step must follow or precede another step. Any feature of any of the aspects disclosed herein may be applied to any other aspect, wherever appropriate. Likewise, any advantage of any of the aspects may apply to any other aspects, and vice versa. Other objectives, features and advantages of the enclosed aspects will be apparent from the description.

The term “unit” may have conventional meaning in the field of electronics, electrical devices and/or electronic devices and may include, for example, electrical and/or electronic circuitry, devices, modules, processors, memories, logic solid state and/or discrete devices, computer programs or instructions for carrying out respective tasks, procedures, computations, outputs, and/or displaying functions, and so on, as such as those that are described herein.

As used herein, the term “configured to” means set up, organized, adapted, or arranged to operate in a particular way; the term is synonymous with “designed to.”

Some of the aspects contemplated herein are described more fully with reference to the accompanying drawings. Other aspects, however, are contained within the scope of the subject matter disclosed herein. The disclosed subject matter should not be construed as limited to only the aspects set forth herein; rather, these aspects are provided by way of example to convey the scope of the subject matter to those skilled in the art.

The present disclosure may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the disclosure. The present aspects are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended aspects are intended to be embraced therein.

Claims

CLAIMS What is claimed is:

1. An amplifier circuit configured to drive an antenna element or sub-array of antenna elements with a Radio Frequency (RF) signal, comprising: at least two balanced power amplifiers (10, 12, 30, 32, 34, 36) connected in parallel, wherein each balanced power amplifier (10, 12, 30, 32, 34, 36) comprises two power amplifiers (PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8) connected in parallel and operating in quadrature; and an output quadrature hybrid coupler (14, 16, 38, 40, 42, 44) connecting the outputs of the two power amplifiers (PA1 , PA2, PA3, PA4, PA5, PA6, PA7, PA8) into a single RF signal; and a delay line (18, 20, 22, 46, 48, 50) interposed between the output of at least one balanced power amplifier (10, 12, 30, 32, 34, 36) and the antenna element or sub-array; whereby the delay line (18, 20, 22, 46, 48, 50) imparts a phase shift to the connected balanced power amplifier (10, 12, 30, 32, 34, 36).

2. The amplifier circuit of claim 1 wherein an amount of phase shift imparted between each of the at least two balanced power amplifiers (10, 12, 30, 32, 34, 36) is 90/N, where N is the number of balanced power amplifiers (10, 12, 30, 32, 34, 36) in the amplifier circuit.

3. The amplifier circuit of claim 1 wherein a first balanced power amplifier (10, 30) is connected directly to the antenna element or sub-array, and every other balanced power amplifier (12, 32, 34, 36) is connected to the antenna element or sub-array through a respective delay line (18, 46, 48, 50) imparting a different phase shift.

4. The amplifier circuit of claim 3, wherein the amplifier circuit comprises two balanced amplifiers (10, 12), and wherein the delay line (18) on the output of one balanced power amplifier (12) imparts a -45° phase shift.

5. The amplifier circuit of claim 3 wherein the amplifier circuit comprises four balanced amplifiers (30, 32, 34, 36), and wherein the delay lines (46, 48, 50) on the output of three balanced power amplifiers (32, 34, 36) impart phase shifts of -22.5°, -45°, and -67.5°.

6. The amplifier circuit of claim 1 wherein each balanced power amplifier (10, 12) is connected to the antenna element or sub-array through a delay line (20, 22) imparting a different phase shift.

7. The amplifier circuit of claim 6, wherein the amplifier circuit comprises two balanced amplifiers (10, 12), and wherein the delay line (20) on the output of one balanced power amplifier (10) imparts a -22.5° phase shift and the delay line (22) on the output of the other balanced power amplifier (12) imparts a 22.5° phase shift.

8. The amplifier circuit of any preceding claim, wherein the connection between a balanced power amplifier output or the outputs of delay lines, and the antenna element or sub-array, is via a power combining network (24, 52, 54, 56).

9. The amplifier circuit of claim 8, wherein the power combining network (24, 52, 54, 56) is a Wilkinson power combining network (24, 52, 54, 56).

10. The amplifier circuit of any preceding claim, wherein the delay line (18, 20, 22, 46, 48, 50) is implemented as one or more of a transmission line, microstrip line, and a circuit comprising lumped reactive components.

11. The amplifier circuit of any preceding claim, wherein each balanced power amplifier (10, 12, 30, 32, 34, 36) further comprises an input quadrature hybrid coupler configured to split an input RF signal between the two parallel power amplifiers.

12. The amplifier circuit of any preceding claim, wherein an isolation terminal of each output quadrature hybrid coupler is connected to RF signal ground via a load having a characteristic impedance (Zo) matched to the power amplifiers.

13. The amplifier circuit of any preceding claim, wherein isolation terminals of all output quadrature hybrid couplers are connected together, and terminated to RF signal ground through a circuit (58, 60) comprising a resistor, a switching circuit configurable as an open or short circuit, or an adjustable tuner providing a complex impedance.

14. A method (100) of driving an antenna element or sub-array of antenna elements with a Radio Frequency (RF) signal, comprising: amplifying (104) the RF signal in each of at least two parallel balanced power amplifiers (10, 12, 30, 32, 34, 36), wherein each balanced power amplifier (10, 12, 30, 32, 34, 36) comprises two power amplifiers (PA1 , PA2, PA3, PA4, PA5, PA6, PA7, PA8) connected in parallel and operating in quadrature, and an output quadrature hybrid coupler (14, 16, 38, 40, 42, 44) connecting the outputs of the two power amplifiers (PA1 , PA2, PA3, PA4, PA5, PA6, PA7, PA8) into a single RF signal; imparting (106) a phase shift to the output of at least one balanced amplifier (10, 12, 30, 32, 34, 36); and combining (108) the outputs and phase-shifted outputs of the at least two balanced power amplifiers (10, 12, 30, 32, 34, 36); and driving (110) an antenna element or sub-array of antenna elements with the combined RF signal.

15. The method of claim 14 wherein imparting (106) a phase shift to the output of at least one balanced amplifier (10, 12, 30, 32, 34, 36) comprises imparting phase shifts such that an amount of phase shift between balanced power amplifiers is 90/N, where N is the number of balanced power amplifiers (10, 12, 30, 32, 34, 36).

16. The method of claim 14 wherein imparting (106) a phase shift to the output of at least one balanced amplifier (10, 12, 30, 32, 34, 36) comprises imparting different phase shifts to the outputs of each of one fewer than the total number of balanced power amplifiers (12, 32, 24, 26), and imparting no phase shift to the output of the remaining balanced power amplifier (10, 30).

17. The method of claim 16, wherein the amplifier circuit comprises two balanced power amplifiers (10, 12), and wherein imparting different phase shifts to the outputs of each of one fewer than the total number of balanced power amplifiers comprises imparting a -45° phase shift to the output of one of the balanced power amplifiers (16).

18. The method of claim 16 wherein the amplifier circuit comprises four balanced amplifiers (30, 32, 34, 36), and wherein imparting different phase shifts to the outputs of each of one fewer than the total number of balanced power amplifiers comprises imparting phase shifts of -22.5°, -45°, and -67.5° to the outputs of each of three of the balanced power amplifiers (32, 34, 36).

19. The method of claim 16 wherein imparting (106) a phase shift to the output of at least one balanced amplifier (10, 12) comprises imparting a different phase shift to the output of each balanced amplifier (10, 12).

20. The method of claim 19, wherein the amplifier circuit comprises two balanced amplifiers (10, 12), and wherein imparting a different phase shift to the output of each balanced amplifier (10, 12) comprises imparting a -22.5° phase shift to the output of one balanced power amplifier (10) and a 22.5° phase shift to the output of the other balanced power amplifier (12).

21. The method of any of claims 14-20, wherein combining (108) the outputs and phase- shifted outputs of the at least two balanced power amplifiers comprises combining the outputs via a power combining network (24, 52, 54, 56).

22. The method of claim 21, wherein the power combining network (24, 52, 54, 56) is a Wilkinson power combining network (24, 52, 54, 56).

23. The method of any of claims 14-22, wherein imparting (106) a phase shift to the output of at least one balanced power amplifier (10, 12, 30, 32, 34, 36) comprises imparting a phase shift by interposing a delay line (18, 20, 22, 46, 48, 50) between the balanced power amplifier (10, 12, 30, 32, 34, 36) and the antenna element or sub-array, the delay line (18, 20, 22, 46, 48, 50) implemented as one or more of a transmission line, microstrip line, and a circuit comprising lumped reactive components.

24. The method of any of claims 14-23, wherein each balanced power amplifier (10, 12, 30, 32, 34, 36) further comprises an input quadrature hybrid coupler configured to split the input RF signal between the two parallel power amplifiers.

25. The method of any of claims 14-24, further comprising terminating an isolation terminal of each output quadrature hybrid coupler to RF signal ground via a load having a characteristic impedance (Zo) matched to the power amplifiers.

26. The method of any of claims 14-25, further comprising terminating an isolation terminal of each output quadrature hybrid coupler to RF signal ground through a circuit (58, 60) comprising a resistor, switching circuit configurable as an open or short circuit, or an adjustable tuner providing a complex impedance.

27. A wireless device (80) operative in a wireless communication network, comprising: an array of antenna elements (89); communication circuitry (88) connected to the antenna array (89) and configured to wirelessly communicate with one or more other network nodes; and processing circuitry (84) operatively connected to the communication circuitry (88) and configured to implement beamforming on the antenna array (89); wherein the communication circuitry (88) includes a plurality of amplifier circuits, each configured to drive an antenna element or sub-array of antenna elements, each amplifier circuit comprising at least two balanced power amplifiers (10, 12, 30, 32, 34, 36) connected in parallel, wherein each balanced power amplifier (10, 12, 30, 32, 34, 36) comprises two power amplifiers (PA1 , PA2, PA3, PA4, PA5, PA6, PA7, PA8) connected in parallel and operating in quadrature; and an output quadrature hybrid coupler (14, 16, 38, 40, 42, 44) connecting the outputs of the two power amplifiers (PA1 , PA2, PA3, PA4, PA5, PA6, PA7, PA8) into a single RF signal; and a delay line (18, 20, 22, 46, 48, 50) interposed between the output of at least one balanced power amplifier (10, 12, 30, 32, 34, 36) and the antenna element or sub-array; whereby the delay line (18, 20, 22, 46, 48, 50) imparts a phase shift to the connected balanced power amplifier (10, 12, 30, 32, 34, 36), with respect to at least one other balanced power amplifier (10, 12, 30, 32, 34, 36).

28. A base station (90) operative in a wireless communication network, comprising: an array of antenna elements (98); communication circuitry (96) connected to the antenna array (98) and configured to wirelessly communicate with one or more other network nodes; and processing circuitry (92) operatively connected to the communication circuitry (96) and configured to implement beamforming on the antenna array (98); wherein the communication circuitry (96) includes a plurality of amplifier circuits, each configured to drive an antenna element or sub-array of antenna elements, each amplifier circuit comprising at least two balanced power amplifiers (10, 12, 30, 32, 34, 36) connected in parallel, wherein each balanced power amplifier (10, 12, 30, 32, 34, 36) comprises two power amplifiers (PA1 , PA2, PA3, PA4, PA5, PA6, PA7, PA8) connected in parallel and operating in quadrature; and an output quadrature hybrid coupler (14, 16, 38, 40, 42, 44) connecting the outputs of the two power amplifiers (PA1 , PA2, PA3, PA4, PA5, PA6, PA7, PA8) into a single RF signal; and a delay line (18, 20, 22, 46, 48, 50) interposed between the output of at least one balanced power amplifier (10, 12, 30, 32, 34, 36) and the antenna element or sub-array; whereby the delay line (18, 20, 22, 46, 48, 50) imparts a phase shift to the connected balanced power amplifier (10, 12, 30, 32, 34, 36), with respect to at least one other balanced power amplifier (10, 12, 30, 32, 34, 36).