EP4649587A1

EP4649587A1 - Charge preamplifier and radiation detection apparatus with wide dynamic range

Info

Publication number: EP4649587A1
Application number: EP23825465.0A
Authority: EP
Inventors: Giuseppe BERTUCCIO; Filippo MELE
Original assignee: Politecnico di Milano
Current assignee: Politecnico di Milano
Priority date: 2023-01-12
Filing date: 2023-12-01
Publication date: 2025-11-19
Also published as: WO2024150048A1

Abstract

It is described a charge preamplifier (200) comprising: an input terminal (IN) for receiving a charge signal (I_in) generated by a radiation sensor (300) and an output terminal (OUT) for an electrical output signal (V_out); an amplifier (1; S1) configured to operate from the charge signal (I_in) to provide the electrical output signal (V_out); a feedback capacitor (Cf) connected to the input terminal (IN) and the output terminal (OUT); a discharge circuit (DSC) including a discharge component (SW; R_f) configured to cause a discharge of the feedback capacitor (C_f). The discharge circuit (DSC) further comprises an electronic device (ED) connected to the discharge component (SW; RE) and configured to: allow a charge and discharge of the feedback capacitor (C_f) and a variation of the electrical output signal (V_out) according to the charge signal (I_in); add, at least during the discharge of the feedback capacitor (C_f), a constant voltage value (V_adj) to a continuous electrical voltage present at the output terminal (OUT).

Description

Charge preamplifier and radiation detection apparatus with wide dynamic range

DESCRIPTION

TECHNICLA FIELD

The present invention relates to charge preamplifiers and radiation detection apparatuses employing a charge preamplifier.

STATE OF THE ART

In typical applications, the charge preamplifier is used in radiation measuring apparatus and thus receives as input the current signal generated by a radiation sensor. This sensor, when a radiation passes through it, produces a charge signal proportional to the energy of the absorbed radiation. Typically, the amount of charge generated by sensors, e.g. for X-rays, is extremely small (a few hundred to a few tens of thousands of electrons).

The charge preamplifier accepts this charge signal as input and converts it into a voltage signal. This voltage signal is used by further processing stages in order to generate, for example, an energy spectrum and/or a time distribution of the radiation.

As is well known, the charge preamplifier (Charge Sensitive Amplifier CSA) can be schematised as a low-noise operational amplifier having a feedback capacitance (Cf) placed between the input and output of the amplifier itself and acting as an integrator for the current signal placed at its input.

In a pulsed reset configuration, like the one shown in figure 1 (Prior Art), the voltage at the IN input node (at the output of the radiation sensor R-D) is kept constant during the acquisition, due to the negative feedback due to the feedback capacitance Cf; consequently, the voltage at the ends of the feedback capacitance will be entirely returned to the output node OU, modifying consequently the voltage Vout. During the "acquisition" phase, the charge accumulated on the feedback capacitance realises on the output node OU a "ramp", generated by the leakage current at the input node IN, superimposed on a "step", produced by the series of current pulses of finite amplitude, generated in correspondence of the radiation quanta absorbed by the detector R-D.

In pulsed reset preamplifiers, to prevent this voltage Vout from exceeding the dynamic output voltage range of the amplifier, the feedback capacitance is discharged - periodically or when a certain programmed threshold value is reached - via a reset switch (R-S), during a phase called 'reset'.

It should be noted that during the 'reset' phase, the preamplifier (which no longer operates as an integrator but as a buffer) is 'blind' to the detector input current, and this phase constitutes dead-time for the purposes of measurement acquisition in the detection apparatus.

The presence of this dead-time is particularly critical in high-flux/ high- luminosity applications, where the presence of a dead-time, even a short one, can cause the loss of numerous events, and thus significantly compromise the information collected by the detection system in terms of output count-rate (OCR).

In order to reduce the ratio of dead-time to acquisition time, the possible alternatives are: reduce the reset time, or increase the possible acquisition time between two reset intervals (avoiding preamplifier saturation). The speeding up of the reset time is inherently limited by the bandwidth and time constants of the detector/ CS A system, and is subject to stability issues. For example, these issues are discussed in the following papers:

- F. Mele, J. Quercia and G. Bertuccio, "Analytical Model of the Discharge Transient in Pulsed-Reset Charge-Sensitive Amplifiers," in IEEE Transactions on Nuclear Science, vol. 68, no. 7, pp. 1511-1518, July 2021.

- C. Fiorini, and Luca Bombelli. "Amplifier and radiation detector." U.S. Patent No. 9,411,054. 9 Aug. 2016.

- H, Funakoshi, S. Ito. "Amplifier circuit, integrating circuit, and light detection device" JP 2596612B2, 22 June 2009.

In the pulsed reset configuration such as the one shown in figure 1, an increase in the acquisition time can be achieved either by means of an increase in the feedback capacitance (which allows the integration of more charge, at the same voltage) or by means of an increase in the maximum acceptable voltage at the ends of the feedback capacitance before saturation of the preamplifier.

For example, the use of larger, selectable feedback capacities as needed is used in the following documents:

L. Shuhuan et al. "Preamplifier with wide dynamic reading range at front end of radiation detector" CN 112087208A, 15 Dicembre 2020.

A. Castoldi, C. Guazzoni, T. Parsani "A selectable-gain CMOS frontend for pulse shape analysis in Double Sided Silicon microstrip detectors", IEEE NSS/MIC 8-15 Novembre 2014.

However, increasing the feedback capacitance has a twofold negative effect on the ENG (Equivalent Noise Charge) of the detection apparatus: firstly, it causes an increase in the total input capacitance which, as is known, causes an increase in the ENC of the system; secondly, increasing the feedback capacitance causes a decrease in the charge/ voltage conversion gain of the CSA, with a consequent increase in the noise contribution of the stages following the CSA (buffer, shaper, ADC etc.) and reduces its robustness to external noise (pick-up noise). Consider also that the charge/ voltage conversion gain is generally a parameter fixed by the specific application of the CSA within the detection system, and cannot always be changed at will.

In order to reduce the reset dead-time, one can try to increase the acquisition time between two reset intervals by increasing the dynamic voltage range at the amplifier output. This makes it possible, with the same feedback capacitance, to increase the amount of total charge collected before a reset is necessary.

To do this, it is possible to use circuit solutions that have a rail-to-rail output dynamic range, which are widely found in the scientific literature. One such circuit solution is described in D. M. Monticelli, "A quad CMOS singlesupply op amp with rail-to-rail output swing," in IEEE Journal of Solid-State Circuits, vol. 21, no. 6, pp. 1026-1034, Dec. 1986.

Furthermore, the paper G. Bertuccio, S. Caccia, "Noise Minimization of MOSFET Input Charge Amplifiers based on AN and Ap 1/f Models", IEEE Transactions on Nuclear Science, Vol. 56, No. 3, 2009, pp. 1511 - 1520, clarifies how the peculiar application of low-noise CSAs requires that the input stage be biased to minimise ENC. Such a condition constrains the choice of DC voltage at the input node IN, which in turn, during the reset step, represents the voltage imposed at the output node by the buffered configuration and which ultimately dictates the voltage value from which the integration 'ramp/ scale' starts. A possible alternative for more freely modifying the DC voltage at the input node IN is described in the circuit solution presented in G. Bertuccio, S. Caccia "Progress in ultra-low-noise ASICs for radiation detectors", Nucl. Instrum. Methods Phys. Res. A, Vol. 579, No. 1, 2007, pp. 243-246, in which the DC voltage at the input node can be modified with the aid of a dedicated power supply terminal on the input transistor, at the cost of an increase in the complexity of the power supply scheme and thus of the detection apparatus and a decrease in the preamplifier's rejection of noise on the power supply lines.

SUMMARY OF THE INVENTION

The present invention addresses the problem of proposing a charge preamplifier which exhibits satisfactory performance in relation to its dynamic range and which is not particularly complex, while avoiding, at least in part, the disadvantages indicated above with reference to the known art.

According to one aspect, the present invention has as its object a charge preamplifier as described by claim 1 and preferred embodiments thereof as defined by claims 2-17.

Forma oggetto della presente invenzione anche un apparato di rivelazione come descritto dalla rivendicazione 18 e da una sua forma di realizzazione particolare definita dalle rivendicazioni 19 - 20.

It is an object of the present invention a detection apparatus as described by claim 18 and a particular embodiment thereof as defined by claims 19 - 20.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is hereinafter described in detail, by way of example and not limitation, with reference to the accompanying drawings, in which:

- figure 1 shows a circuit diagram of a radiation detector with a pulsed reset charge preamplifier, realised according to the known art;

- figure 2 shows schematically a first embodiment of a radiation detector apparatus including a charge preamplifier with pulsed reset, having a discharge circuit including a voltage generator;

- figure 3 shows a first example of the realisation of said voltage generator;

- figure 4 shows a second example of the realisation of said voltage generator;

- figure 5 schematically illustrates the trend of an integration ramp (Rl) of a charge preamplifier such as that of figure 2 and another trend of an integration ramp (R2) of a charge amplifier such as that of figure 1

- figure 6 schematically shows a second form of realisation of a radiation detector apparatus including a charge preamplifier with continuously reset, equipped with a corresponding discharge circuit including a voltage generator;

- figure 7 schematically shows the trend (R3) of the output voltage of a charge preamplifier such as that of figure 6 and another trend (R4) of the output voltage of a charge amplifier with continuous reset but without said voltage generator

- figure 8 shows schematically a third form of realisation of a radiation detector apparatus including a charge preamplifier with pulsed reset.

- figure 9 shows schematically a fourth form of realisation of a radiation detector apparatus including a charge preamplifier with pulsed reset.

DETAILED DESCRIPTION

While the invention is susceptible to various modifications and alternative constructions, particular embodiments and a generalised form are shown in the drawings and will be described in detail below. In this description, similar or identical elements or components will be indicated in the figures with the same identifying symbol.

Figure 2 shows, as an example, the circuit diagram of a detector apparatus 300 comprising a radiation sensor 100 (RAD-DET) and a charge preamplifier 200 of the pulsed reset type.

The radiation sensor 100, when passed through by an electromagnetic radiation or ionizing particle (in general, hereinafter referred to as radiation), produces a charge signal in the form of an electric current pulse Im, the associated electric charge of which is proportional to the energy of the absorbed radiation. By way of example, the radiation sensor 100 may be a Semiconductor (or Silicon) Drift Detector (SDD) type detector or a Pixel Detector type detector. These types of detectors require charge preamplifiers with very low input capacitance to achieve the highest performance in terms of signal-to-noise ratio, response speed and time stability. Typically, the amount of charge generated by detectors, e.g. for X-rays or gamma rays, is extremely small (a few hundred to a few tens of thousands of electrons).

The charge preamplifier 200 is such that it receives at its own input terminal IN the electric current Im provided by the radiation sensor 100 and converts it into an output voltage signal V_out, present at an output terminal OUT. More in detail, the charge preamplifier 200 operates as an integrator capable of integrating the electric current Im by providing at the output terminal OUT the output voltage signal Vout having an amplitude proportional to the electric charge placed at the input terminal IN. This output voltage signal Vout (or, more briefly, output voltage) can be used by further processing stages (not shown), in order to generate, for example, an energy spectrum and/ or a time distribution of radiation. The charge preamplifier 200 is of the pulsed reset type and comprises, according to a circuit schematic thereof, an amplifier 1 (e.g., an operational amplifier, as depicted in the figures), a feedback capacitor Cf and a discharge circuit DSC.

In accordance with the example shown, the amplifier 1 is a low-noise amplifier. Such an amplifier 1 comprises a first input terminal (for example, its inverting terminal "-") connected to a node N in turn connected to the input IN terminal of the charge preamplifier 200.

The amplifier 1 has a second input terminal, for example the non-inverting terminal "+", connected to a reference terminal REF (such as a ground terminal) to receive a reference voltage or bias V_ref. The output terminal of amplifier 1 is connected to the output terminal OUT of charge amplifier 200.

For example, amplifier 1 may be an operational amplifier or a single-ended input amplifier, a differential amplifier or an error amplifier.

According to a particular example, amplifier 1 may be of the three-stage type (not shown) and comprise: an input stage (such as a differential amplifier that performs the difference between the two inputs), an intermediate stage (such as an amplifier capable of providing high current or voltage gain) and an output stage (such as a follower amplifier) that further amplifies the signal from the intermediate stage. The input stage might not be a differential amplifier but an amplifier with a single-ended input, such as the one described in G. Bertuccio, S. Caccia 'Progress in ultra-low-noise ASICs for radiation detectors', Nucl. Instrum. Methods Phys. Res. A, Vol. 579, No. 1, 2007, pp. 243- 246, where the non-inverting terminal "+" schematizes the reference voltage for the inverting terminal

Note that since amplifier 1 is a low noise amplifier, it is imposed that the input stage (or first stage) be biased by choosing a bias voltage V_ref such that ENC is minimised. This condition constrains the value of the voltage Vm at the input terminal IN, because amplifier 1 acts in such a way as to minimise the difference V_ref-Vm.

The feedback capacitor Cf is connected between the output terminal OUT and node N, which is connected to the input terminal IN. More specifically, a first electrode of the feedback capacitor Cf is connected to the node N and a second electrode is connected to the output OUT.

The discharge circuit DSC is connected in parallel to the feedback capacitor Cf and includes a reset switch SW and an electronic device ED.

More particularly, the reset switch SW has a first terminal T1 connected to the first electrode of the feedback capacitor Cf and then to the node N. A second terminal T2 of the reset switch SW is instead connected to a terminal of the electronic device ED, while another terminal of that electronic device ED is connected to the output terminal OUT.

As will be explained in more detail below, with reference to the operation of the apparatus, the reset switch SW is such that it assumes an open configuration, in which the first terminal T1 and the second terminal T2 are disconnected from each other, and a closed configuration, in which these terminals T1 and T2 are connected together. In the open configuration, the charge preamplifier 200 operates by converting the impulsive current signal Im into the electrical output signal V_out and charging the feedback capacitor Cf. In the closed configuration, a discharge of the feedback capacitor Cf is caused. The electronic device ED can be realised in several possible ways: its possible variants will be described on the following pages. The electronic device ED is configured to allow (i.e., not hinder) the correct variation of the electrical output signal V_out as a function of the current signal Im, and to allow charging and discharging of the feedback capacitor Cf according to the normal functionality of the charge preamplifier 200.

Furthermore, the electronic device ED is such as to add (i.e. add or subtract), at least during the discharge of the feedback capacitor Cf, a constant voltage value V_adj to the electrical voltage present at the output terminal OUT. In particular, the electronic device ED imposes, at least during the discharge of the feedback capacitor Cf, a constant voltage difference between the second terminal T2 and the output terminal OUT.

According to the form of implementation of figure 2, the electronic device ED is realised by a voltage generator 2. The voltage generator 2 is such that, in the closed configuration, it enables the discharge of the feedback capacitor Cf by bringing the voltage of the output terminal OUT to a predetermined value. Note that the voltage V_adj is added to the output voltage V_out regardless of whether the latter is constant or not; in particular, note that V_out is not constant during discharge.

In contrast, in the open configuration, the voltage generator 2 is floating. The voltage generator 2 is such that it generates a constant electrical voltage Vadj and, preferably, is of the adjustable type.

The charge preamplifier 200 can be realised, according to some examples, in a plate of semiconductor material according to CMOS (Complementary - Metal-Oxide Semiconductor) technology, or according to BiCMOS (Bipolar Complementary Metal-Oxide Semiconductor) technology or according to BCD (Bipolar-CMOS - DMOS) technology. DMOS technology includes Vertical Diffused MOS (VDMOS) and Lateral Diffused MOS (LDMOS) techniques. As an example, the feedback capacitance Cf has values between IfF and lOOpF.

With regard to the operation of the detector apparatus 300 of figure 2, consider initially, the open configuration of the reset switch SW which corresponds to an acquisition configuration of the apparatus 300.

In the open configuration, the discharge circuit DSC plays no role and, due to the presence of the feedback capacitor Cf, the charge preamplifier 200 acts as an integrator of a total electric current Idet(t) generated by the radiation sensor 100 (consisting of the sum of the signal electric current Im and a dark current II).

This integration results, over time, in an accumulation of a charge Qf (t) in the feedback capacitor Cf, consequently developing a voltage Vf(t) at the capacitor's ends.

The voltage Vf(t) at the ends of the feedback capacitor Cf can be expressed by the relation (1) below:

Note that due to the negative feedback of amplifier 1, the electrical voltage Vm at the input terminal IN (i.e., at node N) is kept constant during acquisition, i.e., equal to the bias voltage V_ref. This implies that the voltage Vf(t) which develops at the ends of the feedback capacitor Cf is returned to the output terminal OUT, modifying the voltage V_out.

During this acquisition, the charge accumulating in the feedback capacitor Cf produces at the output terminal OUT a voltage V_out which varies according to a ramp pattern, generated by a constant current (such as a leakage current) at the input terminal IN, superimposed on a "staircase" produced by the series of current pulses of finite amplitude, generated in correspondence with the radiation absorbed by the radiation sensor 100. Such a voltage V_out (i.e., a ramp superimposed on a staircase) is increasing or decreasing depending on whether the charge preamplifier 200 is designed to integrate negative charges (electrons or ions) or positive charges (lacunes or ions). In order to prevent this voltage Vout from exceeding the dynamic output voltage range of amplifier 1 during acquisition, a reset step is provided in which the reset switch SW is brought into the closed configuration so that the feedback capacitor Cf is short- circuited by the DSC discharge circuit and thus discharged.

The reset step can be triggered periodically (according to a preset frequency) or when a certain Vth threshold value (of the V_out voltage at the output terminal OUT) is reached. The reset procedure is handled, advantageously, by a control module (not shown) that can be connected to the discharge circuit DSC.

Figure 5 shows, by way of example, an initial trend R1 of the output voltage Vout: the increasing ramps shown in the figure refer to acquisition steps (A-PH) which end when the threshold voltage Vth is reached, with subsequent activation of the discharge steps, with the reset switch (R-PH) being closed). The positive slope of the ramp refers, as an example, to a charge preamplifier 200 built to integrate negative charges.

In the reset step, the reset switch SW is closed and the voltage generator 2 is in operation and is such that it does not hinder the discharge of the feedback capacitor Cf, as it has as low a dynamic impedance as possible, so that it behaves as much as possible like an ideal voltage generator. For example, according to the first trend Rl, the acquisition phase A-PH has a duration T_ai while the reset phase R-PH (i.e. discharge) has a duration Tai. Note that during the reset step, the charge preamplifier 200 is 'blind' to the input current Im supplied by the radiation sensor 100. In fact, instead of generating a voltage signal at the output terminal OUT, the charge current Im will simply be discharged from the output terminal OUT (low impedance) via the discharge circuit DSC. Thus, the reset phase R-PH constitutes, for the purpose of measurement acquisition in the detection apparatus 300 a deadtime Ta.

As already indicated, the presence of this dead-time is particularly critical in high-flux/ high-luminosity applications, where the presence of a dead-time, even a short one, can cause the loss of numerous events, and thus significantly compromise the information collected by the detection system in terms of output count-rate (OCR).

During reset, the voltage V_out varies, while the voltage Vm is assumed to remain constant (ideally), as is the voltage V_adj. At the end of the reset transient, the voltage generator 2 operates so that the voltage V_out assumes a set value indicated by the following equation (2):

Vout = Vin + Vadj (2)

Where Vm is the value of the DC voltage at the input terminal IN.

Relation (2) shows that, by suitably dimensioning the value of the voltage V_adj produced by voltage generator 2, it is possible to freely modify the starting point of the integration "ramp", without modifying the value Vm (i.e. of the polarisation V_ref) at the input terminal IN.

For example, with reference to figure 5 (trend Rl), relation (2) gives the voltage corresponding to the starting point of the ramp Rl and equal to V_out = Vin - Vadj. At the end of the reset phase, the reset switch SW is opened and a subsequent acquisition phase begins in which the output voltage V_out varies from the value set by the relation (2) (V out = Vm - V_adj).

It should be noted that, during the acquisition step, the voltage generator 2 is floating (the reset switch SW is open), and therefore the voltage generator 2 does not increase the total input capacitance to the charge preamplifier 200, and its noise is short-circuited by the low impedance of the output terminal OUT of the charge preamplifier 200, ensuring that the performance of the charge preamplifier itself, in terms of noise ENC, is maintained.

Figure 5 also shows, by way of example, a second ramp R2 of the voltage at the output terminal V_out, which would occur in the absence of the voltage generator 2, i.e. for a traditional type of detector apparatus (such as the one in figure 1): the starting value of the second ramp R2 is equal to Vm, a condition caused by the electrical short-circuit of the SW switch between the input terminal IN and the output terminal OUT. In this example case, the acquisition phase A-PH has a duration T_a2 (shorter than the T_ai which occurs for the trend Rl) while the reset phase R-PH (i.e. discharge) still has a duration Td.

A comparison of ramp Rl and ramp R2 shows that the ratio T_ai/Td is greater than the ratio T_a2/Td. This implies that the use of voltage generator 2 causes an increase in the output dynamics of amplifier 1, reducing the relative dead-time defined above and the frequency of reset operations to be performed. It is also apparent from the foregoing that the voltage generator 2 allows the DC voltage at the output terminal OUT at the end of the reset step to be set independently (i.e., not exclusively dependent) from the DC voltage at the input terminal IN (which depends on the bias voltage of the first stage of the amplifier 1), without using additional power supplies, and thus reducing the complexity of the detection system with respect to techniques used according to the known art.

Voltage generator 2 can be realised in various ways. In particular, the voltage generator 2 can be realised by means of a voltage level shifter, also called a voltage level translator.

Figure 3 shows a first form of realisation of the voltage generator 2 (of the voltage level shifter type) comprising a diode DI, a first current generator 4 and an optional second current generator 5 (both configured to generate a constant current lb).

According to an example, the diode DI has its anode connected to a terminal of the first current generator 4, which has a second terminal connected to a power supply terminal. The cathode of diode DI is connected to a terminal of the second current generator 5, which has another terminal connected to GND.

As regards the connection of the voltage generator 2 of figure 3 to the charge preamplifier 200, the anode of the diode DI is connected to the first terminal T2 (in turn connected to the reset switch SW) and the cathode of the diode DI is connected to the OUT output terminal. The constant voltage drop on the diode DI (forward biased) defines the voltage V_adj of the voltage generator 2. The voltage generator in the form of figure 3 has the advantage of being simple to manufacture. What has been described above refers to the case of collection of negative charges at the input of the charge preamplifier 200, as in fig. 5. If the charge preamplifier 200 collected positive charges, the ramp would be decreasing and the anode of the diode DI would be connected to the OUT output.

Figure 4 shows another embodiment of the voltage generator 2 which allows obtaining a relatively wide range of possible values of the generated voltage V_adj. With reference to CMOS technology, the voltage generator 2 comprises: a current generator 6 configured to generate a constant current IB1, a further current generator 7 configured to generate a constant current IB2, a first MOSFET transistor Ml and a second MOSFET transistor M2 (in the example both P channel).

The source terminals of the first and second transistors Ml and M2 are connected to each other and to the current generator 6. The drain terminal of the first transistor Ml is connected to the ground terminal GND, while the relative gate terminal is connected to the first terminal T1 (connected to the SW reset switch) of the charge amplifier 200.

The gate and drain terminals of the second transistor M2 are connected to each other and to the further current generator 7. Furthermore, the gate and drain terminals of the second transistor M2 are connected to the output terminal OUT of the charge preamplifier 200.

The first transistor Ml is biased by the difference between the currents IB1 and IB2 (IB1-IB2) while the second transistor M2 is biased by the current IB2. This type of current polarization allows to obtain a relatively extended range of possible voltages between the T1 and OUT terminals.

A voltage source analogous to that of figure 4 is described in the paper J. Ramirez-Angulo, "Low voltage current mirrors for built-in current sensors," Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94, 1994, pp . 529-532 vol.5.

Figure 6 refers to another embodiment of the charging preamplifier 200 in which this is of the continuous reset type. In this case, the discharge circuit DCS (not provided with a reset switch) includes a discharge resistor Rf which, in the example, is connected between the node N and the voltage generator 2 (similar to the one described above: constant voltage V_adj). The discharge resistor Rf ensures continuous discharge of the feedback capacitor Cf, avoiding saturation of amplifier 1.

In the case of continuous reset, the charging and discharging steps are not clearly distinct, as in the case of pulsed reset. With reference to figure 7 (trend R3), the output voltage V_outis discharged constantly via the discharge resistor Rf, so that, following a signal pulse PL, integrated by the feedback capacitor Cf, which causes a step in output, the output voltage V_out is brought back to the "reset" value through the discharge DS. In the case of continuous reset, the output "ramp" caused by leakage does not occur, as happens in the case of pulsed reset. Furthermore, instead of a "staircase", a series of PL pulses with exponential discharge is obtained, as shown schematically in figure 7.

Even in the case of continuous reset, the voltage generator 2 does not hinder either the charging or the discharging of the feedback capacitor Cf. The voltage generator 2 is such as to bring the direct component to a predetermined value (i.e., when the discharge is completed) of the electrical voltage Vout at the output terminal OUT. In other words, the voltage generator 2 causes a "translation" of the voltage level to which the output terminal OUT returns at the end of the discharge DS. This "translation" allows you to choose the DC voltage level at the output terminal OUT differently from the reference voltage Vref at the input terminal IN.

Figure 7 shows another trend R4 of the voltage at the output terminal in the case of continuous reset, but in the absence of the voltage generator 2. As regards the trend R3, the pulses PL have an amplitude between Vm-V_adj and Vout_m_ax while for the trend R4, the pulses have a lower amplitude, between Vm and Vout_ max/ •

Since the voltage generator 2 allows you to have a value of the direct voltage at the input terminal IN that is different from that of the direct component at the output terminal OUT, it has the advantage of allowing you to obtain an increase in the output dynamics of the amplifier 1.

Note that in the case of continuous reset, to which figure 6 refers, the voltage generator 2 cannot be considered to all intents and purposes a "silent" component. For example, it could be observed that the leakage current of the radiation sensor 100 flows through the voltage generator 2 (which depending on the application can vary from tens of fA to a few nA). This leakage current can cause increased noise. However, continuous reset applications are typically less stringent from a noise performance perspective, having inherently higher noise than the pulsed reset architecture.

Note that, in the embodiment described with reference to figure 2 (pulsed reset) and figure 6 (continuous reset), the voltage generator 2 has been illustrated as interposed between the reset switch SW or the discharge resistor Rf and the output terminal OUT. In an alternative solution, it is possible to place the voltage generator 2 between the node N (connected to the input terminal IN) and the reset switch SW or the discharge resistor Rf.

However, the connection of the voltage generator 2 as illustrated in figures 2 and 6 is preferred for the reason that this leaves the capacitive load at the input node N unchanged, which is a direct function of the total noise of the system. Considering any spurious noise contributions coming from voltage generator 2 (power supply noise, ground/ substrate noise, etc.), if this is connected to the output terminal OUT, these contributions are short-circuited (and therefore cancelled) by the low output impedance of the preamplifier 200. Instead, by connecting the voltage generator 2 to the input terminal IN these contributions would be integrated (just like a signal), contributing to the worsening of the noise performance of the system.

Figure 8 refers to a further embodiment of the charge preamplifier 200, of the pulsed reset type (as per figure 2), in which an electronic device ED alternative to that of figure 2 is used in the discharge branch DSC and using a further amplifier 8, as well as the constant voltage generator 2.

According to this embodiment, the further amplifier 8 can be: a differential amplifier (feedback or non-feedback), an operational amplifier (OPA), a transimpedance operational amplifier (OTA), an error amplifier. The following description refers, by way of example, to the use of a generic differential amplifier (hereinafter referred to as "further differential amplifier 8") and can be easily extended by the technician in the field to the case of use of OPA, OTA amplifiers or an amplifier of error.

The further differential amplifier 8 has a relative output terminal connected to the second terminal T2, in turn connected to the reset switch SW, and includes a relative first input (for example, of the inverting type ^zz-^zz) connected to the generator constant voltage 2 and a related second input (such as a non-inverting input "+") connected to a further node Nl. The further node N1 is connected to the output terminal OUT of the amplifier 1. The constant voltage generator 2 generates the voltage V_adj and can be created, by way of example, as previously described.

Regarding the operation of the charge preamplifier 200 of figure 8, note that during a charging step (reset switch SW open), the further differential amplifier 8 is a circuit with a gain Adiff.

As the output voltage Vout increases (according to the staircase ramp trend as previously described), the further differential amplifier 8 produces at its output terminal (coinciding with the second terminal T2) an increasing voltage Vout.diff which can be expressed as

V out_diff Adiff X (V out ~ V adj) (3) as long as the differential amplifier 8 operates in the non-saturation region.

The gain Adiff can be chosen to be of an appropriate value, possibly even lower than unity, and the amplifier band is also appropriately chosen. Note that the electrical voltage at the second terminal T2 (i.e., at the output of the further differential amplifier 8) does not affect the functionality of the amplifier 1 during charging because the reset switch SW is open and therefore the output of the further differential amplifier 8 is floating.

The voltage at the output terminal of the further differential amplifier 8 could saturate (upwards in the example considered), when the differential voltage (Vout - V_adj) between the relevant input terminals exceeded the input dynamics of the amplifier itself.

Even when the output of the further differential amplifier 8 is saturated, the differential amplifier 1 does not change its functionality and this is due to the open reset switch SW. Therefore, during this charging step, the further differential amplifier 8 does not influence the normal operation of the charging preamplifier 200, and goes into a condition in which the voltage of its noninverting input (connected to the output terminal OUT) is higher than that of the inverting input (connected to the voltage source Vadj), and its output is (ideally) saturated upwards (to a voltage VDD not shown).

During the discharge phase (reset switch SW closed), the further differential amplifier 8 acts to force the input terminal IN towards its output value Vout_diff. This involves an injection of current into the input terminal IN, coming out of the further differential amplifier 8, and passing through the switch SW.

This current, integrated by the feedback capacitance Cf, causes a sudden lowering of the output voltage Vout. Note that, in this condition, the further differential amplifier 8 is operating in a closed loop (and with "globally" negative feedback, due to the sign inversion brought about by the charge preamplifier 200), and acts in such a way as to minimize the difference or error signal at its inputs: Vout-vadj.

As a result, the output voltage V_out continues to drop until it reaches the value V_adj, canceling the error signal V_out-V_adj. It follows that, at the end of the transient described, the output voltage V_out will be equal to the voltage V_adj, independently of the voltage V_ref, just as desired. The same effect would be obtained in the case of using an OTA or OPA or other circuit configurations that generically provide a current or voltage output dependent on the voltage difference at the inputs.

Figure 9 refers to a further embodiment of the charge preamplifier 200, of the pulsed reset type, in which the discharge branch DSC is partly integrated within the amplifier 1, for example of the differential type.

Amplifier 1 which, as already explained previously, can include multiple amplification stages such as, for example, three stages in cascade: a first stage SI, a second stage S2 and a third stage S3.

According to this embodiment, the voltage Vadj, which in previous implementations was obtained from appropriate circuits (such as those shown in fig. 3 and fig. 4) connected to the output terminal OUT, is now taken from an internal node P of the amplifier which, by way of example, in figure 9 coincides with the output of the first stage SI. In particular, the choice of node P satisfies two requirements: a) The signal at the node P is in phase with the signal at the output terminal

OUT so that, when the switch SW is closed, a negative feedback occurs during the reset step. b) The static value of the voltage V_p of the node P is equal to the desired value to which the node N is to be brought at the end of the reset phase.

The relationship between the voltage V_p at node P and the voltage V_out at the output terminal OUT can be written in the form

V_0Ut = Vp + VA (3)

Where VA is a constant static voltage value determined by the internal circuit configuration of the preamplifier 200 and possibly adaptable in the design phase. In the example in Figure 9, the value VA is determined by the circuit implementation of the stages S2 and S3.

During the reset step, the switch SW short-circuits the node N with the node P, imposing, at the end of the transient, the condition Vp=Vm and therefore the relation (3) becomes

V_0Ut = Vin + VA (4)

Which is similar to equation (2) obtained for the previous configurations where VA=V_adj. VA therefore corresponds to the V_adj of the particular configurations shown in fig. 2 and fig. 8.

Note that the configuration of figure 9 can be seen as a generalization of all the previous ones, which are particular cases in which the node P is made to coincide with the node T2 of figures 2, 6 and 8. Similarly to the others, the configuration of figure 9 can be extended to the case of continuous reset with the resistor Rf in place of the switch SW.

It should be underlined that the configuration of figure 9 includes the previous ones and extends the typology by also including all those cases in which the node P is not a low impedance node, a condition that can be advantageous in order to avoid unwanted transients at the input node N of the preamplifier.

A further advantage of the general configuration of figure 9 consists in the fact that, when the switch SW is closed during the reset, the feedback loop that is generated contains fewer processing stages, generally guaranteeing an easier achievement of the stability criteria of the feedback loop.

However, the previous configurations, using the generator V_adj connected to the output OUT, have the advantage of a simpler and more immediate circuit implementation.

The solutions described above have significant advantages.

Using the voltage generator 2, or the general configuration of figure 9, to separate the voltage at the output terminal OUT from the bias voltage Vm, increases the dynamic range of the charging preamplifier, both in the pulsed reset and in the reset form continuous.

In the case of pulsed reset, the solution described also allows a reduction in the reset frequency, with a respective reduction in the reset dead-time percentage, improving the output count-rate (OCR) performance, particularly in the presence of high incoming flows.

Furthermore, compared to other prior art techniques, the described solution allows not to use additional power terminals for the polarization of the charge amplifier (in particular, of its first stage), with consequent simplification and reduction of the BOM (Bill of Materials) of the detection apparatus including the charge preamplifier.

Inoltre, la riduzione della frequenza del reset comporta anche una riduzione dell'interferenza elettromagnetica (EMI) prodotta dal preamplificatore di carica all' inferno dell'apparato di rivelazione.

The charge preamplifier described also allows a possible reduction in the value of the feedback capacitance with the same input charge dynamics, with the advantage of reducing noise and increasing the conversion gain of the system.

In the general configuration of figure 9 the reset can be controlled by a high impedance node, rather than a low one, by reducing voltage transistors on the virtual ground input node of the preamplifier.

List of symbols of the components of the drawings

- detector apparatus 300

- radiation sensor 100

- charge preamplifier 200

- charging signal Im

- input terminal IN

- output voltage signal V out

- output terminal OUT

- amplifier 1

- feedback capacitor Cf

- reset switch SW

- node N

- electronic device ED

- reference terminal REF

- reference voltage VREF

- discharge circuit DSC

- reset switch SW - voltage generator 2

- constant voltage V_adj

- first terminal T1

- second terminal T2

- threshold value Vth

- diode DI

- first power generator 4

- second power generator 5

- ground terminal GND

- power generator 6

- further current generator 7 ,

- first transistor Ml

- second transistor M2

- discharge resistor Rf

- additional amplifier 8

- first stage SI

- second stage S2

- third stage S3

Claims

1. Charge preamplifier (200) comprising:

- an input terminal (IN) for receiving a charge signal (Im) generated by a radiation sensor (300) and an output terminal (OUT) for an electrical output signal (V out)/

- an amplifier (1; SI) configured to operate from the charge signal (Im) to provide the electrical output signal (V_out);

- a feedback capacitor (Cf) connected to the input terminal (IN) and the output terminal (OUT);

- a discharge circuit (DSC) including a discharge component (SW; Rf) configured to cause a discharge of the feedback capacitor (Cf); wherein the discharge circuit (DSC) further comprises an electronic device (ED) connected to the discharge component (SW; RF) and configured to: allow a charge and discharge of the feedback capacitor (Cf) and a variation of the electrical output signal (V out) according to the charge signal (Im); add, at least during the discharge of the feedback capacitor (Cf), a constant voltage value (V _adj) to a continuous electrical voltage present at the output terminal (OUT).

2. Charge preamplifier (200), according to claim 1 in which:

- the output terminal (OUT) of the preamplifier is an output (P) of the amplifier (1); the feedback capacitor (Cf) is arranged in parallel to the amplifier (1).

3. Charge preamplifier (200) according to claim 2, wherein: the electronic device (ED) comprises a generator (2) of constant voltage (Vadj).

4. Charge preamplifier (200) according to claim 1 wherein:

- said charge preamplifier (200) is of the pulsed reset type;

- said discharge component includes a reset switch (SW) such as to assume a closed configuration in which it causes a discharge of the feedback capacitor (Cf) and an open configuration in which the amplifier (1) converts the charge signal (Im) into the electrical output signal (V_out) and charges the feedback capacitor (Cf).

5. Charge preamplifier (200) according to claim 4, wherein: in the open configuration, the voltage generator (2) is floating; in the closed configuration, the voltage generator (2) brings to a first constant value (Vm - V_adj) the electrical voltage at the output terminal (OUT) and allows the discharge of the feedback capacitor (Cf).

6. Charge preamplifier (200) according to claim 4, wherein said electronic device (ED) further comprises a further amplifier (8) having:

- a first input connected to the voltage generator (2);

- a second input connected to the output terminal (OUT);

- an output (T2) connected to the reset switch (SW); and wherein: the further amplifier (8) is such that, in the closed configuration of the reset switch (SW), it causes the output terminal (OUT) to assume a second constant voltage value dependent on said constant voltage produced by the voltage generator (2).

7. Charge preamplifier (200) according to claim 3, wherein:

- said amplifier (1) is of the continuous reset type;

- said discharge component includes a discharge resistor (Rf).

8. Charge preamplifier (200) according to claim 3, wherein: - said charge preamplifier (200) is configured to operate as an integrator by providing an electrical output signal (V out) in the form of an output voltage representative of an integral over time of the charge signal (Im).

9. Charge preamplifier (200) according to claim 1, wherein said electronic device (ED) allows to obtain, at the end of a discharge of said feedback capacitor (Cf) , a third constant voltage value at the output terminal (OUT) dependent on a constant voltage value (V_adj) and from a continuous input voltage value (Vm) at said input terminal (IN).

10. Charge preamplifier (200) according to claim 3, wherein said voltage generator (2) is of the voltage level shifter type.

11. Charge preamplifier (200) according to claim 3, wherein said voltage generator (2) includes: a diode (DI) connected between the discharge component (SW; Rf) and said output terminal (OUT).

12. Charge preamplifier (200) according to claim 3, wherein said voltage generator (2) comprises: a first transistor (Ml) having a first control terminal connected to said discharge component (SW, Rf); a second transistor (M2) having a second control terminal connected to a first terminal of said second transistor (M2) and to said output terminal (OUT) a first constant current generator (6) connected to first common terminals of said transistors; a second constant current generator (7) connected to said second control terminal and said first terminal of said second transistor (M2).

13. Charge preamplifier (200) according to claim 1, wherein: the amplifier (1) has a relative input (-) connected to a node (N) connected to said input terminal (IN).

14. Charge preamplifier (200) according to claim 13, wherein: the feedback capacitor (Cf) has a first electrode connected to said node (N) and a second electrode connected to said output terminal (OUT).

15. Charge preamplifier (200) according to claim 14, wherein: the discharge component (SW, Rf) has a relative first terminal (Tl) connected to the first electrode and the node N and a relative second terminal (T2) connected to said voltage generator (2).

16. Charge preamplifier (200) according to claim 1, integrated in a semiconductor material plate according to one of the following technologies: CMOS technology (Complementary - Metal-Oxide Semiconductor), BiCMOS technology (Bipolar Complementary Metal-Oxide Semiconductor) BCD technology (Bipolar-CMOS - DMOS).

17. Charge preamplifier (200) according to claim 1, wherein said amplifier (1) comprises: an amplification stage (SI) having an output (P); at least one further amplification stage (S2; S3) having an input connected to said output (P) and having said output terminal (OUT); wherein: the electronic device (ED) comprises said at least one further amplification stage (S2; S3)

18. Charge detector apparatus (300) comprising: a radiation sensor (100) configured so that, when a radiation passes through it, it produces a charge signal (Im) proportional to the energy of the absorbed radiation a charge preamplifier (200) connected to the radiation sensor (100) and made according to at least one of the preceding claims.

19. Detector apparatus (300) according to claim 17, wherein the radiation sensor (100) is a sensor according to one of the following types: semiconductor drift detector, SDD; pixel detector.

20. Detector apparatus (300) according to claim 17, further comprising a reset switch controller (SW).