EP4643395A1 - Hybrid detectors featuring low temperature surface passivation - Google Patents

Abstract

Systems, apparatuses, and methods include a detector including a plurality of detection elements including a portion of a silicon substrate comprising: a front side of the portion of the silicon substrate including a PIN or NIP diode that comprises a p-type region and an n-type region; a back side of the portion of the silicon substrate, opposite of the front side, comprising a passivation layer deposited at low temperature that when a bias is applied the PIN or NIP diode is configured to detect an electron that enters the backside of the portion of the silicon substrate.

Description

HYBRID DETECTORS FEATURING LOW TEMPERATURE SURFACE PASSIVATION

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of EP application 22216866.8 which was filed on December 28, 2022 and which is incorporated herein in its entirety by reference.

FIELD

[0002] The description herein relates to the field of inspection systems, and more particularly to systems for detecting particles with a detector during inspection.

BACKGROUND

[0003] In manufacturing processes of integrated circuits (ICs), unfinished or finished circuit components are inspected to ensure that they are manufactured according to design and are free of defects. An inspection system utilizing an optical microscope typically has resolution down to a few hundred nanometers; and the resolution is limited by the wavelength of light. As the physical sizes of IC components continue to reduce down to sub- 100 or even sub- 10 nanometers, inspection systems capable of higher resolution than those utilizing optical microscopes are needed.

[0004] A charged particle (e.g., electron) beam microscope, such as a scanning electron microscope (SEM) or a transmission electron microscope (TEM), capable of resolution down to less than a nanometer, serves as a practicable tool for inspecting IC components having a feature size that is sub- 100 nanometers. With a SEM, electrons of a single primary electron beam, or electrons of a plurality of primary electron beams, can be focused at locations of interest of a wafer under inspection. The primary electrons interact with the wafer and may be backscattered or may cause the wafer to emit secondary electrons. The intensity of the electron beams comprising the backscattered electrons and the secondary electrons may vary based on the properties of the internal and external structures of the wafer, and thereby may indicate whether the wafer has defects.

SUMMARY

[0005] Embodiments of the present disclosure provide apparatuses, systems, and methods for forming a passivation layer on an electron detector comprising: depositing or synthesizing a passivation material on a surface of a wafer as part of forming the electron detector on the wafer, wherein the wafer is heated to less than 400 °C during deposition of the passivation material and during all remaining steps of manufacture of the electron detector. In some embodiments, systems and methods may include a silicon substrate thinned to a thickness of 50 nm to 1 mm; a front side of the silicon substrate including a lateral or vertical PIN diode formed by a p-type region and an n-type region; a region between the p- type region and the n-type region configured to form an intrinsic region when a reverse bias is applied between the p-type region and the n-type region; a back side of the silicon substrate, opposite of the front side, comprising a substantially transparent surface to electrons; and a passivation layer on either the diode surface or the backside surface opposite to the frontside of the silicon substrate, wherein the lateral or vertical PIN diode is configured to detect an electron that enters the back side of the silicon substrate and passes through the silicon substrate to the depletion region.

[0006] In some embodiments, a detector may include a plurality of detection elements, a detection element of the plurality of detection elements comprising: a portion of a silicon substrate comprising: a front side of the portion of the silicon substrate including a PIN or NIP diode that comprises a p-type region and an n-type region; a back side of the portion of the silicon substrate, opposite of the front side, comprising a substantially transparent surface; and a passivation layer on the back side of the portion of the silicon substrate; wherein: a region between the p-type region and the n-type region is configured to form a depletion or intrinsic region when a reverse bias is applied between the p-type region and the n-type region, and the PIN diode is configured to detect an electron that enters the back side of the portion of the silicon substrate and passes through the portion of the silicon substrate to the depletion or intrinsic region.

[0007] In some embodiments, a detector may include a plurality of detection elements, a detection element of the plurality of detection elements comprising: a portion of a silicon substrate comprising: a front side of the portion of the substrate including a PIN diode that comprises a p-type region and an n- type region; a back side of the portion of the substrate, opposite of the front side, comprising a substantially transparent surface; and a layer on the back side of the portion of the substrate; wherein: frontside interconnect patterning is deposited at low temperature.

[0008] In some embodiments, a detector may include a plurality of detection elements, a detection element of the plurality of detection elements comprising: a portion of a substrate comprising: a front side of the portion of the substrate including a p-type region and an n-type region, the p-type region and the n-type region forming a PIN diode; and a back side of the portion of the substrate, opposite of the front side, comprising a substantially transparent surface; wherein: a backside passivation is deposited at low temperature, after the frontside interconnect patterning processing.

[0009] In some embodiments, a method of forming a detection element of a detector may include forming a PIN diode on a front side of a silicon substrate by inserting, in the silicon substrate, p-type dopants to form a p-type region and n-type dopants to form an n-type region, wherein a region between the p-type region and the n-type region is configured to form a depletion or intrinsic region when a reverse bias is applied between the p-type region and the n-type region; thinning a back side of the silicon substrate, opposite of the front side, wherein the back side comprises a substantially transparent surface that with novel materials such as an ultra-thin aluminum-doped silicon formed by metal-induced crystallization or layer exchange (from Al(Si X%), where X can vary from 0), or chemical vapor deposition (CVD) (e.g., among other low-pressure CVD and plasma enhanced CVD, etc.) Boron acts a defect neutralizing passivation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Fig. 1 is a schematic diagram illustrating an exemplary electron beam inspection (EBI) system, consistent with embodiments of the present disclosure.

[0011] Fig. 2A is a schematic diagram illustrating an exemplary multi-beam system that is part of the exemplary charged particle beam inspection system of Fig. 1, consistent with embodiments of the present disclosure.

[0012] Fig. 2B is a schematic diagram illustrating an exemplary single-beam system that is part of the exemplary charged particle beam inspection system of Fig. 1, consistent with embodiments of the present disclosure.

[0013] Fig. 3A is a schematic representation of an exemplary structure of a detector, consistent with embodiments of the present disclosure.

[0014] Fig. 3B is a schematic illustration of a cross-sectional structure of a substrate of a detector, consistent with embodiments of the present disclosure.

[0015] Fig. 3C is a schematic illustration of a cross-sectional structure of a substrate of a detector, consistent with embodiments of the present disclosure.

[0016] Fig. 3D is a schematic illustration of an individual detection element, consistent with embodiments of the present disclosure.

[0017] Figs. 4A-4C are schematic illustrations of a process to develop a conventional electron detector.

[0018] Fig. 5A-5B are schematic illustrations of an example process to develop an electron detection element using low temperature passivation, consistent with embodiments of the present disclosure.

[0019] Figs. 6A-6C are schematic illustrations of another example process to develop an electron detection element using low temperature passivation, consistent with embodiments of the present disclosure.

DETAILED DESCRIPTION

[0020] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the disclosure. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the subject matter recited in the appended claims. For example, although some embodiments are described in the context of utilizing electron beams, the disclosure is not so limited. Other types of charged particle beams may be similarly applied. Furthermore, other imaging systems may be used, such as optical imaging, photodetection, x-ray detection, extreme ultraviolet inspection, deep ultraviolet inspection, or the like, in which they generate corresponding types of images. [0021] Electronic devices are constructed of circuits formed on a piece of silicon called a substrate. Many circuits may be formed together on the same piece of silicon and are called integrated circuits or ICs. The size of these circuits has decreased dramatically so that many more of them can fit on the substrate. For example, an IC chip in a smart phone can be as small as a thumbnail and yet may include over 2 billion transistors, the size of each transistor being less than l/1000th the size of a human hair.

[0022] Making these extremely small ICs is a complex, time-consuming, and expensive process, often involving hundreds of individual steps. Errors in even one step have the potential to result in defects in the finished IC rendering it useless. Thus, one goal of the manufacturing process is to avoid such defects to maximize the number of functional ICs made in the process, that is, to improve the overall yield of the process.

[0023] One component of improving yield is monitoring the chip making process to ensure that it is producing a sufficient number of functional integrated circuits. One way to monitor the process is to inspect the chip circuit structures at various stages of their formation. Inspection may be carried out using a scanning electron microscope (SEM). A SEM can be used to image these extremely small structures, in effect, taking a “picture” of the structures of the wafer. The image can be used to determine if the structure was formed properly and also if it was formed at the proper location. If the structure is defective, then the process can be adjusted so the defect is less likely to recur. Defects may be generated during various stages of semiconductor processing. For the reason stated above, it is important to find defects accurately and efficiently as early as possible.

[0024] The working principle of a SEM is similar to a camera. A camera takes a picture by receiving and recording brightness and colors of light reflected or emitted from people or objects. A SEM takes a “picture” by receiving and recording energies or quantities of electrons reflected or emitted from the structures. Before taking such a “picture,” an electron beam may be provided onto the structures, and when the electrons are reflected or emitted (“exiting”) from the structures, a detector of the SEM may receive and record the energies or quantities of those electrons to generate an image. To take such a “picture,” some SEMs use a single electron beam (referred to as a “single-beam SEM”), while some SEMs use multiple electron beams (referred to as a “multi-beam SEM”) to take multiple “pictures” of the wafer. By using multiple electron beams, the SEM may provide more electron beams onto the structures for obtaining these multiple “pictures,” resulting in more electrons exiting from the structures. Accordingly, the detector may receive more exiting electrons simultaneously, and generate images of the structures of the wafer with a higher efficiency and a faster speed.

[0025] During the process development of these conventional detectors, a passivation layer is incorporated to reduce leakage current caused by surface defects and to reduce signal charge capture by surface traps. The process for depositing current passivation materials (e.g., Boron) includes heating the wafer to temperatures over 700 °C.

[0026] The use of this higher temperature, however, makes the development process more complex. For example, materials that have low melting points, such as CMOS IC metal interconnects or MOSFET gates, need to be formed after the high temperature step so they are not damaged by temperatures above their melting point. This requirement makes some hybrid detectors (e.g., detectors that comprises multiple elements) or detectors that require backside processing to undergo at least a three-step process: 1) front side processing at high-temperature, comprising ion implantation and implant activation; 2) backside passivation at high temperature; and 3) front side low temperature processing, comprising metal deposition and gate formation.

[0027] Some disclosed embodiments provide systems and methods that address some or all of these disadvantages by providing a new high-quality passivation layer that can be applied (e.g., deposited or synthesized) at lower temperatures so that it can be safely incorporated without damaging IC metal interconnects or MOSFET gates already formed on the wafer. By being able to apply the passivation layer at lower temperatures, the development process can be simplified, improving yield, and reducing costs.

[0028] The low temperature passivation layer is distinguished from a standard CMOS surface passivation in that it acts as a defect neutralizing passivation. A defect neutralizing passivation reduces the defects formed on the surface by achieving low density of surface states available for defect agglomeration. This defect neutralizing passivation also acts as a diffusion barrier to prevent reoxidation of the surface, which can lead to additional surface defects. The passivation material is configured to be substantially transparent to electrons of an electron beam, wherein the substantially transparent can be greater than 90%, greater than 95%, or greater than 99%. SiN, A1O_X, and SiON are some of the commonly used materials for CMOS surface passivation. The aforementioned commonly used materials often are deposited at temperatures higher than 200 °C, and often lack in defect neutralization requiring complex doping and deposition strategies for true mitigation of defectivity. At least some embodiments of the present disclosure use, for example, ultra-thin aluminum-doped silicon (e.g., less than or equal to lOnm in some embodiments and less than or equal to 50nm in other embodiments) formed by metal-induced crystallization or layer exchange (from Al(Si X%), where X can vary from 0) or high purity boron materials as passivating layers for defect reduction as these types of materials allow not only low temperature deposition, but has superior defect reduction compared to the standard materials referenced previously.

[0029] Relative dimensions of components in drawings may be exaggerated for clarity. Within the following description of drawings, the same or like reference numbers refer to the same or like components or entities, and only the differences with respect to the individual embodiments are described.

[0030] As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a component may include A or B, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or A and B. As a second example, if it is stated that a component may include A, B, or C, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0031] Without limiting the scope of the present disclosure, some embodiments may be described in the context of providing detectors and detection methods in systems utilizing electron beams. However, the disclosure is not so limited. Other types of charged particle beams may be similarly applied. Furthermore, systems and methods for detection may be used in other imaging systems, such as optical imaging, photon detection, x-ray detection, ion detection, etc.

[0032] Fig. 1 illustrates an exemplary electron beam inspection (EBI) system 100 consistent with embodiments of the present disclosure. EBI system 100 may be used for imaging. As shown in Fig. 1, EBI system 100 includes a main chamber 101, a load/lock chamber 102, an electron beam tool 104, and an equipment front end module (EFEM) 106. Electron beam tool 104 is located within main chamber 101. EFEM 106 includes a first loading port 106a and a second loading port 106b. EFEM 106 may include additional loading port(s). First loading port 106a and second loading port 106b receive wafer front opening unified pods (FOUPs) that contain wafers (e.g., semiconductor wafers or wafers made of other material(s)) or samples to be inspected (wafers and samples may be used interchangeably). A “lot” is a plurality of wafers that may be loaded for processing as a batch.

[0033] One or more robotic arms (not shown) in EFEM 106 may transport the wafers to load/lock chamber 102. Load/lock chamber 102 is connected to a load/lock vacuum pump system (not shown) which removes gas molecules in load/lock chamber 102 to reach a first pressure below the atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) may transport the wafer from load/lock chamber 102 to main chamber 101. Main chamber 101 is connected to a main chamber vacuum pump system (not shown) which removes gas molecules in main chamber 101 to reach a second pressure below the first pressure. After reaching the second pressure, the wafer is subject to inspection by electron beam tool 104. Electron beam tool 104 may be a single-beam system or a multibeam system.

[0034] A controller 109 is electronically connected to electron beam tool 104. Controller 109 may be a computer configured to execute various controls of EBI system 100. While controller 109 is shown in Fig- 1 as being outside of the structure that includes main chamber 101, load/lock chamber 102, and EFEM 106, it is appreciated that controller 109 may be a part of the structure.

[0035] In some embodiments, controller 109 may include one or more processors (not shown). A processor may be a generic or specific electronic device capable of manipulating or processing information. For example, the processor may include any combination of any number of a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), an optical processor, a programmable logic controllers, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field- Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), and any type circuit capable of data processing. The processor may also be a virtual processor that includes one or more processors distributed across multiple machines or devices coupled via a network.

[0036] In some embodiments, controller 109 may further include one or more memories (not shown). A memory may be a generic or specific electronic device capable of storing codes and data accessible by the processor (e.g., via a bus). For example, the memory may include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or any type of storage device. The codes may include an operating system (OS) and one or more application programs (or “apps”) for specific tasks. The memory may also be a virtual memory that includes one or more memories distributed across multiple machines or devices coupled via a network.

[0037] Embodiments of this disclosure may provide a single charged-particle beam imaging system (“single -beam system”). Compared with a single-beam system, a multiple charged-particle beam imaging system (“multi-beam system”) may be designed to optimize throughput for different scan modes. Embodiments of this disclosure provide a multi-beam system with the capability of optimizing throughput for different scan modes by using beam arrays with different geometries and adapting to different throughputs and resolution requirements.

[0038] Reference is now made to Fig. 2A, which is a schematic diagram illustrating an exemplary electron beam tool 104 including a multi-beam inspection tool that is part of the EBI system 100 of Fig. 1, consistent with embodiments of the present disclosure. In some embodiments, electron beam tool 104 may be operated as a single-beam inspection tool that is part of EBI system 100 of Fig. 1. Multibeam electron beam tool 104 (also referred to herein as apparatus 104) comprises an electron source 201, a Coulomb aperture plate (or “gun aperture plate”) 271, a condenser lens 210, a source conversion unit 220, a primary projection system 230, a motorized stage 209, and a sample holder 207 supported by motorized stage 209 to hold a sample 208 (e.g., a wafer or a photomask) to be inspected. Multi-beam electron beam tool 104 may further comprise a secondary projection system 250 and an electron detection device 240. Primary projection system 230 may comprise an objective lens 231. Electron detection device 240 may comprise a plurality of detection elements 241, 242, and 243. A beam separator 233 and a deflection scanning unit 232 may be positioned inside primary projection system 230.

[0039] Electron source 201, Coulomb aperture plate 271, condenser lens 210, source conversion unit 220, beam separator 233, deflection scanning unit 232, and primary projection system 230 may be aligned with a primary optical axis 204 of apparatus 104. Secondary projection system 250 and electron detection device 240 may be aligned with a secondary optical axis 251 of apparatus 104.

[0040] Electron source 201 may comprise a cathode (not shown) and an extractor or anode (not shown), in which, during operation, electron source 201 is configured to emit primary electrons from the cathode and the primary electrons are extracted or accelerated by the extractor and/or the anode to form a primary electron beam 202 that form a primary beam crossover (virtual or real) 203. Primary electron beam 202 may be visualized as being emitted from primary beam crossover 203.

[0041] Source conversion unit 220 may comprise an image-forming element array (not shown), an aberration compensator array (not shown), a beam-limit aperture array (not shown), and a pre-bending micro-deflector array (not shown). In some embodiments, the pre -bending micro-deflector array deflects a plurality of primary beamlets 211, 212, 213 of primary electron beam 202 to normally enter the beam-limit aperture array, the image-forming element array, and an aberration compensator array. In some embodiments, apparatus 104 may be operated as a single-beam system such that a single primary beamlet is generated. In some embodiments, condenser lens 210 is designed to focus primary electron beam 202 to become a parallel beam and be normally incident onto source conversion unit 220. The image-forming element array may comprise a plurality of micro-deflectors or micro-lenses to influence the plurality of primary beamlets 211, 212, 213 of primary electron beam 202 and to form a plurality of parallel images (virtual or real) of primary beam crossover 203, one for each of the primary beamlets 211, 212, and 213. In some embodiments, the aberration compensator array may comprise a field curvature compensator array (not shown) and an astigmatism compensator array (not shown). The field curvature compensator array may comprise a plurality of micro-lenses to compensate field curvature aberrations of the primary beamlets 211, 212, and 213. The astigmatism compensator array may comprise a plurality of micro- stigmators to compensate astigmatism aberrations of the primary beamlets 211, 212, and 213. The beam-limit aperture array may be configured to limit diameters of individual primary beamlets 211, 212, and 213. Fig. 2A shows three primary beamlets 211, 212, and 213 as an example, and it is appreciated that source conversion unit 220 may be configured to form any number of primary beamlets. Controller 109 may be connected to various parts of EBI system 100 of Fig- 1, such as source conversion unit 220, electron detection device 240, primary projection system 230, or motorized stage 209. In some embodiments, as explained in further details below, controller 109 may perform various image and signal processing functions. Controller 109 may also generate various control signals to govern operations of the charged particle beam inspection system.

[0042] Condenser lens 210 is configured to focus primary electron beam 202. Condenser lens 210 may further be configured to adjust electric currents of primary beamlets 211, 212, and 213 downstream of source conversion unit 220 by varying the focusing power of condenser lens 210. Alternatively, the electric currents may be changed by altering the radial sizes of beam- limit apertures within the beamlimit aperture array corresponding to the individual primary beamlets. The electric currents may be changed by both altering the radial sizes of beam- limit apertures and the focusing power of condenser lens 210. Condenser lens 210 may be an adjustable condenser lens that may be configured so that the position of its first principle plane is movable. The adjustable condenser lens may be configured to be magnetic, which may result in off-axis beamlets 212 and 213 illuminating source conversion unit 220 with rotation angles. The rotation angles change with the focusing power or the position of the first principal plane of the adjustable condenser lens. Condenser lens 210 may be an anti-rotation condenser lens that may be configured to keep the rotation angles unchanged while the focusing power of condenser lens 210 is changed. In some embodiments, condenser lens 210 may be an adjustable antirotation condenser lens, in which the rotation angles do not change when its focusing power and the position of its first principal plane are varied.

[0043] Objective lens 231 may be configured to focus beamlets 211, 212, and 213 onto a sample 208 for inspection and may form, in the current embodiments, three probe spots 221, 222, and 223 on the surface of sample 208. Coulomb aperture plate 271, in operation, is configured to block off peripheral electrons of primary electron beam 202 to reduce Coulomb effect. The Coulomb effect may enlarge the size of each of probe spots 221, 222, and 223 of primary beamlets 211, 212, 213, and therefore deteriorate inspection resolution.

[0044] Beam separator 233 may, for example, be a Wien filter comprising an electrostatic deflector generating an electrostatic dipole field and a magnetic dipole field (not shown in Fig. 2A). In operation, beam separator 233 may be configured to exert an electrostatic force by electrostatic dipole field on individual electrons of primary beamlets 211, 212, and 213. The electrostatic force is equal in magnitude but opposite in direction to the magnetic force exerted by magnetic dipole field of beam separator 233 on the individual electrons. Primary beamlets 211, 212, and 213 may therefore pass at least substantially straight through beam separator 233 with at least substantially zero deflection angles.

[0045] Deflection scanning unit 232, in operation, is configured to deflect primary beamlets 211, 212, and 213 to scan probe spots 221, 222, and 223 across individual scanning areas in a section of the surface of sample 208. In response to incidence of primary beamlets 211, 212, and 213 or probe spots 221, 222, and 223 on sample 208, electrons emerge from sample 208 and generate three secondary electron beams 261, 262, and 263. Each of secondary electron beams 261, 262, and 263 typically comprise secondary electrons (having electron energy < 50eV) and backscattered electrons (having electron energy between 50eV and the landing energy of primary beamlets 211, 212, and 213). Beam separator 233 is configured to deflect secondary electron beams 261, 262, and 263 towards secondary projection system 250. Secondary projection system 250 subsequently focuses secondary electron beams 261, 262, and 263 onto detection elements 241, 242, and 243 of electron detection device 240. Detection elements 241, 242, and 243 are arranged to detect corresponding secondary electron beams 261, 262, and 263 and generate corresponding signals which are sent to controller 109 or a signal processing system (not shown), e.g., to construct images of the corresponding scanned areas of sample 208.

[0046] In some embodiments, detection elements 241, 242, and 243 detect corresponding secondary electron beams 261, 262, and 263, respectively, and generate corresponding intensity signal outputs (not shown) to an image processing system (e.g., controller 109). In some embodiments, each detection element 241, 242, and 243 may comprise one or more pixels. The intensity signal output of a detection element may be a sum of signals generated by all the pixels within the detection element. [0047] In some embodiments, controller 109 may comprise image processing system that includes an image acquirer (not shown), a storage (not shown). The image acquirer may comprise one or more processors. For example, the image acquirer may comprise a computer, server, mainframe host, terminals, personal computer, any kind of mobile computing devices, and the like, or a combination thereof. The image acquirer may be communicatively coupled to electron detection device 240 of apparatus 104 through a medium such as an electrical conductor, optical fiber cable, portable storage media, IR, Bluetooth, internet, wireless network, wireless radio, among others, or a combination thereof. In some embodiments, the image acquirer may receive a signal from electron detection device 240 and may construct an image. The image acquirer may thus acquire images of sample 208. The image acquirer may also perform various post-processing functions, such as generating contours, superimposing indicators on an acquired image, and the like. The image acquirer may be configured to perform adjustments of brightness and contrast, etc. of acquired images. In some embodiments, the storage may be a storage medium such as a hard disk, flash drive, cloud storage, random access memory (RAM), other types of computer readable memory, and the like. The storage may be coupled with the image acquirer and may be used for saving scanned raw image data as original images, and postprocessed images.

[0048] In some embodiments, the image acquirer may acquire one or more images of a sample based on an imaging signal received from electron detection device 240. An imaging signal may correspond to a scanning operation for conducting charged particle imaging. An acquired image may be a single image comprising a plurality of imaging areas. The single image may be stored in the storage. The single image may be an original image that may be divided into a plurality of regions. Each of the regions may comprise one imaging area containing a feature of sample 208. The acquired images may comprise multiple images of a single imaging area of sample 208 sampled multiple times over a time sequence. The multiple images may be stored in the storage. In some embodiments, controller 109 may be configured to perform image processing steps with the multiple images of the same location of sample 208.

[0049] In some embodiments, controller 109 may include measurement circuitries (e.g., analog-to- digital converters) to obtain a distribution of the detected secondary electrons. The electron distribution data collected during a detection time window, in combination with corresponding scan path data of each of primary beamlets 211, 212, and 213 incident on the wafer surface, can be used to reconstruct images of the wafer structures under inspection. The reconstructed images can be used to reveal various features of the internal or external structures of sample 208, and thereby can be used to reveal any defects that may exist in the wafer.

[0050] In some embodiments, controller 109 may control motorized stage 209 to move sample 208 during inspection of sample 208. In some embodiments, controller 109 may enable motorized stage 209 to move sample 208 in a direction continuously at a constant speed. In other embodiments, controller 109 may enable motorized stage 209 to change the speed of the movement of sample 208 over time depending on the steps of scanning process.

[0051] Although Fig. 2A shows that apparatus 104 uses three primary electron beams, it is appreciated that apparatus 104 may use one, two, or more number of primary electron beams. The present disclosure does not limit the number of primary electron beams used in apparatus 104. In some embodiments, apparatus 104 may be a SEM used for lithography. In some embodiments, electron beam tool 104 may be a single -beam system or a multi-beam system.

[0052] For example, as shown in Fig. 2B, an electron beam tool 100B (also referred to herein as apparatus 100B) may be a single-beam inspection tool that is used in EBI system 10, consistent with embodiments of the present disclosure. Apparatus 100B includes a wafer holder 136 supported by motorized stage 134 to hold a wafer 150 to be inspected. Electron beam tool 100B includes an electron emitter, which may comprise a cathode 103, an anode 121, and a gun aperture 122. Electron beam tool 100B further includes a beam limit aperture 125, a condenser lens 126, a column aperture 135, an objective lens assembly 132, and a detector 144. Objective lens assembly 132, in some embodiments, may be a modified SORIL lens, which includes a pole piece 132a, a control electrode 132b, a deflector 132c, and an exciting coil 132d. In an imaging process, an electron beam 161 emanating from the tip of cathode 103 may be accelerated by anode 121 voltage, pass through gun aperture 122, beam limit aperture 125, condenser lens 126, and be focused into a probe spot 170 by the modified SORIL lens and impinge onto the surface of wafer 150. Probe spot 170 may be scanned across the surface of wafer 150 by a deflector, such as deflector 132c or other deflectors in the SORIL lens. Secondary or scattered primary particles, such as secondary electrons or scattered primary electrons emanated from the wafer surface may be collected by detector 144 to determine intensity of the beam and so that an image of an area of interest on wafer 150 may be reconstructed.

[0053] There may also be provided an image processing system 199 that includes an image acquirer 120, a storage 130, and controller 109. Image acquirer 120 may comprise one or more processors. For example, image acquirer 120 may comprise a computer, server, mainframe host, terminals, personal computer, any kind of mobile computing devices, and the like, or a combination thereof. Image acquirer 120 may connect with detector 144 of electron beam tool 100B through a medium such as an electrical conductor, optical fiber cable, portable storage media, IR, Bluetooth, internet, wireless network, wireless radio, or a combination thereof. Image acquirer 120 may receive a signal from detector 144 and may construct an image. Image acquirer 120 may thus acquire images of wafer 150. Image acquirer 120 may also perform various post-processing functions, such as generating contours, superimposing indicators on an acquired image, and the like. Image acquirer 120 may be configured to perform adjustments of brightness and contrast, etc. of acquired images. Storage 130 may be a storage medium such as a hard disk, random access memory (RAM), cloud storage, other types of computer readable memory, and the like. Storage 130 may be coupled with image acquirer 120 and may be used for saving scanned raw image data as original images, and post-processed images. Image acquirer 120 and storage 130 may be connected to controller 109. In some embodiments, image acquirer 120, storage 130, and controller 109 may be integrated together as one electronic control unit.

[0054] In some embodiments, image acquirer 120 may acquire one or more images of a sample based on an imaging signal received from detector 144. An imaging signal may correspond to a scanning operation for conducting charged particle imaging. An acquired image may be a single image comprising a plurality of imaging areas that may contain various features of wafer 150. The single image may be stored in storage 130. Imaging may be performed on the basis of imaging frames.

[0055] The condenser and illumination optics of the electron beam tool may comprise or be supplemented by electromagnetic quadrupole electron lenses. For example, as shown in Fig. 2B, electron beam tool 100B may comprise a first quadrupole lens 148 and a second quadrupole lens 158. In some embodiments, the quadrupole lenses are used for controlling the electron beam. For example, first quadrupole lens 148 can be controlled to adjust the beam current and second quadrupole lens 158 can be controlled to adjust the beam spot size and beam shape.

[0056] Fig. 2B illustrates a charged particle beam apparatus in which an inspection system may use a single primary beam that may be configured to generate secondary electrons by interacting with wafer 150. Detector 144 may be placed along optical axis 105, as in the embodiment shown in Fig. 2B. The primary electron beam may be configured to travel along optical axis 105. Accordingly, detector 144 may include a hole at its center so that the primary electron beam may pass through to reach wafer 150. [0057] Reference is now made to Fig. 3A, which illustrates a schematic representation of an exemplary structure of a detector 300, consistent with embodiments of the present disclosure. Detector 300 may be provided as detector 144 or electron detection device 240 with reference to Fig. 2A and Fig. 2B. While one array is shown in Fig. 3A, it is appreciated that detector 300 may include multiple arrays, such as one array for each secondary electron beam.

[0058] Detector 300 may comprise an array of detection elements, including detection elements 311, 312, and 313. The detection elements may be arranged in a planar, two-dimensional array, the plane of the array being substantially perpendicular to an incidence direction of incoming charged particles. In some embodiments, detector 300 may be arranged so as to be inclined relative to the incidence direction. [0059] Detector 300 may comprise a substrate 310. Substrate 310 may be a semiconductor substrate that may include the detection elements. A detection element may be a diode. A detection element may also be an element similar to a diode that can convert incident energy into a measurable signal. The detection elements may comprise, for example, a PIN diode, an avalanche diode, an electron multiplier tube (EMT), etc., or combinations thereof. Additionally, the term “detection element” may include or cover “sensing element,” “sensor element,” “detection cell,” or “detector segment,” etc. In some embodiments, a pixel on the detector can be a detection element.

[0060] An area 325 may be provided between adjacent detection elements. Area 325 may be an isolation area to isolate the sides or corners of neighboring detection elements from one another. Area 325 may comprise an insulating material that is a material different from that of other areas of the detection surface of detector 300. Area 325 may be provided as a cross-shaped area as seen in the plane view of Fig. 3A. Area 325 may be provided as a square. In some embodiments, area 325 may not be provided between adjacent sides of detection elements. For example, in some embodiments, there may be no isolation area provided on a detection surface of a detector.

[0061] Detection elements may generate an electric signal commensurate with charged particles received in the active area of a detection element. For example, a detection element may generate an electric current signal commensurate with the energy of a received electron. A pre-processing circuit may convert the generated current signal into a voltage that may represent the intensity of an electron beam spot or a part thereof. The pre-processing circuitry may comprise, for example, pre-amp circuitries. Pre-amp circuitries may include, for example, a charge transfer amplifier (CTA), a transimpedance amplifier (TIA), or an impedance conversion circuit coupled with a CTA or a TIA. In some embodiments, signal processing circuitry may be provided that provides an output signal in arbitrary units on a timewise basis. There may be provided one or a plurality of substrates, such as dies, that may form circuit layers for processing the output of detection elements. The dies may be stacked together in a thickness direction of the detector. Other circuitries may also be provided for other functions. For example, switch actuating circuitries may be provided that may control switching elements for connecting detection elements to one another.

[0062] Reference is now made to Fig. 3B, which shows a schematic illustration of a cross-sectional structure of a substrate 310, which may be an example of a structure included in a PIN detector, consistent with embodiments of the present disclosure. Substrate 310 may comprise one or more layers. For example, substrate 310 may be configured to have a plurality of layers stacked in a thickness direction, the thickness direction being substantially parallel to an incidence direction of an electron beam. In some embodiments, substrate 310 may have a plurality of layers stacked in a direction perpendicular to the incidence direction of an electron beam. Substrate 310 may be provided with a sensor surface 301 for receiving incident charged particles. Detection elements (for example detection elements 311, 312, and 313) may be provided in a sensing layer of substrate 310. Area 325 may be provided between adjacent detection elements. For example, substrate 310 may comprise a trench, or other structure that is made of or filled with insulating material. In some embodiments, area 325 may extend fully or partially through substrate 310.

[0063] As shown in Fig. 3C, in some embodiments, area 325 may not be provided between detection elements, consistent with embodiments of the present disclosure. For example, there may be no insulating material provided between the sides of adjacent detection elements in cross-sectional view. The plurality of detection elements may be contiguous in cross-sectional view. Isolation between adjacent detection elements may still be achieved by other means, such as by controlling electrical field. For example, electrical field may be controlled between each detection element.

[0064] Although the figures may show detection elements 311, 312, and 313 as discrete units, such divisions may not actually be present. For example, the detection elements of a detector may be formed by a semiconductor device constituting a PIN diode device. The PIN diode device may be manufactured as a substrate with a plurality of layers including a p-type region, an intrinsic region, and an n-type region. One or more of such layers may be contiguous in cross-sectional view. In some embodiments, however, detection elements may be provided with physical separation between them. Further layers may also be provided in addition to the sensor layer, such as a circuit layer, and a read-out layer, for example.

[0065] As one example of a further layer, detector 300 may be provided with one or more circuit layers adjacent to the sensor layer. The one or more circuit layers may comprise line wires, interconnects, and various electronic circuit components. The one or more circuit layers may comprise a processing system. The one or more circuit layers may comprise signal processing circuitries. The one or more circuit layers may be configured to receive the output current detected from detection elements in the sensor layer. The one or more circuit layers and the sensor layer may be provided in the same or separate dies, for example.

[0066] Fig. 3D shows a schematic illustration of an individual detection element, which may be an example of one of detection elements 311, 312, and 313, consistent with embodiments of the present disclosure. For example, in Fig. 3D, a detection element 311 A is shown. Detection element 311 A may include a semiconductor structure of a p-type layer 321, an intrinsic layer 322, and an n-type layer 323. Detection element 311 A may include two terminals, such as an anode and a cathode. Detection element 311 A may be reverse biased, and a depletion region 330 may form and may span part of the length of p-type layer 321, substantially the entire length of intrinsic layer 322, and part of the length of n-type layer 323. In depletion region 330, charge carriers may be removed, and new charge carriers generated in depletion region 330 may be swept away according to their charge. For example, when an incoming charged particle reaches sensor surface 301, electron-hole pairs may be created, and a hole 351 may be attracted toward p-type layer 321 while an electron 352 may be attracted toward n-type layer 323. In some embodiments, a passivation layer may be provided on sensor surface 301.

[0067] In operation, a depletion region of a detection element may function as a capture region. An incoming charged particle may interact with the semiconductor material in the depletion region and generate new charges. For example, the detection element may be configured such that a charged particle having a certain amount of energy or greater may cause electrons of the lattice of the semiconductor material to be dislodged, thus creating electron-hole pairs. The resulting electrons and holes may be caused to travel in opposite directions due to, for example, an electric field in the depletion region. Generation of carriers that travel toward terminals of the detection element may correspond to current flow in the detection element.

[0068] In a comparative example, a photodiode may be configured to generate electric charge in response to receiving photons. A photon may have energy that corresponds to its wavelength or frequency. Typically, a photon in the visible light spectrum may have energy on the order of about 1 eV. However, in a semiconductor photodiode, it is typical that about 3.6 eV may be required to generate one electron-hole pair. Therefore, photodiodes may encounter difficulties in detecting current generation such as the following.

[0069] In general, a level of energy of a photon may be similar to that required to generate an electronhole pair in a semiconductor photodiode. Thus, in order to generate electric current stably and reliably, it may be necessary that photons of high energy be incident on a semiconductor photodiode. A photon may have energy sufficient to generate one electron-hole pair when its frequency is at or above a certain level.

[0070] Furthermore, the electric current generated by electron-hole pairs in response to photon arrival events may be relatively low. Current generated in response to photon arrival events may not be sufficient to overcome background noise. Some diodes, such as a photodiode biased to avalanche or Geiger counting mode, may employ amplification to generate a larger level of electric current so that a useful detection signal can be generated. In some embodiments, a photodiode may be biased to avalanche operation mode. In some embodiments, amplification may be provided by gain blocks attached to the photodiode. An avalanche effect may be generated from strong internal electric fields resulting from bias voltage. The avalanche effect may be used to achieve amplification due to impact ionization.

[0071] Figs. 4A-4C show schematic illustrations of a process to develop a conventional designed electron detector developed at higher temperatures. For example, Fig. 4A shows a detection element 400 comprising a substrate 403, conventionally composed of Silicon (Si), Germanium (Ge), SiGe, Gallium Arsenide (GaAs), etc. with a vertical PIN diode, where the PIN diode includes p-type regions 404 and 405, and an n-type region 406 that may be prepared for processing. The PIN diode may be formed on a front side 401 of detection element 400. While the figures and corresponding description refer to a vertical PIN diode, it is appreciated that a lateral PIN diode can also be used in which region 404 is an n-type region, region 405 is a p-type region and region 406 is an intrinsic region. Moreover, while the figures and correspond description refer to a PIN diode, it is appreciated that a NIP diode can be used.

[0072] As shown in Fig. 4B, the process then proceeds to invert detection element 400 to deposit a passivation layer 407 to backside 402 of detection element 400. In conventional systems, passivation layer 407 is composed of Boron, which is formed at high temperatures of 700 °C on a backside 402 of detection element 400.

[0073] As shown in Fig. 4C, the process then proceeds to invert detection element 400 again to perform processing on the front side 401. As shown in Fig. 4C, metal interconnects 408-410 can be applied to detection element 400. In conventional systems, interconnects 408-410 are applied to detection element 400 after the passivation layer 407 is applied because higher temperatures of 700 °C would damage metal interconnects 408-410. Moreover, conventional processing technique limit the library of the types of interconnects that can sustain high temperature processing of 700 °C. [0074] As stated above, the disclosed embodiments provide systems and methods that address some or all of these disadvantages of conventional systems by providing a new passivation layer that can be applied (e.g., deposited or synthesized) at lower temperatures. This passivation layer is configured to reduce leakage caused by surface defects and to reduce electron capture caused by surface traps. By being able to apply the passivation layer at lower temperatures, the development process can be simplified, costs can be reduced, and the passivation layer acts as a defect neutralizing passivation. Figs. 5A and 5B show a simplified process to develop a detection element (e.g., detection elements 311, 312, 313), consistent with embodiments of this invention. A first step is shown in Fig. 5A, whereby detection element 500 may include a substrate 503 (e.g., silicon substrate) with a vertical PIN diode, where the PIN diode includes pp-type regions 504 and 505, and an n-type region 506. The PIN diode may be formed on a front side 501 of detection element 500. After the formation of the PIN diode, metal interconnects 507, 508, and 509 may be deposited on top of the PIN diodes formed on a front side 501 of detection element 500 at temperatures no higher than 400 °C. For example, the metal interconnects can be made of Aluminum, which can be damaged at temperatures of 700 °C. While the figures and corresponding description refer to a vertical PIN diode, it is appreciated that a lateral PIN diode can also be used in which region 504 is an n-type region, region 505 is a p-type region and region 506 is an intrinsic region.

[0075] After the interconnects are applied, the process can proceed to deposit a passivation layer 510 on a backside 502 of substrate 503 as shown in Fig. 5B. In some embodiments, the passivation layer 510 may include a novel material of composition (but not limited to) ultra-thin Al-doped Si formed by metal-induced crystallization or layer exchange (from Al(Si X%), where X can vary from 0), CVD (e.g., among other low-pressure CVD and plasma enhanced CVD, etc.) Boron, Indium, Tin, or other metals, semiconductors, or alloys.

[0076] Furthermore, passivation layer 510 may be applied (e.g., deposited or synthesized) on a backside 502 at temperatures lower than 400 °C. In some embodiments the passivation layer 510 may be deposited on the same side as the diodes. Low temperature passivation processes help target the limitation of conventional systems surface defect by creating a defect neutralizing passivation that benefits integration simplicity, allowing passivation with interconnect materials already present. It also can help expand the library of materials used on frontside 501 patterning for gain enhancement. By applying (e.g. by depositing, synthesizing, etc.) the passivation layer at lower temperature, the materials for interconnects can be expanded to include Al, Mo, Co, Cu, Ru, Ni, and their alloys.

[0077] Moreover, the process is simpler as full frontside processing can be performed before processing the backside with a low temperature passivation layer when compared to conventional systems, which require partial frontside processing, then flipping to backside processing at higher temperatures, and then flipping again to apply interconnects on the front side at lower temperatures (as shown in Figs. 4A-4C). [0078] The thickness of passivation layer 510 may be in the 1 nm to 1000 nm range. A thickness closer to 1 nm can adequately passivate the surface interface traps while maintaining a low dead region (a larger thickness results in lower lifetime of the generated charges). On the other hand, a thickness closer to 1000 nm can reduce the sheet resistance and provide better Resistance-Capacitance (R-C) time constant. An optimal thickness is evaluated considering both aspects. In addition, a certain profile of the passivation can be engineered (a gaussian profile or a ERFC profile) to generate a favorable in-built electric field that helps in directing the generated signal charges towards the collecting electrode.

[0079] Reference is now made to Figs. 6A-6C, illustrating another example process of forming a detection element 600 (e.g., such as detection elements 311, 312, 313, 500), consistent with embodiments of the present disclosure.

[0080] For example, a first step is shown in Fig. 6A, whereby detection element 600 may include a substrate 603 (e.g., substrate 503 Fig. 5B) (e.g., bulk silicon, epitaxial silicon, silicon-on-insulator (SOI), or of other soft metal substrate prepared for processing. In some embodiments, substrate 603 may be a thick substrate (e.g., can range from 50 nm - 1mm and, in a selected embodiment, the range is from 500-600 pm) that can act as the intrinsic region 603 (e.g., substrate and intrinsic region 503 of Fig. 5B) of a PIN diode. The PIN diode includes p-type regions 604-605 (e.g., p-type regions 504-505 of Fig. 5B) and a n-type region 606 (e.g., n-type region 506 in Fig. 5B). The PIN diode may be formed on a front side 601 (e.g., front side 501 of Fig. 5B) of detection element 600.

[0081] After the formation of PIN diode on substrate 603, interconnects 607, 608, 609 (e.g., interconnects 507, 508, 509 of Fig. 5B) may be printed onto the frontside 601 (e.g., frontside 501 of Fig. 5B) of the detection element 600 as shown in Fig. 6B. As stated above, metal interconnects 607- 609 may be deposited on top of the PIN diodes formed on a front side 601 of detection element 600 at temperatures no higher than 400 °C. For example, the metal interconnects can be made of Aluminum, which can be damaged at temperatures of 700 °C. Metal interconnects 607-609 can be applied at these lower temperatures due to applying a low temperature passivation layer.

[0082] After the interconnects are applied, the process can proceed to deposit a defect neutralizing passivation layer 610 on an exposed backside 602 of substrate 603 as shown in Fig. 6C. In some embodiments the passivation layer 610 can be deposited on the same side as the diodes. In some embodiments, such as the example shown in Fig. 6C, the substrate 603 may be trimmed by a process of mechanically or chemically trimming (e.g., chemical mechanical planarization, wet stripping, and dry etching) to a thickness of 100 pm (however, the trim may be thinner or thicker than 100 pm as needed).

[0083] Passivation layer 610 (e.g., passivation layer 510 of Fig. 5B) may be formed on the exposed backside 602 of detection element or on the same side as the diodes. Passivation layer 610 may include a novel material of composition (but not limited to) ultra-thin Al-doped Si formed by metal-induced crystallization or layer exchange (from Al(Si X%), where X can vary from 0), CVD (e.g., among other low-pressure CVD and plasma enhanced CVD, etc.) Boron, Indium, Tin, or other metals, semiconductors, or alloys.

[0084] Furthermore, passivation layer 610 may be deposited on the exposed backside 602 at temperatures lower than 400 °C. The passivation layer is configured to reduce leakage caused by surface defects and reduce electron capture caused by surface traps. Low temperature defect neutralizing passivation processes benefit integration simplicity by allowing passivation with interconnect materials already present. It also can help expand the library of materials used on frontside 601 patterning for gain enhancement. By applying the passivation layer at lower temperature, the materials for interconnects can be expanded to include Al, Mo, Co, Cu, Ru, Ni, and their alloys.

[0085] Moreover, the process is simpler as full frontside processing can be performed before processing the backside with a low temperature passivation layer when compared to conventional systems, which require partial frontside processing, then flipping to backside processing at higher temperatures, and then flipping again to apply interconnects on the front side at lower temperatures (as shown in Figs. 4A-4C).

[0086] The embodiments may further be described using the following clauses:

1. A method of forming a passivation layer on an electron detector comprising: applying a passivation material on a surface of a wafer as part of forming the electron detector on the wafer; wherein the wafer is heated to less than 400 °C during the application of the passivation material and during all remaining steps of manufacture of the electron detector.

2. The method of clause 1, wherein heating of the wafer during application of the passivation material is to less than 30 °C.

3. The method of any one of clauses 1 and 2, wherein the passivation material is composed of Al-doped Si or CVD Boron.

4. The method of any one of clauses 1-3, wherein the passivation material is not composed of any of SiN, AlOx, or SiON.

5. The method of any one of clauses 1-3, wherein the passivation material is configured to be substantially transparent to electrons of an electron beam.

6. The method of any one of clauses 1-5, wherein the applied passivation material has a thickness of 1 nm - 1000 nm.

7. The method of any one of clauses 1-6, wherein frontside patterning of the wafer is completed before application of the passivation material on the backside of the wafer.

8. The method of clause 7, wherein frontside patterning includes formation of MOSFET gates.

9. The method of clause 7, wherein frontside patterning includes formation of metal interconnects.

10. The method of any one of clauses 1-7, further comprising forming a PIN or NIP diode on the front side of the wafer before depositing the passivation material on the backside of the wafer.

11. The method of clause 10, wherein the PIN or NIP diode is a vertical diode. 12. The method of clause 10, wherein the PIN or NIP diode is a lateral diode.

13. The method of any one of clauses 1-12, further comprising forming interconnects on the front side of the wafer before applying the passivation material on the backside of the wafer.

14. The method of clause 13, wherein the interconnects are composed of at least one of Al, Mo, Co, Ru, Cu, Ni, or their alloys.

15. A detection element comprising: a substrate comprising a silicon wafer; a diode formed on a first side of the wafer, the diode being configured to facilitate detection of charged particles emitted from a sample being imaged by a charged particle microscope; interconnect formed on the first side of the wafer; and a passivation material formed on a second side of the wafer, the passivation material being formed after the interconnect wires are formed.

16. The detection element of clause 15, wherein the passivation material is composed of Al-doped Si or CVD Boron.

17. The detection element of clause 15, wherein the passivation material is not composed of SiN, A1O_X, or SiON.

18. The detection element of clause 15, wherein the passivation material is configured to be substantially transparent to electrons of an electron beam.

19. The detection element of any one of clauses 15-18, wherein the passivation material has a thickness of 1 nm - 1000 nm.

20. The detection element of any one of clauses 15-19, wherein the interconnects are composed of at least one of Al, Mo, Co, Ru, Cu, Ni, or their alloys.

21. The detection element of any one of clauses 15-20, wherein the passivation material is formed on the second side of the wafer by heating the wafer to less than 400 °C during application of the passivation material.

22. The detection element of any one of clauses 15-21, wherein the passivation material is formed on the second side of the wafer by heating the wafer to less than 30 °C during application of the passivation material.

23. The detection element of any one of clauses 15-22, wherein the diode is a PIN diode or a NIP diode.

24. The detection element of clause 23, wherein the PIN or NIP diode is a vertical diode.

25. The detection element of clause 23, wherein the PIN or NIP diode is a lateral diode.

26. A detector comprising: a plurality of detection elements each comprising: a substrate comprising a silicon wafer; a diode formed on a first side of the wafer, the diode being configured to facilitate detection of charged particles emitted from a sample being imaged by a charged particle microscope; interconnect formed on the first side of the wafer; and a passivation material formed on the first side or a second side of the wafer, the passivation material being formed after the interconnect wires are formed.

27. The detector of clause 26, wherein the passivation material is composed of Al-doped Si or CVD Boron.

28. The detector of any one of clauses 26 and 27, wherein the passivation material is not composed of SiN, A1O_X, or SiON.

29. The detector of any one of clauses 26-28, wherein the passivation material is configured to the substantially transparent to electrons of an electron beam.

30. The detector of any one of clauses 26-29, wherein the passivation material has a thickness of 1 nm - 1000 nm.

31. The detector of any one of clauses 26-30, wherein the interconnects are composed of at least of Al, Mo, Co, Ru, Cu, Ni, or their alloys.

32. The detector of any one of clauses 26-31, wherein the passivation material is formed on the second side of the wafer by heating the wafer to less than 400 °C during application of the passivation material.

33. The detector of any one of clauses 26-32, wherein the passivation material is formed on the second side of the wafer by heating the wafer to less than 30 °C during application of the passivation material.

34. The detector of any one of clauses 26-33, wherein the diode is a PIN diode or a NIP diode.

35. The detector of clause 34, wherein the PIN or NIP diode is a vertical diode.

36. The detector of clause 34, wherein the PIN or NIP diode is a lateral diode.

37. A charged particle beam microscope comprising: a detector comprising: a plurality of detection elements each comprising: a substrate comprising a silicon wafer; a diode formed on a first side of the wafer, the diode being configured to facilitate detection of charged particles emitted from a sample being imaged by a charged particle microscope; interconnect formed on the first side of the wafer; and a passivation material formed on a second side of the wafer, the passivation material being formed after the interconnect wires are formed.

38. The charged particle beam microscope of clause 37, wherein the passivation material is composed of Al-doped Si or CVD Boron.

39. The charged particle beam microscope of any one of clauses 37 and 38, wherein the passivation material is not composed of SiN, A1O_X, or SiON.

40. The charged particle beam microscope of any one of clauses 37-39, wherein the passivation material is configured to be substantially transparent to electrons of an electron beam.

41. The charged particle beam microscope of any one of clauses 37-40, wherein the passivation material has a thickness of 1 nm - 1000 nm. 42. The charged particle beam microscope of any one of clauses 37-41, wherein the interconnects are composed of at least of Al, Mo, Co, Ru, Cu, Ni, or their alloys.

43. The charged particle beam microscope of any one of clauses 37-42, wherein the passivation material is formed on the second side of the wafer by heating the wafer to less than 400 °C during application of the passivation material.

44. The charged particle beam microscope of any one of clauses 37-43, wherein the passivation material is formed on the second side of the wafer by heating the wafer to less than 30 °C during application of the passivation material.

45. The charged particle beam microscope of any one of clauses 37-44, wherein the diode is a PIN diode or a NIP diode.

46. The charged particle beam microscope of clause 45, wherein the PIN or NIP diode is a vertical diode.

47. The charged particle beam microscope of clause 45, wherein the PIN or NIP diode is a lateral diode.

48. The method of clause 1, wherein the passivation material is configured to provide defect neutralizing passivation.

49. The detection element of clause 15, wherein the passivation material is configured to provide defect neutralizing passivation.

50. The detector of clause 26, wherein the passivation material is configured to provide defect neutralizing passivation.

51. The charged particle beam microscope of clause 37, wherein the passivation material is configured to provide defect neutralizing passivation.

[0087] It will be appreciated that the embodiments of the present disclosure are not limited to the exact construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. A method of forming a passivation layer on an electron detector comprising: applying a passivation material on a surface of a wafer as part of forming the electron detector on the wafer; wherein the wafer is heated to less than 400 °C during application of the passivation material and during all remaining steps of manufacture of the electron detector.

2. The method of claim 1, wherein heating of the wafer during application of the passivation material is to less than 30 °C.

3. The method of claim 1, wherein the passivation material is composed of Al-doped Si or CVD Boron.

4. The method of claim 1, wherein the passivation material is not composed of any of SiN, AlOx, or SiON.

5. The method of claim 1, wherein the passivation material is configured to be substantially transparent to electrons of an electron beam.

6. The method of claim 1, wherein the applied passivation material has a thickness of 1 nm - 1000 nm.

7. The method of claim 1, wherein frontside patterning of the wafer is completed before application of the passivation material on the backside of the wafer.

8. The method of claim 7, wherein frontside patterning includes formation of MOSFET gates.

9. The method of claim 7, wherein frontside patterning includes formation of metal interconnects.

10. The method of claim 1, further comprising forming a PIN or NIP diode on the front side of the wafer before application of the passivation material on the backside of the wafer.

11. The method of claim 10, wherein the PIN or NIP diode is a vertical diode.

12. The method of claim 10, wherein the PIN or NIP diode is a lateral diode.

13. The method of claim 1, further comprising forming interconnects on the front side of the wafer before application of the passivation material on the backside of the wafer.

14. The method of claim 13, wherein the interconnects are composed of at least one of Al, Mo, Co, Ru, Cu, Ni, or their alloys.

15. A detection element comprising: a substrate comprising a silicon wafer; a diode formed on a first side of the wafer, the diode being configured to facilitate detection of charged particles emitted from a sample being imaged by a charged particle microscope; interconnect formed on the first side of the wafer; and a passivation material formed on a second side of the wafer, the passivation material being formed after the interconnect is formed.